Embedded HandbookApps
All sections › Appendices
STM32F103 · level reference · 105 min read
Open in the interactive handbook

Appendix A. STM32F1 register maps

Registers and bits of the main STM32F1 blocks, taken from the family header — the one included in every project. Offsets are computed from the *_TypeDef structures (the old-style F1 header has no register comments), bits from the definitions in the same file; each bit description comes from its comment, in English, as in the reference manual. 16-bit registers are common on the F1 — this is not a mistake, the upper 16 bits of the word are reserved there.

How to read: the offset is from the block's base address; 31:16 is a bit field from 16 to 31; a single number is a single bit. The number in brackets in a block heading is the section where the block is covered.

STM32F103 peripherals by bus: bus bases and the appendix block offsets, as in a debugger window

Register widths in appendix A by block: 104 of 32 bits, 55 of 16, 1 of 8; on the USART each 16-bit register sits in the lower half of its word, offsets in steps of 4

RCC — Clocks (section 6)

Register Offset Bits Purpose
CR 0x00 32
RCC_CR_HSION 0 Internal High Speed clock enable
RCC_CR_HSIRDY 1 Internal High Speed clock ready flag
RCC_CR_HSITRIM 3:7 Internal High Speed clock trimming
RCC_CR_HSICAL 8:15 Internal High Speed clock Calibration
RCC_CR_HSEON 16 External High Speed clock enable
RCC_CR_HSERDY 17 External High Speed clock ready flag
RCC_CR_HSEBYP 18 External High Speed clock Bypass
RCC_CR_CSSON 19 Clock Security System enable
RCC_CR_PLLON 24 PLL enable
RCC_CR_PLLRDY 25 PLL clock ready flag
RCC_CR_PLL2ON 26 PLL2 enable
RCC_CR_PLL2RDY 27 PLL2 clock ready flag
RCC_CR_PLL3ON 28 PLL3 enable
RCC_CR_PLL3RDY 29 PLL3 clock ready flag
CFGR 0x04 32
RCC_CFGR_SW 0:1 SW[1:0] bits (System clock Switch)
RCC_CFGR_SW_0 0 Bit 0
RCC_CFGR_SW_1 1 Bit 1
RCC_CFGR_SW_HSI — HSI selected as system clock
RCC_CFGR_SW_HSE 0 HSE selected as system clock
RCC_CFGR_SW_PLL 1 PLL selected as system clock
RCC_CFGR_SWS 2:3 SWS[1:0] bits (System Clock Switch Status)
RCC_CFGR_SWS_0 2 Bit 0
RCC_CFGR_SWS_1 3 Bit 1
RCC_CFGR_SWS_HSI — HSI oscillator used as system clock
RCC_CFGR_SWS_HSE 2 HSE oscillator used as system clock
RCC_CFGR_SWS_PLL 3 PLL used as system clock
RCC_CFGR_HPRE 4:7 HPRE[3:0] bits (AHB prescaler)
RCC_CFGR_HPRE_0 4 Bit 0
RCC_CFGR_HPRE_1 5 Bit 1
RCC_CFGR_HPRE_2 6 Bit 2
RCC_CFGR_HPRE_3 7 Bit 3
RCC_CFGR_HPRE_DIV1 — SYSCLK not divided
RCC_CFGR_HPRE_DIV2 7 SYSCLK divided by 2
RCC_CFGR_HPRE_DIV4 4:7 SYSCLK divided by 4
RCC_CFGR_HPRE_DIV8 5:7 SYSCLK divided by 8
RCC_CFGR_HPRE_DIV16 4:7 SYSCLK divided by 16
RCC_CFGR_HPRE_DIV64 6:7 SYSCLK divided by 64
RCC_CFGR_HPRE_DIV128 4:7 SYSCLK divided by 128
RCC_CFGR_HPRE_DIV256 5:7 SYSCLK divided by 256
RCC_CFGR_HPRE_DIV512 4:7 SYSCLK divided by 512
RCC_CFGR_PPRE1 8:10 PRE1[2:0] bits (APB1 prescaler)
RCC_CFGR_PPRE1_0 8 Bit 0
RCC_CFGR_PPRE1_1 9 Bit 1
RCC_CFGR_PPRE1_2 10 Bit 2
RCC_CFGR_PPRE1_DIV1 — HCLK not divided
RCC_CFGR_PPRE1_DIV2 10 HCLK divided by 2
RCC_CFGR_PPRE1_DIV4 8:10 HCLK divided by 4
RCC_CFGR_PPRE1_DIV8 9:10 HCLK divided by 8
RCC_CFGR_PPRE1_DIV16 8:10 HCLK divided by 16
RCC_CFGR_PPRE2 11:13 PRE2[2:0] bits (APB2 prescaler)
RCC_CFGR_PPRE2_0 11 Bit 0
RCC_CFGR_PPRE2_1 12 Bit 1
RCC_CFGR_PPRE2_2 13 Bit 2
RCC_CFGR_PPRE2_DIV1 — HCLK not divided
RCC_CFGR_PPRE2_DIV2 13 HCLK divided by 2
RCC_CFGR_PPRE2_DIV4 11:13 HCLK divided by 4
RCC_CFGR_PPRE2_DIV8 12:13 HCLK divided by 8
RCC_CFGR_PPRE2_DIV16 11:13 HCLK divided by 16
RCC_CFGR_ADCPRE 14:15 ADCPRE[1:0] bits (ADC prescaler)
RCC_CFGR_ADCPRE_0 14 Bit 0
RCC_CFGR_ADCPRE_1 15 Bit 1
RCC_CFGR_ADCPRE_DIV2 — PCLK2 divided by 2
RCC_CFGR_ADCPRE_DIV4 14 PCLK2 divided by 4
RCC_CFGR_ADCPRE_DIV6 15 PCLK2 divided by 6
RCC_CFGR_ADCPRE_DIV8 14:15 PCLK2 divided by 8
RCC_CFGR_PLLSRC 16 PLL entry clock source
RCC_CFGR_PLLXTPRE 17 HSE divider for PLL entry
RCC_CFGR_PLLMULL 18:21 PLLMUL[3:0] bits (PLL multiplication factor)
RCC_CFGR_PLLMULL_0 18 Bit 0
RCC_CFGR_PLLMULL_1 19 Bit 1
RCC_CFGR_PLLMULL_2 20 Bit 2
RCC_CFGR_PLLMULL_3 21 Bit 3
RCC_CFGR_PLLSRC_HSI_Div2 — HSI clock divided by 2 selected as PLL entry clock source
RCC_CFGR_PLLSRC_PREDIV1 16 PREDIV1 clock selected as PLL entry clock source
RCC_CFGR_PLLXTPRE_PREDIV1 — PREDIV1 clock not divided for PLL entry
RCC_CFGR_PLLXTPRE_PREDIV1_Div2 17 PREDIV1 clock divided by 2 for PLL entry
RCC_CFGR_PLLMULL4 19 PLL input clock * 4
RCC_CFGR_PLLMULL5 18:19 PLL input clock * 5
RCC_CFGR_PLLMULL6 20 PLL input clock * 6
RCC_CFGR_PLLMULL7 18:20 PLL input clock * 7
RCC_CFGR_PLLMULL8 19:20 PLL input clock * 8
RCC_CFGR_PLLMULL9 18:20 PLL input clock * 9
RCC_CFGR_PLLMULL6_5 18:21 PLL input clock * 6.5
RCC_CFGR_OTGFSPRE 22 USB OTG FS prescaler
RCC_CFGR_MCO 24:27 MCO[3:0] bits (Microcontroller Clock Output)
RCC_CFGR_MCO_0 24 Bit 0
RCC_CFGR_MCO_1 25 Bit 1
RCC_CFGR_MCO_2 26 Bit 2
RCC_CFGR_MCO_3 27 Bit 3
RCC_CFGR_MCO_NOCLOCK — No clock
RCC_CFGR_MCO_SYSCLK 26 System clock selected as MCO source
RCC_CFGR_MCO_HSI 24:26 HSI clock selected as MCO source
RCC_CFGR_MCO_HSE 25:26 HSE clock selected as MCO source
RCC_CFGR_MCO_PLLCLK_Div2 24:26 PLL clock divided by 2 selected as MCO source
RCC_CFGR_MCO_PLL2CLK 27 PLL2 clock selected as MCO source
RCC_CFGR_MCO_PLL3CLK_Div2 24:27 PLL3 clock divided by 2 selected as MCO source
RCC_CFGR_MCO_Ext_HSE 25:27 XT1 external 3-25 MHz oscillator clock selected as MCO source
RCC_CFGR_MCO_PLL3CLK 24:27 PLL3 clock selected as MCO source
RCC_CFGR_PLLSRC_HSI_Div2 — HSI clock divided by 2 selected as PLL entry clock source
RCC_CFGR_PLLSRC_PREDIV1 16 PREDIV1 clock selected as PLL entry clock source
RCC_CFGR_PLLXTPRE_PREDIV1 — PREDIV1 clock not divided for PLL entry
RCC_CFGR_PLLXTPRE_PREDIV1_Div2 17 PREDIV1 clock divided by 2 for PLL entry
RCC_CFGR_PLLMULL2 — PLL input clock*2
RCC_CFGR_PLLMULL3 18 PLL input clock*3
RCC_CFGR_PLLMULL4 19 PLL input clock*4
RCC_CFGR_PLLMULL5 18:19 PLL input clock*5
RCC_CFGR_PLLMULL6 20 PLL input clock*6
RCC_CFGR_PLLMULL7 18:20 PLL input clock*7
RCC_CFGR_PLLMULL8 19:20 PLL input clock*8
RCC_CFGR_PLLMULL9 18:20 PLL input clock*9
RCC_CFGR_PLLMULL10 21 PLL input clock10
RCC_CFGR_PLLMULL11 18:21 PLL input clock*11
RCC_CFGR_PLLMULL12 19:21 PLL input clock*12
RCC_CFGR_PLLMULL13 18:21 PLL input clock*13
RCC_CFGR_PLLMULL14 20:21 PLL input clock*14
RCC_CFGR_PLLMULL15 18:21 PLL input clock*15
RCC_CFGR_PLLMULL16 19:21 PLL input clock*16
RCC_CFGR_MCO 24:26 MCO[2:0] bits (Microcontroller Clock Output)
RCC_CFGR_MCO_0 24 Bit 0
RCC_CFGR_MCO_1 25 Bit 1
RCC_CFGR_MCO_2 26 Bit 2
RCC_CFGR_MCO_NOCLOCK — No clock
RCC_CFGR_MCO_SYSCLK 26 System clock selected as MCO source
RCC_CFGR_MCO_HSI 24:26 HSI clock selected as MCO source
RCC_CFGR_MCO_HSE 25:26 HSE clock selected as MCO source
RCC_CFGR_MCO_PLL 24:26 PLL clock divided by 2 selected as MCO source
RCC_CFGR_PLLSRC_HSI_Div2 — HSI clock divided by 2 selected as PLL entry clock source
RCC_CFGR_PLLSRC_HSE 16 HSE clock selected as PLL entry clock source
RCC_CFGR_PLLXTPRE_HSE — HSE clock not divided for PLL entry
RCC_CFGR_PLLXTPRE_HSE_Div2 17 HSE clock divided by 2 for PLL entry
RCC_CFGR_PLLMULL2 — PLL input clock*2
RCC_CFGR_PLLMULL3 18 PLL input clock*3
RCC_CFGR_PLLMULL4 19 PLL input clock*4
RCC_CFGR_PLLMULL5 18:19 PLL input clock*5
RCC_CFGR_PLLMULL6 20 PLL input clock*6
RCC_CFGR_PLLMULL7 18:20 PLL input clock*7
RCC_CFGR_PLLMULL8 19:20 PLL input clock*8
RCC_CFGR_PLLMULL9 18:20 PLL input clock*9
RCC_CFGR_PLLMULL10 21 PLL input clock10
RCC_CFGR_PLLMULL11 18:21 PLL input clock*11
RCC_CFGR_PLLMULL12 19:21 PLL input clock*12
RCC_CFGR_PLLMULL13 18:21 PLL input clock*13
RCC_CFGR_PLLMULL14 20:21 PLL input clock*14
RCC_CFGR_PLLMULL15 18:21 PLL input clock*15
RCC_CFGR_PLLMULL16 19:21 PLL input clock*16
RCC_CFGR_USBPRE 22 USB Device prescaler
RCC_CFGR_MCO 24:26 MCO[2:0] bits (Microcontroller Clock Output)
RCC_CFGR_MCO_0 24 Bit 0
RCC_CFGR_MCO_1 25 Bit 1
RCC_CFGR_MCO_2 26 Bit 2
RCC_CFGR_MCO_NOCLOCK — No clock
RCC_CFGR_MCO_SYSCLK 26 System clock selected as MCO source
RCC_CFGR_MCO_HSI 24:26 HSI clock selected as MCO source
RCC_CFGR_MCO_HSE 25:26 HSE clock selected as MCO source
RCC_CFGR_MCO_PLL 24:26 PLL clock divided by 2 selected as MCO source
CIR 0x08 32
RCC_CIR_LSIRDYF 0 LSI Ready Interrupt flag
RCC_CIR_LSERDYF 1 LSE Ready Interrupt flag
RCC_CIR_HSIRDYF 2 HSI Ready Interrupt flag
RCC_CIR_HSERDYF 3 HSE Ready Interrupt flag
RCC_CIR_PLLRDYF 4 PLL Ready Interrupt flag
RCC_CIR_CSSF 7 Clock Security System Interrupt flag
RCC_CIR_LSIRDYIE 8 LSI Ready Interrupt Enable
RCC_CIR_LSERDYIE 9 LSE Ready Interrupt Enable
RCC_CIR_HSIRDYIE 10 HSI Ready Interrupt Enable
RCC_CIR_HSERDYIE 11 HSE Ready Interrupt Enable
RCC_CIR_PLLRDYIE 12 PLL Ready Interrupt Enable
RCC_CIR_LSIRDYC 16 LSI Ready Interrupt Clear
RCC_CIR_LSERDYC 17 LSE Ready Interrupt Clear
RCC_CIR_HSIRDYC 18 HSI Ready Interrupt Clear
RCC_CIR_HSERDYC 19 HSE Ready Interrupt Clear
RCC_CIR_PLLRDYC 20 PLL Ready Interrupt Clear
RCC_CIR_CSSC 23 Clock Security System Interrupt Clear
RCC_CIR_PLL2RDYF 5 PLL2 Ready Interrupt flag
RCC_CIR_PLL3RDYF 6 PLL3 Ready Interrupt flag
RCC_CIR_PLL2RDYIE 13 PLL2 Ready Interrupt Enable
RCC_CIR_PLL3RDYIE 14 PLL3 Ready Interrupt Enable
RCC_CIR_PLL2RDYC 21 PLL2 Ready Interrupt Clear
RCC_CIR_PLL3RDYC 22 PLL3 Ready Interrupt Clear
APB2RSTR 0x0C 32
RCC_APB2RSTR_AFIORST 0 Alternate Function I/O reset
RCC_APB2RSTR_IOPARST 2 I/O port A reset
RCC_APB2RSTR_IOPBRST 3 I/O port B reset
RCC_APB2RSTR_IOPCRST 4 I/O port C reset
RCC_APB2RSTR_IOPDRST 5 I/O port D reset
RCC_APB2RSTR_ADC1RST 9 ADC 1 interface reset
RCC_APB2RSTR_ADC2RST 10 ADC 2 interface reset
RCC_APB2RSTR_TIM1RST 11 TIM1 Timer reset
RCC_APB2RSTR_SPI1RST 12 SPI 1 reset
RCC_APB2RSTR_USART1RST 14 USART1 reset
RCC_APB2RSTR_TIM15RST 16 TIM15 Timer reset
RCC_APB2RSTR_TIM16RST 17 TIM16 Timer reset
RCC_APB2RSTR_TIM17RST 18 TIM17 Timer reset
RCC_APB2RSTR_IOPERST 6 I/O port E reset
RCC_APB2RSTR_IOPFRST 7 I/O port F reset
RCC_APB2RSTR_IOPGRST 8 I/O port G reset
RCC_APB2RSTR_TIM8RST 13 TIM8 Timer reset
RCC_APB2RSTR_ADC3RST 15 ADC3 interface reset
RCC_APB2RSTR_IOPFRST 7 I/O port F reset
RCC_APB2RSTR_IOPGRST 8 I/O port G reset
RCC_APB2RSTR_TIM9RST 19 TIM9 Timer reset
RCC_APB2RSTR_TIM10RST 20 TIM10 Timer reset
RCC_APB2RSTR_TIM11RST 21 TIM11 Timer reset
APB1RSTR 0x10 32
RCC_APB1RSTR_TIM2RST 0 Timer 2 reset
RCC_APB1RSTR_TIM3RST 1 Timer 3 reset
RCC_APB1RSTR_WWDGRST 11 Window Watchdog reset
RCC_APB1RSTR_USART2RST 17 USART 2 reset
RCC_APB1RSTR_I2C1RST 21 I2C 1 reset
RCC_APB1RSTR_CAN1RST 25 CAN1 reset
RCC_APB1RSTR_BKPRST 27 Backup interface reset
RCC_APB1RSTR_PWRRST 28 Power interface reset
RCC_APB1RSTR_TIM4RST 2 Timer 4 reset
RCC_APB1RSTR_SPI2RST 14 SPI 2 reset
RCC_APB1RSTR_USART3RST 18 USART 3 reset
RCC_APB1RSTR_I2C2RST 22 I2C 2 reset
RCC_APB1RSTR_USBRST 23 USB Device reset
RCC_APB1RSTR_TIM5RST 3 Timer 5 reset
RCC_APB1RSTR_TIM6RST 4 Timer 6 reset
RCC_APB1RSTR_TIM7RST 5 Timer 7 reset
RCC_APB1RSTR_SPI3RST 15 SPI 3 reset
RCC_APB1RSTR_UART4RST 19 UART 4 reset
RCC_APB1RSTR_UART5RST 20 UART 5 reset
RCC_APB1RSTR_DACRST 29 DAC interface reset
RCC_APB1RSTR_TIM6RST 4 Timer 6 reset
RCC_APB1RSTR_TIM7RST 5 Timer 7 reset
RCC_APB1RSTR_DACRST 29 DAC interface reset
RCC_APB1RSTR_CECRST 30 CEC interface reset
RCC_APB1RSTR_TIM5RST 3 Timer 5 reset
RCC_APB1RSTR_TIM12RST 6 TIM12 Timer reset
RCC_APB1RSTR_TIM13RST 7 TIM13 Timer reset
RCC_APB1RSTR_TIM14RST 8 TIM14 Timer reset
RCC_APB1RSTR_SPI3RST 15 SPI 3 reset
RCC_APB1RSTR_UART4RST 19 UART 4 reset
RCC_APB1RSTR_UART5RST 20 UART 5 reset
RCC_APB1RSTR_CAN2RST 26 CAN2 reset
RCC_APB1RSTR_TIM12RST 6 TIM12 Timer reset
RCC_APB1RSTR_TIM13RST 7 TIM13 Timer reset
RCC_APB1RSTR_TIM14RST 8 TIM14 Timer reset
AHBENR 0x14 32
RCC_AHBENR_DMA1EN 0 DMA1 clock enable
RCC_AHBENR_SRAMEN 2 SRAM interface clock enable
RCC_AHBENR_FLITFEN 4 FLITF clock enable
RCC_AHBENR_CRCEN 6 CRC clock enable
RCC_AHBENR_DMA2EN 1 DMA2 clock enable
RCC_AHBENR_FSMCEN 8 FSMC clock enable
RCC_AHBENR_SDIOEN 10 SDIO clock enable
RCC_AHBENR_FSMCEN 8 FSMC clock enable
RCC_AHBENR_OTGFSEN 12 USB OTG FS clock enable
RCC_AHBENR_ETHMACEN 14 ETHERNET MAC clock enable
RCC_AHBENR_ETHMACTXEN 15 ETHERNET MAC Tx clock enable
RCC_AHBENR_ETHMACRXEN 16 ETHERNET MAC Rx clock enable
APB2ENR 0x18 32
RCC_APB2ENR_AFIOEN 0 Alternate Function I/O clock enable
RCC_APB2ENR_IOPAEN 2 I/O port A clock enable
RCC_APB2ENR_IOPBEN 3 I/O port B clock enable
RCC_APB2ENR_IOPCEN 4 I/O port C clock enable
RCC_APB2ENR_IOPDEN 5 I/O port D clock enable
RCC_APB2ENR_ADC1EN 9 ADC 1 interface clock enable
RCC_APB2ENR_ADC2EN 10 ADC 2 interface clock enable
RCC_APB2ENR_TIM1EN 11 TIM1 Timer clock enable
RCC_APB2ENR_SPI1EN 12 SPI 1 clock enable
RCC_APB2ENR_USART1EN 14 USART1 clock enable
RCC_APB2ENR_TIM15EN 16 TIM15 Timer clock enable
RCC_APB2ENR_TIM16EN 17 TIM16 Timer clock enable
RCC_APB2ENR_TIM17EN 18 TIM17 Timer clock enable
RCC_APB2ENR_IOPEEN 6 I/O port E clock enable
RCC_APB2ENR_IOPFEN 7 I/O port F clock enable
RCC_APB2ENR_IOPGEN 8 I/O port G clock enable
RCC_APB2ENR_TIM8EN 13 TIM8 Timer clock enable
RCC_APB2ENR_ADC3EN 15 DMA1 clock enable
RCC_APB2ENR_IOPFEN 7 I/O port F clock enable
RCC_APB2ENR_IOPGEN 8 I/O port G clock enable
RCC_APB2ENR_TIM9EN 19 TIM9 Timer clock enable
RCC_APB2ENR_TIM10EN 20 TIM10 Timer clock enable
RCC_APB2ENR_TIM11EN 21 TIM11 Timer clock enable
APB1ENR 0x1C 32
RCC_APB1ENR_TIM2EN 0 Timer 2 clock enabled
RCC_APB1ENR_TIM3EN 1 Timer 3 clock enable
RCC_APB1ENR_WWDGEN 11 Window Watchdog clock enable
RCC_APB1ENR_USART2EN 17 USART 2 clock enable
RCC_APB1ENR_I2C1EN 21 I2C 1 clock enable
RCC_APB1ENR_CAN1EN 25 CAN1 clock enable
RCC_APB1ENR_BKPEN 27 Backup interface clock enable
RCC_APB1ENR_PWREN 28 Power interface clock enable
RCC_APB1ENR_TIM4EN 2 Timer 4 clock enable
RCC_APB1ENR_SPI2EN 14 SPI 2 clock enable
RCC_APB1ENR_USART3EN 18 USART 3 clock enable
RCC_APB1ENR_I2C2EN 22 I2C 2 clock enable
RCC_APB1ENR_USBEN 23 USB Device clock enable
RCC_APB1ENR_TIM5EN 3 Timer 5 clock enable
RCC_APB1ENR_TIM6EN 4 Timer 6 clock enable
RCC_APB1ENR_TIM7EN 5 Timer 7 clock enable
RCC_APB1ENR_SPI3EN 15 SPI 3 clock enable
RCC_APB1ENR_UART4EN 19 UART 4 clock enable
RCC_APB1ENR_UART5EN 20 UART 5 clock enable
RCC_APB1ENR_DACEN 29 DAC interface clock enable
RCC_APB1ENR_TIM6EN 4 Timer 6 clock enable
RCC_APB1ENR_TIM7EN 5 Timer 7 clock enable
RCC_APB1ENR_DACEN 29 DAC interface clock enable
RCC_APB1ENR_CECEN 30 CEC interface clock enable
RCC_APB1ENR_TIM5EN 3 Timer 5 clock enable
RCC_APB1ENR_TIM12EN 6 TIM12 Timer clock enable
RCC_APB1ENR_TIM13EN 7 TIM13 Timer clock enable
RCC_APB1ENR_TIM14EN 8 TIM14 Timer clock enable
RCC_APB1ENR_SPI3EN 15 SPI 3 clock enable
RCC_APB1ENR_UART4EN 19 UART 4 clock enable
RCC_APB1ENR_UART5EN 20 UART 5 clock enable
RCC_APB1ENR_CAN2EN 26 CAN2 clock enable
RCC_APB1ENR_TIM12EN 6 TIM12 Timer clock enable
RCC_APB1ENR_TIM13EN 7 TIM13 Timer clock enable
RCC_APB1ENR_TIM14EN 8 TIM14 Timer clock enable
BDCR 0x20 32
RCC_BDCR_LSEON 0 External Low Speed oscillator enable
RCC_BDCR_LSERDY 1 External Low Speed oscillator Ready
RCC_BDCR_LSEBYP 2 External Low Speed oscillator Bypass
RCC_BDCR_RTCSEL 8:9 RTCSEL[1:0] bits (RTC clock source selection)
RCC_BDCR_RTCSEL_0 8 Bit 0
RCC_BDCR_RTCSEL_1 9 Bit 1
RCC_BDCR_RTCSEL_NOCLOCK — No clock
RCC_BDCR_RTCSEL_LSE 8 LSE oscillator clock used as RTC clock
RCC_BDCR_RTCSEL_LSI 9 LSI oscillator clock used as RTC clock
RCC_BDCR_RTCSEL_HSE 8:9 HSE oscillator clock divided by 128 used as RTC clock
RCC_BDCR_RTCEN 15 RTC clock enable
RCC_BDCR_BDRST 16 Backup domain software reset
CSR 0x24 32
RCC_CSR_LSION 0 Internal Low Speed oscillator enable
RCC_CSR_LSIRDY 1 Internal Low Speed oscillator Ready
RCC_CSR_RMVF 24 Remove reset flag
RCC_CSR_PINRSTF 26 PIN reset flag
RCC_CSR_PORRSTF 27 POR/PDR reset flag
RCC_CSR_SFTRSTF 28 Software Reset flag
RCC_CSR_IWDGRSTF 29 Independent Watchdog reset flag
RCC_CSR_WWDGRSTF 30 Window watchdog reset flag
RCC_CSR_LPWRRSTF 31 Low-Power reset flag
AHBRSTR 0x28 32
RCC_AHBRSTR_OTGFSRST 12 USB OTG FS reset
RCC_AHBRSTR_ETHMACRST 14 ETHERNET MAC reset
CFGR2 0x2C 32
RCC_CFGR2_PREDIV1 0:3 PREDIV1[3:0] bits
RCC_CFGR2_PREDIV1_0 0 Bit 0
RCC_CFGR2_PREDIV1_1 1 Bit 1
RCC_CFGR2_PREDIV1_2 2 Bit 2
RCC_CFGR2_PREDIV1_3 3 Bit 3
RCC_CFGR2_PREDIV1_DIV1 — PREDIV1 input clock not divided
RCC_CFGR2_PREDIV1_DIV2 0 PREDIV1 input clock divided by 2
RCC_CFGR2_PREDIV1_DIV3 1 PREDIV1 input clock divided by 3
RCC_CFGR2_PREDIV1_DIV4 0:1 PREDIV1 input clock divided by 4
RCC_CFGR2_PREDIV1_DIV5 2 PREDIV1 input clock divided by 5
RCC_CFGR2_PREDIV1_DIV6 0:2 PREDIV1 input clock divided by 6
RCC_CFGR2_PREDIV1_DIV7 1:2 PREDIV1 input clock divided by 7
RCC_CFGR2_PREDIV1_DIV8 0:2 PREDIV1 input clock divided by 8
RCC_CFGR2_PREDIV1_DIV9 3 PREDIV1 input clock divided by 9
RCC_CFGR2_PREDIV1_DIV10 0:3 PREDIV1 input clock divided by 10
RCC_CFGR2_PREDIV1_DIV11 1:3 PREDIV1 input clock divided by 11
RCC_CFGR2_PREDIV1_DIV12 0:3 PREDIV1 input clock divided by 12
RCC_CFGR2_PREDIV1_DIV13 2:3 PREDIV1 input clock divided by 13
RCC_CFGR2_PREDIV1_DIV14 0:3 PREDIV1 input clock divided by 14
RCC_CFGR2_PREDIV1_DIV15 1:3 PREDIV1 input clock divided by 15
RCC_CFGR2_PREDIV1_DIV16 0:3 PREDIV1 input clock divided by 16
RCC_CFGR2_PREDIV2 4:7 PREDIV2[3:0] bits
RCC_CFGR2_PREDIV2_0 4 Bit 0
RCC_CFGR2_PREDIV2_1 5 Bit 1
RCC_CFGR2_PREDIV2_2 6 Bit 2
RCC_CFGR2_PREDIV2_3 7 Bit 3
RCC_CFGR2_PREDIV2_DIV1 — PREDIV2 input clock not divided
RCC_CFGR2_PREDIV2_DIV2 4 PREDIV2 input clock divided by 2
RCC_CFGR2_PREDIV2_DIV3 5 PREDIV2 input clock divided by 3
RCC_CFGR2_PREDIV2_DIV4 4:5 PREDIV2 input clock divided by 4
RCC_CFGR2_PREDIV2_DIV5 6 PREDIV2 input clock divided by 5
RCC_CFGR2_PREDIV2_DIV6 4:6 PREDIV2 input clock divided by 6
RCC_CFGR2_PREDIV2_DIV7 5:6 PREDIV2 input clock divided by 7
RCC_CFGR2_PREDIV2_DIV8 4:6 PREDIV2 input clock divided by 8
RCC_CFGR2_PREDIV2_DIV9 7 PREDIV2 input clock divided by 9
RCC_CFGR2_PREDIV2_DIV10 4:7 PREDIV2 input clock divided by 10
RCC_CFGR2_PREDIV2_DIV11 5:7 PREDIV2 input clock divided by 11
RCC_CFGR2_PREDIV2_DIV12 4:7 PREDIV2 input clock divided by 12
RCC_CFGR2_PREDIV2_DIV13 6:7 PREDIV2 input clock divided by 13
RCC_CFGR2_PREDIV2_DIV14 4:7 PREDIV2 input clock divided by 14
RCC_CFGR2_PREDIV2_DIV15 5:7 PREDIV2 input clock divided by 15
RCC_CFGR2_PREDIV2_DIV16 4:7 PREDIV2 input clock divided by 16
RCC_CFGR2_PLL2MUL 8:11 PLL2MUL[3:0] bits
RCC_CFGR2_PLL2MUL_0 8 Bit 0
RCC_CFGR2_PLL2MUL_1 9 Bit 1
RCC_CFGR2_PLL2MUL_2 10 Bit 2
RCC_CFGR2_PLL2MUL_3 11 Bit 3
RCC_CFGR2_PLL2MUL8 9:10 PLL2 input clock * 8
RCC_CFGR2_PLL2MUL9 8:10 PLL2 input clock * 9
RCC_CFGR2_PLL2MUL10 11 PLL2 input clock * 10
RCC_CFGR2_PLL2MUL11 8:11 PLL2 input clock * 11
RCC_CFGR2_PLL2MUL12 9:11 PLL2 input clock * 12
RCC_CFGR2_PLL2MUL13 8:11 PLL2 input clock * 13
RCC_CFGR2_PLL2MUL14 10:11 PLL2 input clock * 14
RCC_CFGR2_PLL2MUL16 9:11 PLL2 input clock * 16
RCC_CFGR2_PLL2MUL20 8:11 PLL2 input clock * 20
RCC_CFGR2_PLL3MUL 12:15 PLL3MUL[3:0] bits
RCC_CFGR2_PLL3MUL_0 12 Bit 0
RCC_CFGR2_PLL3MUL_1 13 Bit 1
RCC_CFGR2_PLL3MUL_2 14 Bit 2
RCC_CFGR2_PLL3MUL_3 15 Bit 3
RCC_CFGR2_PLL3MUL8 13:14 PLL3 input clock * 8
RCC_CFGR2_PLL3MUL9 12:14 PLL3 input clock * 9
RCC_CFGR2_PLL3MUL10 15 PLL3 input clock * 10
RCC_CFGR2_PLL3MUL11 12:15 PLL3 input clock * 11
RCC_CFGR2_PLL3MUL12 13:15 PLL3 input clock * 12
RCC_CFGR2_PLL3MUL13 12:15 PLL3 input clock * 13
RCC_CFGR2_PLL3MUL14 14:15 PLL3 input clock * 14
RCC_CFGR2_PLL3MUL16 13:15 PLL3 input clock * 16
RCC_CFGR2_PLL3MUL20 12:15 PLL3 input clock * 20
RCC_CFGR2_PREDIV1SRC 16 PREDIV1 entry clock source
RCC_CFGR2_PREDIV1SRC_PLL2 16 PLL2 selected as PREDIV1 entry clock source
RCC_CFGR2_PREDIV1SRC_HSE — HSE selected as PREDIV1 entry clock source
RCC_CFGR2_I2S2SRC 17 I2S2 entry clock source
RCC_CFGR2_I2S3SRC 18 I2S3 clock source
RCC_CFGR2_PREDIV1 0:3 PREDIV1[3:0] bits
RCC_CFGR2_PREDIV1_0 0 Bit 0
RCC_CFGR2_PREDIV1_1 1 Bit 1
RCC_CFGR2_PREDIV1_2 2 Bit 2
RCC_CFGR2_PREDIV1_3 3 Bit 3
RCC_CFGR2_PREDIV1_DIV1 — PREDIV1 input clock not divided
RCC_CFGR2_PREDIV1_DIV2 0 PREDIV1 input clock divided by 2
RCC_CFGR2_PREDIV1_DIV3 1 PREDIV1 input clock divided by 3
RCC_CFGR2_PREDIV1_DIV4 0:1 PREDIV1 input clock divided by 4
RCC_CFGR2_PREDIV1_DIV5 2 PREDIV1 input clock divided by 5
RCC_CFGR2_PREDIV1_DIV6 0:2 PREDIV1 input clock divided by 6
RCC_CFGR2_PREDIV1_DIV7 1:2 PREDIV1 input clock divided by 7
RCC_CFGR2_PREDIV1_DIV8 0:2 PREDIV1 input clock divided by 8
RCC_CFGR2_PREDIV1_DIV9 3 PREDIV1 input clock divided by 9
RCC_CFGR2_PREDIV1_DIV10 0:3 PREDIV1 input clock divided by 10
RCC_CFGR2_PREDIV1_DIV11 1:3 PREDIV1 input clock divided by 11
RCC_CFGR2_PREDIV1_DIV12 0:3 PREDIV1 input clock divided by 12
RCC_CFGR2_PREDIV1_DIV13 2:3 PREDIV1 input clock divided by 13
RCC_CFGR2_PREDIV1_DIV14 0:3 PREDIV1 input clock divided by 14
RCC_CFGR2_PREDIV1_DIV15 1:3 PREDIV1 input clock divided by 15
RCC_CFGR2_PREDIV1_DIV16 0:3 PREDIV1 input clock divided by 16
CFGR2 0x34 32
RCC_CFGR2_PREDIV1 0:3 PREDIV1[3:0] bits
RCC_CFGR2_PREDIV1_0 0 Bit 0
RCC_CFGR2_PREDIV1_1 1 Bit 1
RCC_CFGR2_PREDIV1_2 2 Bit 2
RCC_CFGR2_PREDIV1_3 3 Bit 3
RCC_CFGR2_PREDIV1_DIV1 — PREDIV1 input clock not divided
RCC_CFGR2_PREDIV1_DIV2 0 PREDIV1 input clock divided by 2
RCC_CFGR2_PREDIV1_DIV3 1 PREDIV1 input clock divided by 3
RCC_CFGR2_PREDIV1_DIV4 0:1 PREDIV1 input clock divided by 4
RCC_CFGR2_PREDIV1_DIV5 2 PREDIV1 input clock divided by 5
RCC_CFGR2_PREDIV1_DIV6 0:2 PREDIV1 input clock divided by 6
RCC_CFGR2_PREDIV1_DIV7 1:2 PREDIV1 input clock divided by 7
RCC_CFGR2_PREDIV1_DIV8 0:2 PREDIV1 input clock divided by 8
RCC_CFGR2_PREDIV1_DIV9 3 PREDIV1 input clock divided by 9
RCC_CFGR2_PREDIV1_DIV10 0:3 PREDIV1 input clock divided by 10
RCC_CFGR2_PREDIV1_DIV11 1:3 PREDIV1 input clock divided by 11
RCC_CFGR2_PREDIV1_DIV12 0:3 PREDIV1 input clock divided by 12
RCC_CFGR2_PREDIV1_DIV13 2:3 PREDIV1 input clock divided by 13
RCC_CFGR2_PREDIV1_DIV14 0:3 PREDIV1 input clock divided by 14
RCC_CFGR2_PREDIV1_DIV15 1:3 PREDIV1 input clock divided by 15
RCC_CFGR2_PREDIV1_DIV16 0:3 PREDIV1 input clock divided by 16
RCC_CFGR2_PREDIV2 4:7 PREDIV2[3:0] bits
RCC_CFGR2_PREDIV2_0 4 Bit 0
RCC_CFGR2_PREDIV2_1 5 Bit 1
RCC_CFGR2_PREDIV2_2 6 Bit 2
RCC_CFGR2_PREDIV2_3 7 Bit 3
RCC_CFGR2_PREDIV2_DIV1 — PREDIV2 input clock not divided
RCC_CFGR2_PREDIV2_DIV2 4 PREDIV2 input clock divided by 2
RCC_CFGR2_PREDIV2_DIV3 5 PREDIV2 input clock divided by 3
RCC_CFGR2_PREDIV2_DIV4 4:5 PREDIV2 input clock divided by 4
RCC_CFGR2_PREDIV2_DIV5 6 PREDIV2 input clock divided by 5
RCC_CFGR2_PREDIV2_DIV6 4:6 PREDIV2 input clock divided by 6
RCC_CFGR2_PREDIV2_DIV7 5:6 PREDIV2 input clock divided by 7
RCC_CFGR2_PREDIV2_DIV8 4:6 PREDIV2 input clock divided by 8
RCC_CFGR2_PREDIV2_DIV9 7 PREDIV2 input clock divided by 9
RCC_CFGR2_PREDIV2_DIV10 4:7 PREDIV2 input clock divided by 10
RCC_CFGR2_PREDIV2_DIV11 5:7 PREDIV2 input clock divided by 11
RCC_CFGR2_PREDIV2_DIV12 4:7 PREDIV2 input clock divided by 12
RCC_CFGR2_PREDIV2_DIV13 6:7 PREDIV2 input clock divided by 13
RCC_CFGR2_PREDIV2_DIV14 4:7 PREDIV2 input clock divided by 14
RCC_CFGR2_PREDIV2_DIV15 5:7 PREDIV2 input clock divided by 15
RCC_CFGR2_PREDIV2_DIV16 4:7 PREDIV2 input clock divided by 16
RCC_CFGR2_PLL2MUL 8:11 PLL2MUL[3:0] bits
RCC_CFGR2_PLL2MUL_0 8 Bit 0
RCC_CFGR2_PLL2MUL_1 9 Bit 1
RCC_CFGR2_PLL2MUL_2 10 Bit 2
RCC_CFGR2_PLL2MUL_3 11 Bit 3
RCC_CFGR2_PLL2MUL8 9:10 PLL2 input clock * 8
RCC_CFGR2_PLL2MUL9 8:10 PLL2 input clock * 9
RCC_CFGR2_PLL2MUL10 11 PLL2 input clock * 10
RCC_CFGR2_PLL2MUL11 8:11 PLL2 input clock * 11
RCC_CFGR2_PLL2MUL12 9:11 PLL2 input clock * 12
RCC_CFGR2_PLL2MUL13 8:11 PLL2 input clock * 13
RCC_CFGR2_PLL2MUL14 10:11 PLL2 input clock * 14
RCC_CFGR2_PLL2MUL16 9:11 PLL2 input clock * 16
RCC_CFGR2_PLL2MUL20 8:11 PLL2 input clock * 20
RCC_CFGR2_PLL3MUL 12:15 PLL3MUL[3:0] bits
RCC_CFGR2_PLL3MUL_0 12 Bit 0
RCC_CFGR2_PLL3MUL_1 13 Bit 1
RCC_CFGR2_PLL3MUL_2 14 Bit 2
RCC_CFGR2_PLL3MUL_3 15 Bit 3
RCC_CFGR2_PLL3MUL8 13:14 PLL3 input clock * 8
RCC_CFGR2_PLL3MUL9 12:14 PLL3 input clock * 9
RCC_CFGR2_PLL3MUL10 15 PLL3 input clock * 10
RCC_CFGR2_PLL3MUL11 12:15 PLL3 input clock * 11
RCC_CFGR2_PLL3MUL12 13:15 PLL3 input clock * 12
RCC_CFGR2_PLL3MUL13 12:15 PLL3 input clock * 13
RCC_CFGR2_PLL3MUL14 14:15 PLL3 input clock * 14
RCC_CFGR2_PLL3MUL16 13:15 PLL3 input clock * 16
RCC_CFGR2_PLL3MUL20 12:15 PLL3 input clock * 20
RCC_CFGR2_PREDIV1SRC 16 PREDIV1 entry clock source
RCC_CFGR2_PREDIV1SRC_PLL2 16 PLL2 selected as PREDIV1 entry clock source
RCC_CFGR2_PREDIV1SRC_HSE — HSE selected as PREDIV1 entry clock source
RCC_CFGR2_I2S2SRC 17 I2S2 entry clock source
RCC_CFGR2_I2S3SRC 18 I2S3 clock source
RCC_CFGR2_PREDIV1 0:3 PREDIV1[3:0] bits
RCC_CFGR2_PREDIV1_0 0 Bit 0
RCC_CFGR2_PREDIV1_1 1 Bit 1
RCC_CFGR2_PREDIV1_2 2 Bit 2
RCC_CFGR2_PREDIV1_3 3 Bit 3
RCC_CFGR2_PREDIV1_DIV1 — PREDIV1 input clock not divided
RCC_CFGR2_PREDIV1_DIV2 0 PREDIV1 input clock divided by 2
RCC_CFGR2_PREDIV1_DIV3 1 PREDIV1 input clock divided by 3
RCC_CFGR2_PREDIV1_DIV4 0:1 PREDIV1 input clock divided by 4
RCC_CFGR2_PREDIV1_DIV5 2 PREDIV1 input clock divided by 5
RCC_CFGR2_PREDIV1_DIV6 0:2 PREDIV1 input clock divided by 6
RCC_CFGR2_PREDIV1_DIV7 1:2 PREDIV1 input clock divided by 7
RCC_CFGR2_PREDIV1_DIV8 0:2 PREDIV1 input clock divided by 8
RCC_CFGR2_PREDIV1_DIV9 3 PREDIV1 input clock divided by 9
RCC_CFGR2_PREDIV1_DIV10 0:3 PREDIV1 input clock divided by 10
RCC_CFGR2_PREDIV1_DIV11 1:3 PREDIV1 input clock divided by 11
RCC_CFGR2_PREDIV1_DIV12 0:3 PREDIV1 input clock divided by 12
RCC_CFGR2_PREDIV1_DIV13 2:3 PREDIV1 input clock divided by 13
RCC_CFGR2_PREDIV1_DIV14 0:3 PREDIV1 input clock divided by 14
RCC_CFGR2_PREDIV1_DIV15 1:3 PREDIV1 input clock divided by 15
RCC_CFGR2_PREDIV1_DIV16 0:3 PREDIV1 input clock divided by 16

GPIO — I/O ports (section 8)

Register Offset Bits Purpose
CRL 0x00 32
GPIO_CRL_MODE 0:29 Port x mode bits
GPIO_CRL_MODE0 0:1 MODE0[1:0] bits (Port x mode bits, pin 0)
GPIO_CRL_MODE0_0 0 Bit 0
GPIO_CRL_MODE0_1 1 Bit 1
GPIO_CRL_MODE1 4:5 MODE1[1:0] bits (Port x mode bits, pin 1)
GPIO_CRL_MODE1_0 4 Bit 0
GPIO_CRL_MODE1_1 5 Bit 1
GPIO_CRL_MODE2 8:9 MODE2[1:0] bits (Port x mode bits, pin 2)
GPIO_CRL_MODE2_0 8 Bit 0
GPIO_CRL_MODE2_1 9 Bit 1
GPIO_CRL_MODE3 12:13 MODE3[1:0] bits (Port x mode bits, pin 3)
GPIO_CRL_MODE3_0 12 Bit 0
GPIO_CRL_MODE3_1 13 Bit 1
GPIO_CRL_MODE4 16:17 MODE4[1:0] bits (Port x mode bits, pin 4)
GPIO_CRL_MODE4_0 16 Bit 0
GPIO_CRL_MODE4_1 17 Bit 1
GPIO_CRL_MODE5 20:21 MODE5[1:0] bits (Port x mode bits, pin 5)
GPIO_CRL_MODE5_0 20 Bit 0
GPIO_CRL_MODE5_1 21 Bit 1
GPIO_CRL_MODE6 24:25 MODE6[1:0] bits (Port x mode bits, pin 6)
GPIO_CRL_MODE6_0 24 Bit 0
GPIO_CRL_MODE6_1 25 Bit 1
GPIO_CRL_MODE7 28:29 MODE7[1:0] bits (Port x mode bits, pin 7)
GPIO_CRL_MODE7_0 28 Bit 0
GPIO_CRL_MODE7_1 29 Bit 1
GPIO_CRL_CNF 2:31 Port x configuration bits
GPIO_CRL_CNF0 2:3 CNF0[1:0] bits (Port x configuration bits, pin 0)
GPIO_CRL_CNF0_0 2 Bit 0
GPIO_CRL_CNF0_1 3 Bit 1
GPIO_CRL_CNF1 6:7 CNF1[1:0] bits (Port x configuration bits, pin 1)
GPIO_CRL_CNF1_0 6 Bit 0
GPIO_CRL_CNF1_1 7 Bit 1
GPIO_CRL_CNF2 10:11 CNF2[1:0] bits (Port x configuration bits, pin 2)
GPIO_CRL_CNF2_0 10 Bit 0
GPIO_CRL_CNF2_1 11 Bit 1
GPIO_CRL_CNF3 14:15 CNF3[1:0] bits (Port x configuration bits, pin 3)
GPIO_CRL_CNF3_0 14 Bit 0
GPIO_CRL_CNF3_1 15 Bit 1
GPIO_CRL_CNF4 18:19 CNF4[1:0] bits (Port x configuration bits, pin 4)
GPIO_CRL_CNF4_0 18 Bit 0
GPIO_CRL_CNF4_1 19 Bit 1
GPIO_CRL_CNF5 22:23 CNF5[1:0] bits (Port x configuration bits, pin 5)
GPIO_CRL_CNF5_0 22 Bit 0
GPIO_CRL_CNF5_1 23 Bit 1
GPIO_CRL_CNF6 26:27 CNF6[1:0] bits (Port x configuration bits, pin 6)
GPIO_CRL_CNF6_0 26 Bit 0
GPIO_CRL_CNF6_1 27 Bit 1
GPIO_CRL_CNF7 30:31 CNF7[1:0] bits (Port x configuration bits, pin 7)
GPIO_CRL_CNF7_0 30 Bit 0
GPIO_CRL_CNF7_1 31 Bit 1
CRH 0x04 32
GPIO_CRH_MODE 0:29 Port x mode bits
GPIO_CRH_MODE8 0:1 MODE8[1:0] bits (Port x mode bits, pin 8)
GPIO_CRH_MODE8_0 0 Bit 0
GPIO_CRH_MODE8_1 1 Bit 1
GPIO_CRH_MODE9 4:5 MODE9[1:0] bits (Port x mode bits, pin 9)
GPIO_CRH_MODE9_0 4 Bit 0
GPIO_CRH_MODE9_1 5 Bit 1
GPIO_CRH_MODE10 8:9 MODE10[1:0] bits (Port x mode bits, pin 10)
GPIO_CRH_MODE10_0 8 Bit 0
GPIO_CRH_MODE10_1 9 Bit 1
GPIO_CRH_MODE11 12:13 MODE11[1:0] bits (Port x mode bits, pin 11)
GPIO_CRH_MODE11_0 12 Bit 0
GPIO_CRH_MODE11_1 13 Bit 1
GPIO_CRH_MODE12 16:17 MODE12[1:0] bits (Port x mode bits, pin 12)
GPIO_CRH_MODE12_0 16 Bit 0
GPIO_CRH_MODE12_1 17 Bit 1
GPIO_CRH_MODE13 20:21 MODE13[1:0] bits (Port x mode bits, pin 13)
GPIO_CRH_MODE13_0 20 Bit 0
GPIO_CRH_MODE13_1 21 Bit 1
GPIO_CRH_MODE14 24:25 MODE14[1:0] bits (Port x mode bits, pin 14)
GPIO_CRH_MODE14_0 24 Bit 0
GPIO_CRH_MODE14_1 25 Bit 1
GPIO_CRH_MODE15 28:29 MODE15[1:0] bits (Port x mode bits, pin 15)
GPIO_CRH_MODE15_0 28 Bit 0
GPIO_CRH_MODE15_1 29 Bit 1
GPIO_CRH_CNF 2:31 Port x configuration bits
GPIO_CRH_CNF8 2:3 CNF8[1:0] bits (Port x configuration bits, pin 8)
GPIO_CRH_CNF8_0 2 Bit 0
GPIO_CRH_CNF8_1 3 Bit 1
GPIO_CRH_CNF9 6:7 CNF9[1:0] bits (Port x configuration bits, pin 9)
GPIO_CRH_CNF9_0 6 Bit 0
GPIO_CRH_CNF9_1 7 Bit 1
GPIO_CRH_CNF10 10:11 CNF10[1:0] bits (Port x configuration bits, pin 10)
GPIO_CRH_CNF10_0 10 Bit 0
GPIO_CRH_CNF10_1 11 Bit 1
GPIO_CRH_CNF11 14:15 CNF11[1:0] bits (Port x configuration bits, pin 11)
GPIO_CRH_CNF11_0 14 Bit 0
GPIO_CRH_CNF11_1 15 Bit 1
GPIO_CRH_CNF12 18:19 CNF12[1:0] bits (Port x configuration bits, pin 12)
GPIO_CRH_CNF12_0 18 Bit 0
GPIO_CRH_CNF12_1 19 Bit 1
GPIO_CRH_CNF13 22:23 CNF13[1:0] bits (Port x configuration bits, pin 13)
GPIO_CRH_CNF13_0 22 Bit 0
GPIO_CRH_CNF13_1 23 Bit 1
GPIO_CRH_CNF14 26:27 CNF14[1:0] bits (Port x configuration bits, pin 14)
GPIO_CRH_CNF14_0 26 Bit 0
GPIO_CRH_CNF14_1 27 Bit 1
GPIO_CRH_CNF15 30:31 CNF15[1:0] bits (Port x configuration bits, pin 15)
GPIO_CRH_CNF15_0 30 Bit 0
GPIO_CRH_CNF15_1 31 Bit 1
IDR 0x08 32
GPIO_IDR_IDR0 0 Port input data, bit 0
GPIO_IDR_IDR1 1 Port input data, bit 1
GPIO_IDR_IDR2 2 Port input data, bit 2
GPIO_IDR_IDR3 3 Port input data, bit 3
GPIO_IDR_IDR4 4 Port input data, bit 4
GPIO_IDR_IDR5 5 Port input data, bit 5
GPIO_IDR_IDR6 6 Port input data, bit 6
GPIO_IDR_IDR7 7 Port input data, bit 7
GPIO_IDR_IDR8 8 Port input data, bit 8
GPIO_IDR_IDR9 9 Port input data, bit 9
GPIO_IDR_IDR10 10 Port input data, bit 10
GPIO_IDR_IDR11 11 Port input data, bit 11
GPIO_IDR_IDR12 12 Port input data, bit 12
GPIO_IDR_IDR13 13 Port input data, bit 13
GPIO_IDR_IDR14 14 Port input data, bit 14
GPIO_IDR_IDR15 15 Port input data, bit 15
ODR 0x0C 32
GPIO_ODR_ODR0 0 Port output data, bit 0
GPIO_ODR_ODR1 1 Port output data, bit 1
GPIO_ODR_ODR2 2 Port output data, bit 2
GPIO_ODR_ODR3 3 Port output data, bit 3
GPIO_ODR_ODR4 4 Port output data, bit 4
GPIO_ODR_ODR5 5 Port output data, bit 5
GPIO_ODR_ODR6 6 Port output data, bit 6
GPIO_ODR_ODR7 7 Port output data, bit 7
GPIO_ODR_ODR8 8 Port output data, bit 8
GPIO_ODR_ODR9 9 Port output data, bit 9
GPIO_ODR_ODR10 10 Port output data, bit 10
GPIO_ODR_ODR11 11 Port output data, bit 11
GPIO_ODR_ODR12 12 Port output data, bit 12
GPIO_ODR_ODR13 13 Port output data, bit 13
GPIO_ODR_ODR14 14 Port output data, bit 14
GPIO_ODR_ODR15 15 Port output data, bit 15
BSRR 0x10 32
GPIO_BSRR_BS0 0 Port x Set bit 0
GPIO_BSRR_BS1 1 Port x Set bit 1
GPIO_BSRR_BS2 2 Port x Set bit 2
GPIO_BSRR_BS3 3 Port x Set bit 3
GPIO_BSRR_BS4 4 Port x Set bit 4
GPIO_BSRR_BS5 5 Port x Set bit 5
GPIO_BSRR_BS6 6 Port x Set bit 6
GPIO_BSRR_BS7 7 Port x Set bit 7
GPIO_BSRR_BS8 8 Port x Set bit 8
GPIO_BSRR_BS9 9 Port x Set bit 9
GPIO_BSRR_BS10 10 Port x Set bit 10
GPIO_BSRR_BS11 11 Port x Set bit 11
GPIO_BSRR_BS12 12 Port x Set bit 12
GPIO_BSRR_BS13 13 Port x Set bit 13
GPIO_BSRR_BS14 14 Port x Set bit 14
GPIO_BSRR_BS15 15 Port x Set bit 15
GPIO_BSRR_BR0 16 Port x Reset bit 0
GPIO_BSRR_BR1 17 Port x Reset bit 1
GPIO_BSRR_BR2 18 Port x Reset bit 2
GPIO_BSRR_BR3 19 Port x Reset bit 3
GPIO_BSRR_BR4 20 Port x Reset bit 4
GPIO_BSRR_BR5 21 Port x Reset bit 5
GPIO_BSRR_BR6 22 Port x Reset bit 6
GPIO_BSRR_BR7 23 Port x Reset bit 7
GPIO_BSRR_BR8 24 Port x Reset bit 8
GPIO_BSRR_BR9 25 Port x Reset bit 9
GPIO_BSRR_BR10 26 Port x Reset bit 10
GPIO_BSRR_BR11 27 Port x Reset bit 11
GPIO_BSRR_BR12 28 Port x Reset bit 12
GPIO_BSRR_BR13 29 Port x Reset bit 13
GPIO_BSRR_BR14 30 Port x Reset bit 14
GPIO_BSRR_BR15 31 Port x Reset bit 15
BRR 0x14 32
GPIO_BRR_BR0 0 Port x Reset bit 0
GPIO_BRR_BR1 1 Port x Reset bit 1
GPIO_BRR_BR2 2 Port x Reset bit 2
GPIO_BRR_BR3 3 Port x Reset bit 3
GPIO_BRR_BR4 4 Port x Reset bit 4
GPIO_BRR_BR5 5 Port x Reset bit 5
GPIO_BRR_BR6 6 Port x Reset bit 6
GPIO_BRR_BR7 7 Port x Reset bit 7
GPIO_BRR_BR8 8 Port x Reset bit 8
GPIO_BRR_BR9 9 Port x Reset bit 9
GPIO_BRR_BR10 10 Port x Reset bit 10
GPIO_BRR_BR11 11 Port x Reset bit 11
GPIO_BRR_BR12 12 Port x Reset bit 12
GPIO_BRR_BR13 13 Port x Reset bit 13
GPIO_BRR_BR14 14 Port x Reset bit 14
GPIO_BRR_BR15 15 Port x Reset bit 15
LCKR 0x18 32
GPIO_LCKR_LCK0 0 Port x Lock bit 0
GPIO_LCKR_LCK1 1 Port x Lock bit 1
GPIO_LCKR_LCK2 2 Port x Lock bit 2
GPIO_LCKR_LCK3 3 Port x Lock bit 3
GPIO_LCKR_LCK4 4 Port x Lock bit 4
GPIO_LCKR_LCK5 5 Port x Lock bit 5
GPIO_LCKR_LCK6 6 Port x Lock bit 6
GPIO_LCKR_LCK7 7 Port x Lock bit 7
GPIO_LCKR_LCK8 8 Port x Lock bit 8
GPIO_LCKR_LCK9 9 Port x Lock bit 9
GPIO_LCKR_LCK10 10 Port x Lock bit 10
GPIO_LCKR_LCK11 11 Port x Lock bit 11
GPIO_LCKR_LCK12 12 Port x Lock bit 12
GPIO_LCKR_LCK13 13 Port x Lock bit 13
GPIO_LCKR_LCK14 14 Port x Lock bit 14
GPIO_LCKR_LCK15 15 Port x Lock bit 15
GPIO_LCKR_LCKK 16 Lock key

AFIO — Alternate functions (section 8)

Register Offset Bits Purpose
EVCR 0x00 32
AFIO_EVCR_PIN 0:3 PIN[3:0] bits (Pin selection)
AFIO_EVCR_PIN_0 0 Bit 0
AFIO_EVCR_PIN_1 1 Bit 1
AFIO_EVCR_PIN_2 2 Bit 2
AFIO_EVCR_PIN_3 3 Bit 3
AFIO_EVCR_PIN_PX0 — Pin 0 selected
AFIO_EVCR_PIN_PX1 0 Pin 1 selected
AFIO_EVCR_PIN_PX2 1 Pin 2 selected
AFIO_EVCR_PIN_PX3 0:1 Pin 3 selected
AFIO_EVCR_PIN_PX4 2 Pin 4 selected
AFIO_EVCR_PIN_PX5 0:2 Pin 5 selected
AFIO_EVCR_PIN_PX6 1:2 Pin 6 selected
AFIO_EVCR_PIN_PX7 0:2 Pin 7 selected
AFIO_EVCR_PIN_PX8 3 Pin 8 selected
AFIO_EVCR_PIN_PX9 0:3 Pin 9 selected
AFIO_EVCR_PIN_PX10 1:3 Pin 10 selected
AFIO_EVCR_PIN_PX11 0:3 Pin 11 selected
AFIO_EVCR_PIN_PX12 2:3 Pin 12 selected
AFIO_EVCR_PIN_PX13 0:3 Pin 13 selected
AFIO_EVCR_PIN_PX14 1:3 Pin 14 selected
AFIO_EVCR_PIN_PX15 0:3 Pin 15 selected
AFIO_EVCR_PORT 4:6 PORT[2:0] bits (Port selection)
AFIO_EVCR_PORT_0 4 Bit 0
AFIO_EVCR_PORT_1 5 Bit 1
AFIO_EVCR_PORT_2 6 Bit 2
AFIO_EVCR_PORT_PA — Port A selected
AFIO_EVCR_PORT_PB 4 Port B selected
AFIO_EVCR_PORT_PC 5 Port C selected
AFIO_EVCR_PORT_PD 4:5 Port D selected
AFIO_EVCR_PORT_PE 6 Port E selected
AFIO_EVCR_EVOE 7 Event Output Enable
MAPR 0x04 32
AFIO_MAPR_SPI1_REMAP 0 SPI1 remapping
AFIO_MAPR_I2C1_REMAP 1 I2C1 remapping
AFIO_MAPR_USART1_REMAP 2 USART1 remapping
AFIO_MAPR_USART2_REMAP 3 USART2 remapping
AFIO_MAPR_USART3_REMAP 4:5 USART3_REMAP[1:0] bits (USART3 remapping)
AFIO_MAPR_USART3_REMAP_0 4 Bit 0
AFIO_MAPR_USART3_REMAP_1 5 Bit 1
AFIO_MAPR_USART3_REMAP_NOREMAP — No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
AFIO_MAPR_USART3_REMAP_PARTIALREMAP 4 Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
AFIO_MAPR_USART3_REMAP_FULLREMAP 4:5 Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
AFIO_MAPR_TIM1_REMAP 6:7 TIM1_REMAP[1:0] bits (TIM1 remapping)
AFIO_MAPR_TIM1_REMAP_0 6 Bit 0
AFIO_MAPR_TIM1_REMAP_1 7 Bit 1
AFIO_MAPR_TIM1_REMAP_NOREMAP — No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
AFIO_MAPR_TIM1_REMAP_PARTIALREMAP 6 Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
AFIO_MAPR_TIM1_REMAP_FULLREMAP 6:7 Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
AFIO_MAPR_TIM2_REMAP 8:9 TIM2_REMAP[1:0] bits (TIM2 remapping)
AFIO_MAPR_TIM2_REMAP_0 8 Bit 0
AFIO_MAPR_TIM2_REMAP_1 9 Bit 1
AFIO_MAPR_TIM2_REMAP_NOREMAP — No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 8 Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 9 Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
AFIO_MAPR_TIM2_REMAP_FULLREMAP 8:9 Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
AFIO_MAPR_TIM3_REMAP 10:11 TIM3_REMAP[1:0] bits (TIM3 remapping)
AFIO_MAPR_TIM3_REMAP_0 10 Bit 0
AFIO_MAPR_TIM3_REMAP_1 11 Bit 1
AFIO_MAPR_TIM3_REMAP_NOREMAP — No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 11 Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
AFIO_MAPR_TIM3_REMAP_FULLREMAP 10:11 Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
AFIO_MAPR_TIM4_REMAP 12 TIM4_REMAP bit (TIM4 remapping)
AFIO_MAPR_CAN_REMAP 13:14 CAN_REMAP[1:0] bits (CAN Alternate function remapping)
AFIO_MAPR_CAN_REMAP_0 13 Bit 0
AFIO_MAPR_CAN_REMAP_1 14 Bit 1
AFIO_MAPR_CAN_REMAP_REMAP1 — CANRX mapped to PA11, CANTX mapped to PA12
AFIO_MAPR_CAN_REMAP_REMAP2 14 CANRX mapped to PB8, CANTX mapped to PB9
AFIO_MAPR_CAN_REMAP_REMAP3 13:14 CANRX mapped to PD0, CANTX mapped to PD1
AFIO_MAPR_PD01_REMAP 15 Port D0/Port D1 mapping on OSC_IN/OSC_OUT
AFIO_MAPR_TIM5CH4_IREMAP 16 TIM5 Channel4 Internal Remap
AFIO_MAPR_ADC1_ETRGINJ_REMAP 17 ADC 1 External Trigger Injected Conversion remapping
AFIO_MAPR_ADC1_ETRGREG_REMAP 18 ADC 1 External Trigger Regular Conversion remapping
AFIO_MAPR_ADC2_ETRGINJ_REMAP 19 ADC 2 External Trigger Injected Conversion remapping
AFIO_MAPR_ADC2_ETRGREG_REMAP 20 ADC 2 External Trigger Regular Conversion remapping
AFIO_MAPR_SWJ_CFG 24:26 SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
AFIO_MAPR_SWJ_CFG_0 24 Bit 0
AFIO_MAPR_SWJ_CFG_1 25 Bit 1
AFIO_MAPR_SWJ_CFG_2 26 Bit 2
AFIO_MAPR_SWJ_CFG_RESET — Full SWJ (JTAG-DP + SW-DP) : Reset State
AFIO_MAPR_SWJ_CFG_NOJNTRST 24 Full SWJ (JTAG-DP + SW-DP) but without JNTRST
AFIO_MAPR_SWJ_CFG_JTAGDISABLE 25 JTAG-DP Disabled and SW-DP Enabled
AFIO_MAPR_SWJ_CFG_DISABLE 26 JTAG-DP Disabled and SW-DP Disabled
AFIO_MAPR_ETH_REMAP 21 SPI3_REMAP bit (Ethernet MAC I/O remapping)
AFIO_MAPR_CAN2_REMAP 22 CAN2_REMAP bit (CAN2 I/O remapping)
AFIO_MAPR_MII_RMII_SEL 23 MII_RMII_SEL bit (Ethernet MII or RMII selection)
AFIO_MAPR_SPI3_REMAP 28 SPI3_REMAP bit (SPI3 remapping)
AFIO_MAPR_TIM2ITR1_IREMAP 29 TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping)
AFIO_MAPR_PTP_PPS_REMAP 30 PTP_PPS_REMAP bit (Ethernet PTP PPS remapping)
EXTICR+4×4 0x08 32
MAPR2 0x1C 32
AFIO_MAPR2_TIM15_REMAP 0 TIM15 remapping
AFIO_MAPR2_TIM16_REMAP 1 TIM16 remapping
AFIO_MAPR2_TIM17_REMAP 2 TIM17 remapping
AFIO_MAPR2_CEC_REMAP 3 CEC remapping
AFIO_MAPR2_TIM1_DMA_REMAP 4 TIM1_DMA remapping
AFIO_MAPR2_TIM13_REMAP 8 TIM13 remapping
AFIO_MAPR2_TIM14_REMAP 9 TIM14 remapping
AFIO_MAPR2_FSMC_NADV_REMAP 10 FSMC NADV remapping
AFIO_MAPR2_TIM67_DAC_DMA_REMAP 11 TIM6/TIM7 and DAC DMA remapping
AFIO_MAPR2_TIM12_REMAP 12 TIM12 remapping
AFIO_MAPR2_MISC_REMAP 13 Miscellaneous remapping
AFIO_MAPR2_TIM9_REMAP 5 TIM9 remapping
AFIO_MAPR2_TIM10_REMAP 6 TIM10 remapping
AFIO_MAPR2_TIM11_REMAP 7 TIM11 remapping
AFIO_MAPR2_TIM13_REMAP 8 TIM13 remapping
AFIO_MAPR2_TIM14_REMAP 9 TIM14 remapping
AFIO_MAPR2_FSMC_NADV_REMAP 10 FSMC NADV remapping

EXTI — External interrupts (section 7)

Register Offset Bits Purpose
IMR 0x00 32
EXTI_IMR_MR0 0 Interrupt Mask on line 0
EXTI_IMR_MR1 1 Interrupt Mask on line 1
EXTI_IMR_MR2 2 Interrupt Mask on line 2
EXTI_IMR_MR3 3 Interrupt Mask on line 3
EXTI_IMR_MR4 4 Interrupt Mask on line 4
EXTI_IMR_MR5 5 Interrupt Mask on line 5
EXTI_IMR_MR6 6 Interrupt Mask on line 6
EXTI_IMR_MR7 7 Interrupt Mask on line 7
EXTI_IMR_MR8 8 Interrupt Mask on line 8
EXTI_IMR_MR9 9 Interrupt Mask on line 9
EXTI_IMR_MR10 10 Interrupt Mask on line 10
EXTI_IMR_MR11 11 Interrupt Mask on line 11
EXTI_IMR_MR12 12 Interrupt Mask on line 12
EXTI_IMR_MR13 13 Interrupt Mask on line 13
EXTI_IMR_MR14 14 Interrupt Mask on line 14
EXTI_IMR_MR15 15 Interrupt Mask on line 15
EXTI_IMR_MR16 16 Interrupt Mask on line 16
EXTI_IMR_MR17 17 Interrupt Mask on line 17
EXTI_IMR_MR18 18 Interrupt Mask on line 18
EXTI_IMR_MR19 19 Interrupt Mask on line 19
EMR 0x04 32
EXTI_EMR_MR0 0 Event Mask on line 0
EXTI_EMR_MR1 1 Event Mask on line 1
EXTI_EMR_MR2 2 Event Mask on line 2
EXTI_EMR_MR3 3 Event Mask on line 3
EXTI_EMR_MR4 4 Event Mask on line 4
EXTI_EMR_MR5 5 Event Mask on line 5
EXTI_EMR_MR6 6 Event Mask on line 6
EXTI_EMR_MR7 7 Event Mask on line 7
EXTI_EMR_MR8 8 Event Mask on line 8
EXTI_EMR_MR9 9 Event Mask on line 9
EXTI_EMR_MR10 10 Event Mask on line 10
EXTI_EMR_MR11 11 Event Mask on line 11
EXTI_EMR_MR12 12 Event Mask on line 12
EXTI_EMR_MR13 13 Event Mask on line 13
EXTI_EMR_MR14 14 Event Mask on line 14
EXTI_EMR_MR15 15 Event Mask on line 15
EXTI_EMR_MR16 16 Event Mask on line 16
EXTI_EMR_MR17 17 Event Mask on line 17
EXTI_EMR_MR18 18 Event Mask on line 18
EXTI_EMR_MR19 19 Event Mask on line 19
RTSR 0x08 32
EXTI_RTSR_TR0 0 Rising trigger event configuration bit of line 0
EXTI_RTSR_TR1 1 Rising trigger event configuration bit of line 1
EXTI_RTSR_TR2 2 Rising trigger event configuration bit of line 2
EXTI_RTSR_TR3 3 Rising trigger event configuration bit of line 3
EXTI_RTSR_TR4 4 Rising trigger event configuration bit of line 4
EXTI_RTSR_TR5 5 Rising trigger event configuration bit of line 5
EXTI_RTSR_TR6 6 Rising trigger event configuration bit of line 6
EXTI_RTSR_TR7 7 Rising trigger event configuration bit of line 7
EXTI_RTSR_TR8 8 Rising trigger event configuration bit of line 8
EXTI_RTSR_TR9 9 Rising trigger event configuration bit of line 9
EXTI_RTSR_TR10 10 Rising trigger event configuration bit of line 10
EXTI_RTSR_TR11 11 Rising trigger event configuration bit of line 11
EXTI_RTSR_TR12 12 Rising trigger event configuration bit of line 12
EXTI_RTSR_TR13 13 Rising trigger event configuration bit of line 13
EXTI_RTSR_TR14 14 Rising trigger event configuration bit of line 14
EXTI_RTSR_TR15 15 Rising trigger event configuration bit of line 15
EXTI_RTSR_TR16 16 Rising trigger event configuration bit of line 16
EXTI_RTSR_TR17 17 Rising trigger event configuration bit of line 17
EXTI_RTSR_TR18 18 Rising trigger event configuration bit of line 18
EXTI_RTSR_TR19 19 Rising trigger event configuration bit of line 19
FTSR 0x0C 32
EXTI_FTSR_TR0 0 Falling trigger event configuration bit of line 0
EXTI_FTSR_TR1 1 Falling trigger event configuration bit of line 1
EXTI_FTSR_TR2 2 Falling trigger event configuration bit of line 2
EXTI_FTSR_TR3 3 Falling trigger event configuration bit of line 3
EXTI_FTSR_TR4 4 Falling trigger event configuration bit of line 4
EXTI_FTSR_TR5 5 Falling trigger event configuration bit of line 5
EXTI_FTSR_TR6 6 Falling trigger event configuration bit of line 6
EXTI_FTSR_TR7 7 Falling trigger event configuration bit of line 7
EXTI_FTSR_TR8 8 Falling trigger event configuration bit of line 8
EXTI_FTSR_TR9 9 Falling trigger event configuration bit of line 9
EXTI_FTSR_TR10 10 Falling trigger event configuration bit of line 10
EXTI_FTSR_TR11 11 Falling trigger event configuration bit of line 11
EXTI_FTSR_TR12 12 Falling trigger event configuration bit of line 12
EXTI_FTSR_TR13 13 Falling trigger event configuration bit of line 13
EXTI_FTSR_TR14 14 Falling trigger event configuration bit of line 14
EXTI_FTSR_TR15 15 Falling trigger event configuration bit of line 15
EXTI_FTSR_TR16 16 Falling trigger event configuration bit of line 16
EXTI_FTSR_TR17 17 Falling trigger event configuration bit of line 17
EXTI_FTSR_TR18 18 Falling trigger event configuration bit of line 18
EXTI_FTSR_TR19 19 Falling trigger event configuration bit of line 19
SWIER 0x10 32
EXTI_SWIER_SWIER0 0 Software Interrupt on line 0
EXTI_SWIER_SWIER1 1 Software Interrupt on line 1
EXTI_SWIER_SWIER2 2 Software Interrupt on line 2
EXTI_SWIER_SWIER3 3 Software Interrupt on line 3
EXTI_SWIER_SWIER4 4 Software Interrupt on line 4
EXTI_SWIER_SWIER5 5 Software Interrupt on line 5
EXTI_SWIER_SWIER6 6 Software Interrupt on line 6
EXTI_SWIER_SWIER7 7 Software Interrupt on line 7
EXTI_SWIER_SWIER8 8 Software Interrupt on line 8
EXTI_SWIER_SWIER9 9 Software Interrupt on line 9
EXTI_SWIER_SWIER10 10 Software Interrupt on line 10
EXTI_SWIER_SWIER11 11 Software Interrupt on line 11
EXTI_SWIER_SWIER12 12 Software Interrupt on line 12
EXTI_SWIER_SWIER13 13 Software Interrupt on line 13
EXTI_SWIER_SWIER14 14 Software Interrupt on line 14
EXTI_SWIER_SWIER15 15 Software Interrupt on line 15
EXTI_SWIER_SWIER16 16 Software Interrupt on line 16
EXTI_SWIER_SWIER17 17 Software Interrupt on line 17
EXTI_SWIER_SWIER18 18 Software Interrupt on line 18
EXTI_SWIER_SWIER19 19 Software Interrupt on line 19
PR 0x14 32
EXTI_PR_PR0 0 Pending bit for line 0
EXTI_PR_PR1 1 Pending bit for line 1
EXTI_PR_PR2 2 Pending bit for line 2
EXTI_PR_PR3 3 Pending bit for line 3
EXTI_PR_PR4 4 Pending bit for line 4
EXTI_PR_PR5 5 Pending bit for line 5
EXTI_PR_PR6 6 Pending bit for line 6
EXTI_PR_PR7 7 Pending bit for line 7
EXTI_PR_PR8 8 Pending bit for line 8
EXTI_PR_PR9 9 Pending bit for line 9
EXTI_PR_PR10 10 Pending bit for line 10
EXTI_PR_PR11 11 Pending bit for line 11
EXTI_PR_PR12 12 Pending bit for line 12
EXTI_PR_PR13 13 Pending bit for line 13
EXTI_PR_PR14 14 Pending bit for line 14
EXTI_PR_PR15 15 Pending bit for line 15
EXTI_PR_PR16 16 Pending bit for line 16
EXTI_PR_PR17 17 Pending bit for line 17
EXTI_PR_PR18 18 Pending bit for line 18
EXTI_PR_PR19 19 Pending bit for line 19

DMA — DMA channel (section 9)

Register Offset Bits Purpose
CCR 0x00 32
CNDTR 0x04 32
CPAR 0x08 32
CMAR 0x0C 32

PWR — Power (section 10)

Register Offset Bits Purpose
CR 0x00 32
PWR_CR_LPDS 0 Low-Power Deepsleep
PWR_CR_PDDS 1 Power Down Deepsleep
PWR_CR_CWUF 2 Clear Wakeup Flag
PWR_CR_CSBF 3 Clear Standby Flag
PWR_CR_PVDE 4 Power Voltage Detector Enable
PWR_CR_PLS 5:7 PLS[2:0] bits (PVD Level Selection)
PWR_CR_PLS_0 5 Bit 0
PWR_CR_PLS_1 6 Bit 1
PWR_CR_PLS_2 7 Bit 2
PWR_CR_PLS_2V2 — PVD level 2.2V
PWR_CR_PLS_2V3 5 PVD level 2.3V
PWR_CR_PLS_2V4 6 PVD level 2.4V
PWR_CR_PLS_2V5 5:6 PVD level 2.5V
PWR_CR_PLS_2V6 7 PVD level 2.6V
PWR_CR_PLS_2V7 5:7 PVD level 2.7V
PWR_CR_PLS_2V8 6:7 PVD level 2.8V
PWR_CR_PLS_2V9 5:7 PVD level 2.9V
PWR_CR_DBP 8 Disable Backup Domain write protection
CSR 0x04 32
PWR_CSR_WUF 0 Wakeup Flag
PWR_CSR_SBF 1 Standby Flag
PWR_CSR_PVDO 2 PVD Output
PWR_CSR_EWUP 8 Enable WKUP pin

FLASH — Flash controller (section 11)

Register Offset Bits Purpose
ACR 0x00 32
FLASH_ACR_LATENCY 0:2 LATENCY[2:0] bits (Latency)
FLASH_ACR_LATENCY_0 — Bit 0
FLASH_ACR_LATENCY_1 0 Bit 0
FLASH_ACR_LATENCY_2 1 Bit 1
FLASH_ACR_HLFCYA 3 Flash Half Cycle Access Enable
FLASH_ACR_PRFTBE 4 Prefetch Buffer Enable
FLASH_ACR_PRFTBS 5 Prefetch Buffer Status
KEYR 0x04 32
FLASH_KEYR_FKEYR 0:31 FPEC Key
OPTKEYR 0x08 32
FLASH_OPTKEYR_OPTKEYR 0:31 Option Byte Key
SR 0x0C 32
FLASH_SR_BSY 0 Busy
FLASH_SR_PGERR 2 Programming Error
FLASH_SR_WRPRTERR 4 Write Protection Error
FLASH_SR_EOP 5 End of operation
CR 0x10 32
FLASH_CR_PG 0 Programming
FLASH_CR_PER 1 Page Erase
FLASH_CR_MER 2 Mass Erase
FLASH_CR_OPTPG 4 Option Byte Programming
FLASH_CR_OPTER 5 Option Byte Erase
FLASH_CR_STRT 6 Start
FLASH_CR_LOCK 7 Lock
FLASH_CR_OPTWRE 9 Option Bytes Write Enable
FLASH_CR_ERRIE 10 Error Interrupt Enable
FLASH_CR_EOPIE 12 End of operation interrupt enable
AR 0x14 32
FLASH_AR_FAR 0:31 Flash Address
OBR 0x1C 32
FLASH_OBR_OPTERR 0 Option Byte Error
FLASH_OBR_RDPRT 1 Read protection
FLASH_OBR_USER 2:9 User Option Bytes
FLASH_OBR_WDG_SW 2 WDG_SW
FLASH_OBR_nRST_STOP 3 nRST_STOP
FLASH_OBR_nRST_STDBY 4 nRST_STDBY
FLASH_OBR_BFB2 5 BFB2
WRPR 0x20 32
FLASH_WRPR_WRP 0:31 Write Protect
KEYR2 0x44 32
SR2 0x4C 32
CR2 0x50 32
AR2 0x54 32

IWDG — Independent watchdog (section 12)

Register Offset Bits Purpose
KR 0x00 32
IWDG_KR_KEY 0:15 Key value (write only, read 0000h)
PR 0x04 32
IWDG_PR_PR 0:2 PR[2:0] (Prescaler divider)
IWDG_PR_PR_0 0 Bit 0
IWDG_PR_PR_1 1 Bit 1
IWDG_PR_PR_2 2 Bit 2
RLR 0x08 32
IWDG_RLR_RL 0:11 Watchdog counter reload value
SR 0x0C 32
IWDG_SR_PVU 0 Watchdog prescaler value update
IWDG_SR_RVU 1 Watchdog counter reload value update

WWDG — Window watchdog (section 12)

Register Offset Bits Purpose
CR 0x00 32
WWDG_CR_T 0:6 T[6:0] bits (7-Bit counter (MSB to LSB))
WWDG_CR_T0 0 Bit 0
WWDG_CR_T1 1 Bit 1
WWDG_CR_T2 2 Bit 2
WWDG_CR_T3 3 Bit 3
WWDG_CR_T4 4 Bit 4
WWDG_CR_T5 5 Bit 5
WWDG_CR_T6 6 Bit 6
WWDG_CR_WDGA 7 Activation bit
CFR 0x04 32
WWDG_CFR_W 0:6 W[6:0] bits (7-bit window value)
WWDG_CFR_W0 0 Bit 0
WWDG_CFR_W1 1 Bit 1
WWDG_CFR_W2 2 Bit 2
WWDG_CFR_W3 3 Bit 3
WWDG_CFR_W4 4 Bit 4
WWDG_CFR_W5 5 Bit 5
WWDG_CFR_W6 6 Bit 6
WWDG_CFR_WDGTB 7:8 WDGTB[1:0] bits (Timer Base)
WWDG_CFR_WDGTB0 7 Bit 0
WWDG_CFR_WDGTB1 8 Bit 1
WWDG_CFR_EWI 9 Early Wakeup Interrupt
SR 0x08 32
WWDG_SR_EWIF 0 Early Wakeup Interrupt Flag

CRC — Checksum (CRC) (section 12)

Register Offset Bits Purpose
DR 0x00 32
CRC_DR_DR 0:31 Data register bits
IDR 0x04 8
CRC_IDR_IDR 0:7 General-purpose 8-bit data register bits
CR 0x08 32
CRC_CR_RESET 0 RESET bit

RTC — Real-time clock (section 12)

Register Offset Bits Purpose
CRH 0x00 16
RTC_CRH_SECIE 0 Second Interrupt Enable
RTC_CRH_ALRIE 1 Alarm Interrupt Enable
RTC_CRH_OWIE 2 OverfloW Interrupt Enable
CRL 0x04 16
RTC_CRL_SECF 0 Second Flag
RTC_CRL_ALRF 1 Alarm Flag
RTC_CRL_OWF 2 OverfloW Flag
RTC_CRL_RSF 3 Registers Synchronized Flag
RTC_CRL_CNF 4 Configuration Flag
RTC_CRL_RTOFF 5 RTC operation OFF
PRLH 0x08 16
RTC_PRLH_PRL 0:3 RTC Prescaler Reload Value High
PRLL 0x0C 16
RTC_PRLL_PRL 0:15 RTC Prescaler Reload Value Low
DIVH 0x10 16
RTC_DIVH_RTC_DIV 0:3 RTC Clock Divider High
DIVL 0x14 16
RTC_DIVL_RTC_DIV 0:15 RTC Clock Divider Low
CNTH 0x18 16
RTC_CNTH_RTC_CNT 0:15 RTC Counter High
CNTL 0x1C 16
RTC_CNTL_RTC_CNT 0:15 RTC Counter Low
ALRH 0x20 16
RTC_ALRH_RTC_ALR 0:15 RTC Alarm High
ALRL 0x24 16
RTC_ALRL_RTC_ALR 0:15 RTC Alarm Low

TIM — Timers (section 13)

Register Offset Bits Purpose
CR1 0x00 16
TIM_CR1_CEN 0 Counter enable
TIM_CR1_UDIS 1 Update disable
TIM_CR1_URS 2 Update request source
TIM_CR1_OPM 3 One pulse mode
TIM_CR1_DIR 4 Direction
TIM_CR1_CMS 5:6 CMS[1:0] bits (Center-aligned mode selection)
TIM_CR1_CMS_0 5 Bit 0
TIM_CR1_CMS_1 6 Bit 1
TIM_CR1_ARPE 7 Auto-reload preload enable
TIM_CR1_CKD 8:9 CKD[1:0] bits (clock division)
TIM_CR1_CKD_0 8 Bit 0
TIM_CR1_CKD_1 9 Bit 1
CR2 0x04 16
TIM_CR2_CCPC 0 Capture/Compare Preloaded Control
TIM_CR2_CCUS 2 Capture/Compare Control Update Selection
TIM_CR2_CCDS 3 Capture/Compare DMA Selection
TIM_CR2_MMS 4:6 MMS[2:0] bits (Master Mode Selection)
TIM_CR2_MMS_0 4 Bit 0
TIM_CR2_MMS_1 5 Bit 1
TIM_CR2_MMS_2 6 Bit 2
TIM_CR2_TI1S 7 TI1 Selection
TIM_CR2_OIS1 8 Output Idle state 1 (OC1 output)
TIM_CR2_OIS1N 9 Output Idle state 1 (OC1N output)
TIM_CR2_OIS2 10 Output Idle state 2 (OC2 output)
TIM_CR2_OIS2N 11 Output Idle state 2 (OC2N output)
TIM_CR2_OIS3 12 Output Idle state 3 (OC3 output)
TIM_CR2_OIS3N 13 Output Idle state 3 (OC3N output)
TIM_CR2_OIS4 14 Output Idle state 4 (OC4 output)
SMCR 0x08 16
TIM_SMCR_SMS 0:2 SMS[2:0] bits (Slave mode selection)
TIM_SMCR_SMS_0 0 Bit 0
TIM_SMCR_SMS_1 1 Bit 1
TIM_SMCR_SMS_2 2 Bit 2
TIM_SMCR_TS 4:6 TS[2:0] bits (Trigger selection)
TIM_SMCR_TS_0 4 Bit 0
TIM_SMCR_TS_1 5 Bit 1
TIM_SMCR_TS_2 6 Bit 2
TIM_SMCR_MSM 7 Master/slave mode
TIM_SMCR_ETF 8:11 ETF[3:0] bits (External trigger filter)
TIM_SMCR_ETF_0 8 Bit 0
TIM_SMCR_ETF_1 9 Bit 1
TIM_SMCR_ETF_2 10 Bit 2
TIM_SMCR_ETF_3 11 Bit 3
TIM_SMCR_ETPS 12:13 ETPS[1:0] bits (External trigger prescaler)
TIM_SMCR_ETPS_0 12 Bit 0
TIM_SMCR_ETPS_1 13 Bit 1
TIM_SMCR_ECE 14 External clock enable
TIM_SMCR_ETP 15 External trigger polarity
DIER 0x0C 16
TIM_DIER_UIE 0 Update interrupt enable
TIM_DIER_CC1IE 1 Capture/Compare 1 interrupt enable
TIM_DIER_CC2IE 2 Capture/Compare 2 interrupt enable
TIM_DIER_CC3IE 3 Capture/Compare 3 interrupt enable
TIM_DIER_CC4IE 4 Capture/Compare 4 interrupt enable
TIM_DIER_COMIE 5 COM interrupt enable
TIM_DIER_TIE 6 Trigger interrupt enable
TIM_DIER_BIE 7 Break interrupt enable
TIM_DIER_UDE 8 Update DMA request enable
TIM_DIER_CC1DE 9 Capture/Compare 1 DMA request enable
TIM_DIER_CC2DE 10 Capture/Compare 2 DMA request enable
TIM_DIER_CC3DE 11 Capture/Compare 3 DMA request enable
TIM_DIER_CC4DE 12 Capture/Compare 4 DMA request enable
TIM_DIER_COMDE 13 COM DMA request enable
TIM_DIER_TDE 14 Trigger DMA request enable
SR 0x10 16
TIM_SR_UIF 0 Update interrupt Flag
TIM_SR_CC1IF 1 Capture/Compare 1 interrupt Flag
TIM_SR_CC2IF 2 Capture/Compare 2 interrupt Flag
TIM_SR_CC3IF 3 Capture/Compare 3 interrupt Flag
TIM_SR_CC4IF 4 Capture/Compare 4 interrupt Flag
TIM_SR_COMIF 5 COM interrupt Flag
TIM_SR_TIF 6 Trigger interrupt Flag
TIM_SR_BIF 7 Break interrupt Flag
TIM_SR_CC1OF 9 Capture/Compare 1 Overcapture Flag
TIM_SR_CC2OF 10 Capture/Compare 2 Overcapture Flag
TIM_SR_CC3OF 11 Capture/Compare 3 Overcapture Flag
TIM_SR_CC4OF 12 Capture/Compare 4 Overcapture Flag
EGR 0x14 16
TIM_EGR_UG 0 Update Generation
TIM_EGR_CC1G 1 Capture/Compare 1 Generation
TIM_EGR_CC2G 2 Capture/Compare 2 Generation
TIM_EGR_CC3G 3 Capture/Compare 3 Generation
TIM_EGR_CC4G 4 Capture/Compare 4 Generation
TIM_EGR_COMG 5 Capture/Compare Control Update Generation
TIM_EGR_TG 6 Trigger Generation
TIM_EGR_BG 7 Break Generation
CCMR1 0x18 16
TIM_CCMR1_CC1S 0:1 CC1S[1:0] bits (Capture/Compare 1 Selection)
TIM_CCMR1_CC1S_0 0 Bit 0
TIM_CCMR1_CC1S_1 1 Bit 1
TIM_CCMR1_OC1FE 2 Output Compare 1 Fast enable
TIM_CCMR1_OC1PE 3 Output Compare 1 Preload enable
TIM_CCMR1_OC1M 4:6 OC1M[2:0] bits (Output Compare 1 Mode)
TIM_CCMR1_OC1M_0 4 Bit 0
TIM_CCMR1_OC1M_1 5 Bit 1
TIM_CCMR1_OC1M_2 6 Bit 2
TIM_CCMR1_OC1CE 7 Output Compare 1Clear Enable
TIM_CCMR1_CC2S 8:9 CC2S[1:0] bits (Capture/Compare 2 Selection)
TIM_CCMR1_CC2S_0 8 Bit 0
TIM_CCMR1_CC2S_1 9 Bit 1
TIM_CCMR1_OC2FE 10 Output Compare 2 Fast enable
TIM_CCMR1_OC2PE 11 Output Compare 2 Preload enable
TIM_CCMR1_OC2M 12:14 OC2M[2:0] bits (Output Compare 2 Mode)
TIM_CCMR1_OC2M_0 12 Bit 0
TIM_CCMR1_OC2M_1 13 Bit 1
TIM_CCMR1_OC2M_2 14 Bit 2
TIM_CCMR1_OC2CE 15 Output Compare 2 Clear Enable
TIM_CCMR1_IC1PSC 2:3 IC1PSC[1:0] bits (Input Capture 1 Prescaler)
TIM_CCMR1_IC1PSC_0 2 Bit 0
TIM_CCMR1_IC1PSC_1 3 Bit 1
TIM_CCMR1_IC1F 4:7 IC1F[3:0] bits (Input Capture 1 Filter)
TIM_CCMR1_IC1F_0 4 Bit 0
TIM_CCMR1_IC1F_1 5 Bit 1
TIM_CCMR1_IC1F_2 6 Bit 2
TIM_CCMR1_IC1F_3 7 Bit 3
TIM_CCMR1_IC2PSC 10:11 IC2PSC[1:0] bits (Input Capture 2 Prescaler)
TIM_CCMR1_IC2PSC_0 10 Bit 0
TIM_CCMR1_IC2PSC_1 11 Bit 1
TIM_CCMR1_IC2F 12:15 IC2F[3:0] bits (Input Capture 2 Filter)
TIM_CCMR1_IC2F_0 12 Bit 0
TIM_CCMR1_IC2F_1 13 Bit 1
TIM_CCMR1_IC2F_2 14 Bit 2
TIM_CCMR1_IC2F_3 15 Bit 3
CCMR2 0x1C 16
TIM_CCMR2_CC3S 0:1 CC3S[1:0] bits (Capture/Compare 3 Selection)
TIM_CCMR2_CC3S_0 0 Bit 0
TIM_CCMR2_CC3S_1 1 Bit 1
TIM_CCMR2_OC3FE 2 Output Compare 3 Fast enable
TIM_CCMR2_OC3PE 3 Output Compare 3 Preload enable
TIM_CCMR2_OC3M 4:6 OC3M[2:0] bits (Output Compare 3 Mode)
TIM_CCMR2_OC3M_0 4 Bit 0
TIM_CCMR2_OC3M_1 5 Bit 1
TIM_CCMR2_OC3M_2 6 Bit 2
TIM_CCMR2_OC3CE 7 Output Compare 3 Clear Enable
TIM_CCMR2_CC4S 8:9 CC4S[1:0] bits (Capture/Compare 4 Selection)
TIM_CCMR2_CC4S_0 8 Bit 0
TIM_CCMR2_CC4S_1 9 Bit 1
TIM_CCMR2_OC4FE 10 Output Compare 4 Fast enable
TIM_CCMR2_OC4PE 11 Output Compare 4 Preload enable
TIM_CCMR2_OC4M 12:14 OC4M[2:0] bits (Output Compare 4 Mode)
TIM_CCMR2_OC4M_0 12 Bit 0
TIM_CCMR2_OC4M_1 13 Bit 1
TIM_CCMR2_OC4M_2 14 Bit 2
TIM_CCMR2_OC4CE 15 Output Compare 4 Clear Enable
TIM_CCMR2_IC3PSC 2:3 IC3PSC[1:0] bits (Input Capture 3 Prescaler)
TIM_CCMR2_IC3PSC_0 2 Bit 0
TIM_CCMR2_IC3PSC_1 3 Bit 1
TIM_CCMR2_IC3F 4:7 IC3F[3:0] bits (Input Capture 3 Filter)
TIM_CCMR2_IC3F_0 4 Bit 0
TIM_CCMR2_IC3F_1 5 Bit 1
TIM_CCMR2_IC3F_2 6 Bit 2
TIM_CCMR2_IC3F_3 7 Bit 3
TIM_CCMR2_IC4PSC 10:11 IC4PSC[1:0] bits (Input Capture 4 Prescaler)
TIM_CCMR2_IC4PSC_0 10 Bit 0
TIM_CCMR2_IC4PSC_1 11 Bit 1
TIM_CCMR2_IC4F 12:15 IC4F[3:0] bits (Input Capture 4 Filter)
TIM_CCMR2_IC4F_0 12 Bit 0
TIM_CCMR2_IC4F_1 13 Bit 1
TIM_CCMR2_IC4F_2 14 Bit 2
TIM_CCMR2_IC4F_3 15 Bit 3
CCER 0x20 16
TIM_CCER_CC1E 0 Capture/Compare 1 output enable
TIM_CCER_CC1P 1 Capture/Compare 1 output Polarity
TIM_CCER_CC1NE 2 Capture/Compare 1 Complementary output enable
TIM_CCER_CC1NP 3 Capture/Compare 1 Complementary output Polarity
TIM_CCER_CC2E 4 Capture/Compare 2 output enable
TIM_CCER_CC2P 5 Capture/Compare 2 output Polarity
TIM_CCER_CC2NE 6 Capture/Compare 2 Complementary output enable
TIM_CCER_CC2NP 7 Capture/Compare 2 Complementary output Polarity
TIM_CCER_CC3E 8 Capture/Compare 3 output enable
TIM_CCER_CC3P 9 Capture/Compare 3 output Polarity
TIM_CCER_CC3NE 10 Capture/Compare 3 Complementary output enable
TIM_CCER_CC3NP 11 Capture/Compare 3 Complementary output Polarity
TIM_CCER_CC4E 12 Capture/Compare 4 output enable
TIM_CCER_CC4P 13 Capture/Compare 4 output Polarity
TIM_CCER_CC4NP 15 Capture/Compare 4 Complementary output Polarity
CNT 0x24 16
TIM_CNT_CNT 0:15 Counter Value
PSC 0x28 16
TIM_PSC_PSC 0:15 Prescaler Value
ARR 0x2C 16
TIM_ARR_ARR 0:15 actual auto-reload Value
RCR 0x30 16
TIM_RCR_REP 0:7 Repetition Counter Value
CCR1 0x34 16
TIM_CCR1_CCR1 0:15 Capture/Compare 1 Value
CCR2 0x38 16
TIM_CCR2_CCR2 0:15 Capture/Compare 2 Value
CCR3 0x3C 16
TIM_CCR3_CCR3 0:15 Capture/Compare 3 Value
CCR4 0x40 16
TIM_CCR4_CCR4 0:15 Capture/Compare 4 Value
BDTR 0x44 16
TIM_BDTR_DTG 0:7 DTG[0:7] bits (Dead-Time Generator set-up)
TIM_BDTR_DTG_0 0 Bit 0
TIM_BDTR_DTG_1 1 Bit 1
TIM_BDTR_DTG_2 2 Bit 2
TIM_BDTR_DTG_3 3 Bit 3
TIM_BDTR_DTG_4 4 Bit 4
TIM_BDTR_DTG_5 5 Bit 5
TIM_BDTR_DTG_6 6 Bit 6
TIM_BDTR_DTG_7 7 Bit 7
TIM_BDTR_LOCK 8:9 LOCK[1:0] bits (Lock Configuration)
TIM_BDTR_LOCK_0 8 Bit 0
TIM_BDTR_LOCK_1 9 Bit 1
TIM_BDTR_OSSI 10 Off-State Selection for Idle mode
TIM_BDTR_OSSR 11 Off-State Selection for Run mode
TIM_BDTR_BKE 12 Break enable
TIM_BDTR_BKP 13 Break Polarity
TIM_BDTR_AOE 14 Automatic Output enable
TIM_BDTR_MOE 15 Main Output enable
DCR 0x48 16
TIM_DCR_DBA 0:4 DBA[4:0] bits (DMA Base Address)
TIM_DCR_DBA_0 0 Bit 0
TIM_DCR_DBA_1 1 Bit 1
TIM_DCR_DBA_2 2 Bit 2
TIM_DCR_DBA_3 3 Bit 3
TIM_DCR_DBA_4 4 Bit 4
TIM_DCR_DBL 8:12 DBL[4:0] bits (DMA Burst Length)
TIM_DCR_DBL_0 8 Bit 0
TIM_DCR_DBL_1 9 Bit 1
TIM_DCR_DBL_2 10 Bit 2
TIM_DCR_DBL_3 11 Bit 3
TIM_DCR_DBL_4 12 Bit 4
DMAR 0x4C 16
TIM_DMAR_DMAB 0:15 DMA register for burst accesses

ADC — ADC (section 14)

Register Offset Bits Purpose
SR 0x00 32
ADC_SR_AWD 0 Analog watchdog flag
ADC_SR_EOC 1 End of conversion
ADC_SR_JEOC 2 Injected channel end of conversion
ADC_SR_JSTRT 3 Injected channel Start flag
ADC_SR_STRT 4 Regular channel Start flag
CR1 0x04 32
ADC_CR1_AWDCH 0:4 AWDCH[4:0] bits (Analog watchdog channel select bits)
ADC_CR1_AWDCH_0 0 Bit 0
ADC_CR1_AWDCH_1 1 Bit 1
ADC_CR1_AWDCH_2 2 Bit 2
ADC_CR1_AWDCH_3 3 Bit 3
ADC_CR1_AWDCH_4 4 Bit 4
ADC_CR1_EOCIE 5 Interrupt enable for EOC
ADC_CR1_AWDIE 6 Analog Watchdog interrupt enable
ADC_CR1_JEOCIE 7 Interrupt enable for injected channels
ADC_CR1_SCAN 8 Scan mode
ADC_CR1_AWDSGL 9 Enable the watchdog on a single channel in scan mode
ADC_CR1_JAUTO 10 Automatic injected group conversion
ADC_CR1_DISCEN 11 Discontinuous mode on regular channels
ADC_CR1_JDISCEN 12 Discontinuous mode on injected channels
ADC_CR1_DISCNUM 13:15 DISCNUM[2:0] bits (Discontinuous mode channel count)
ADC_CR1_DISCNUM_0 13 Bit 0
ADC_CR1_DISCNUM_1 14 Bit 1
ADC_CR1_DISCNUM_2 15 Bit 2
ADC_CR1_DUALMOD 16:19 DUALMOD[3:0] bits (Dual mode selection)
ADC_CR1_DUALMOD_0 16 Bit 0
ADC_CR1_DUALMOD_1 17 Bit 1
ADC_CR1_DUALMOD_2 18 Bit 2
ADC_CR1_DUALMOD_3 19 Bit 3
ADC_CR1_JAWDEN 22 Analog watchdog enable on injected channels
ADC_CR1_AWDEN 23 Analog watchdog enable on regular channels
CR2 0x08 32
ADC_CR2_ADON 0 A/D Converter ON / OFF
ADC_CR2_CONT 1 Continuous Conversion
ADC_CR2_CAL 2 A/D Calibration
ADC_CR2_RSTCAL 3 Reset Calibration
ADC_CR2_DMA 8 Direct Memory access mode
ADC_CR2_ALIGN 11 Data Alignment
ADC_CR2_JEXTSEL 12:14 JEXTSEL[2:0] bits (External event select for injected group)
ADC_CR2_JEXTSEL_0 12 Bit 0
ADC_CR2_JEXTSEL_1 13 Bit 1
ADC_CR2_JEXTSEL_2 14 Bit 2
ADC_CR2_JEXTTRIG 15 External Trigger Conversion mode for injected channels
ADC_CR2_EXTSEL 17:19 EXTSEL[2:0] bits (External Event Select for regular group)
ADC_CR2_EXTSEL_0 17 Bit 0
ADC_CR2_EXTSEL_1 18 Bit 1
ADC_CR2_EXTSEL_2 19 Bit 2
ADC_CR2_EXTTRIG 20 External Trigger Conversion mode for regular channels
ADC_CR2_JSWSTART 21 Start Conversion of injected channels
ADC_CR2_SWSTART 22 Start Conversion of regular channels
ADC_CR2_TSVREFE 23 Temperature Sensor and VREFINT Enable
SMPR1 0x0C 32
ADC_SMPR1_SMP10 0:2 SMP10[2:0] bits (Channel 10 Sample time selection)
ADC_SMPR1_SMP10_0 0 Bit 0
ADC_SMPR1_SMP10_1 1 Bit 1
ADC_SMPR1_SMP10_2 2 Bit 2
ADC_SMPR1_SMP11 3:5 SMP11[2:0] bits (Channel 11 Sample time selection)
ADC_SMPR1_SMP11_0 3 Bit 0
ADC_SMPR1_SMP11_1 4 Bit 1
ADC_SMPR1_SMP11_2 5 Bit 2
ADC_SMPR1_SMP12 6:8 SMP12[2:0] bits (Channel 12 Sample time selection)
ADC_SMPR1_SMP12_0 6 Bit 0
ADC_SMPR1_SMP12_1 7 Bit 1
ADC_SMPR1_SMP12_2 8 Bit 2
ADC_SMPR1_SMP13 9:11 SMP13[2:0] bits (Channel 13 Sample time selection)
ADC_SMPR1_SMP13_0 9 Bit 0
ADC_SMPR1_SMP13_1 10 Bit 1
ADC_SMPR1_SMP13_2 11 Bit 2
ADC_SMPR1_SMP14 12:14 SMP14[2:0] bits (Channel 14 Sample time selection)
ADC_SMPR1_SMP14_0 12 Bit 0
ADC_SMPR1_SMP14_1 13 Bit 1
ADC_SMPR1_SMP14_2 14 Bit 2
ADC_SMPR1_SMP15 15:17 SMP15[2:0] bits (Channel 15 Sample time selection)
ADC_SMPR1_SMP15_0 15 Bit 0
ADC_SMPR1_SMP15_1 16 Bit 1
ADC_SMPR1_SMP15_2 17 Bit 2
ADC_SMPR1_SMP16 18:20 SMP16[2:0] bits (Channel 16 Sample time selection)
ADC_SMPR1_SMP16_0 18 Bit 0
ADC_SMPR1_SMP16_1 19 Bit 1
ADC_SMPR1_SMP16_2 20 Bit 2
ADC_SMPR1_SMP17 21:23 SMP17[2:0] bits (Channel 17 Sample time selection)
ADC_SMPR1_SMP17_0 21 Bit 0
ADC_SMPR1_SMP17_1 22 Bit 1
ADC_SMPR1_SMP17_2 23 Bit 2
SMPR2 0x10 32
ADC_SMPR2_SMP0 0:2 SMP0[2:0] bits (Channel 0 Sample time selection)
ADC_SMPR2_SMP0_0 0 Bit 0
ADC_SMPR2_SMP0_1 1 Bit 1
ADC_SMPR2_SMP0_2 2 Bit 2
ADC_SMPR2_SMP1 3:5 SMP1[2:0] bits (Channel 1 Sample time selection)
ADC_SMPR2_SMP1_0 3 Bit 0
ADC_SMPR2_SMP1_1 4 Bit 1
ADC_SMPR2_SMP1_2 5 Bit 2
ADC_SMPR2_SMP2 6:8 SMP2[2:0] bits (Channel 2 Sample time selection)
ADC_SMPR2_SMP2_0 6 Bit 0
ADC_SMPR2_SMP2_1 7 Bit 1
ADC_SMPR2_SMP2_2 8 Bit 2
ADC_SMPR2_SMP3 9:11 SMP3[2:0] bits (Channel 3 Sample time selection)
ADC_SMPR2_SMP3_0 9 Bit 0
ADC_SMPR2_SMP3_1 10 Bit 1
ADC_SMPR2_SMP3_2 11 Bit 2
ADC_SMPR2_SMP4 12:14 SMP4[2:0] bits (Channel 4 Sample time selection)
ADC_SMPR2_SMP4_0 12 Bit 0
ADC_SMPR2_SMP4_1 13 Bit 1
ADC_SMPR2_SMP4_2 14 Bit 2
ADC_SMPR2_SMP5 15:17 SMP5[2:0] bits (Channel 5 Sample time selection)
ADC_SMPR2_SMP5_0 15 Bit 0
ADC_SMPR2_SMP5_1 16 Bit 1
ADC_SMPR2_SMP5_2 17 Bit 2
ADC_SMPR2_SMP6 18:20 SMP6[2:0] bits (Channel 6 Sample time selection)
ADC_SMPR2_SMP6_0 18 Bit 0
ADC_SMPR2_SMP6_1 19 Bit 1
ADC_SMPR2_SMP6_2 20 Bit 2
ADC_SMPR2_SMP7 21:23 SMP7[2:0] bits (Channel 7 Sample time selection)
ADC_SMPR2_SMP7_0 21 Bit 0
ADC_SMPR2_SMP7_1 22 Bit 1
ADC_SMPR2_SMP7_2 23 Bit 2
ADC_SMPR2_SMP8 24:26 SMP8[2:0] bits (Channel 8 Sample time selection)
ADC_SMPR2_SMP8_0 24 Bit 0
ADC_SMPR2_SMP8_1 25 Bit 1
ADC_SMPR2_SMP8_2 26 Bit 2
ADC_SMPR2_SMP9 27:29 SMP9[2:0] bits (Channel 9 Sample time selection)
ADC_SMPR2_SMP9_0 27 Bit 0
ADC_SMPR2_SMP9_1 28 Bit 1
ADC_SMPR2_SMP9_2 29 Bit 2
JOFR1 0x14 32
ADC_JOFR1_JOFFSET1 0:11 Data offset for injected channel 1
JOFR2 0x18 32
ADC_JOFR2_JOFFSET2 0:11 Data offset for injected channel 2
JOFR3 0x1C 32
ADC_JOFR3_JOFFSET3 0:11 Data offset for injected channel 3
JOFR4 0x20 32
ADC_JOFR4_JOFFSET4 0:11 Data offset for injected channel 4
HTR 0x24 32
ADC_HTR_HT 0:11 Analog watchdog high threshold
LTR 0x28 32
ADC_LTR_LT 0:11 Analog watchdog low threshold
SQR1 0x2C 32
ADC_SQR1_SQ13 0:4 SQ13[4:0] bits (13th conversion in regular sequence)
ADC_SQR1_SQ13_0 0 Bit 0
ADC_SQR1_SQ13_1 1 Bit 1
ADC_SQR1_SQ13_2 2 Bit 2
ADC_SQR1_SQ13_3 3 Bit 3
ADC_SQR1_SQ13_4 4 Bit 4
ADC_SQR1_SQ14 5:9 SQ14[4:0] bits (14th conversion in regular sequence)
ADC_SQR1_SQ14_0 5 Bit 0
ADC_SQR1_SQ14_1 6 Bit 1
ADC_SQR1_SQ14_2 7 Bit 2
ADC_SQR1_SQ14_3 8 Bit 3
ADC_SQR1_SQ14_4 9 Bit 4
ADC_SQR1_SQ15 10:14 SQ15[4:0] bits (15th conversion in regular sequence)
ADC_SQR1_SQ15_0 10 Bit 0
ADC_SQR1_SQ15_1 11 Bit 1
ADC_SQR1_SQ15_2 12 Bit 2
ADC_SQR1_SQ15_3 13 Bit 3
ADC_SQR1_SQ15_4 14 Bit 4
ADC_SQR1_SQ16 15:19 SQ16[4:0] bits (16th conversion in regular sequence)
ADC_SQR1_SQ16_0 15 Bit 0
ADC_SQR1_SQ16_1 16 Bit 1
ADC_SQR1_SQ16_2 17 Bit 2
ADC_SQR1_SQ16_3 18 Bit 3
ADC_SQR1_SQ16_4 19 Bit 4
ADC_SQR1_L 20:23 L[3:0] bits (Regular channel sequence length)
ADC_SQR1_L_0 20 Bit 0
ADC_SQR1_L_1 21 Bit 1
ADC_SQR1_L_2 22 Bit 2
ADC_SQR1_L_3 23 Bit 3
SQR2 0x30 32
ADC_SQR2_SQ7 0:4 SQ7[4:0] bits (7th conversion in regular sequence)
ADC_SQR2_SQ7_0 0 Bit 0
ADC_SQR2_SQ7_1 1 Bit 1
ADC_SQR2_SQ7_2 2 Bit 2
ADC_SQR2_SQ7_3 3 Bit 3
ADC_SQR2_SQ7_4 4 Bit 4
ADC_SQR2_SQ8 5:9 SQ8[4:0] bits (8th conversion in regular sequence)
ADC_SQR2_SQ8_0 5 Bit 0
ADC_SQR2_SQ8_1 6 Bit 1
ADC_SQR2_SQ8_2 7 Bit 2
ADC_SQR2_SQ8_3 8 Bit 3
ADC_SQR2_SQ8_4 9 Bit 4
ADC_SQR2_SQ9 10:14 SQ9[4:0] bits (9th conversion in regular sequence)
ADC_SQR2_SQ9_0 10 Bit 0
ADC_SQR2_SQ9_1 11 Bit 1
ADC_SQR2_SQ9_2 12 Bit 2
ADC_SQR2_SQ9_3 13 Bit 3
ADC_SQR2_SQ9_4 14 Bit 4
ADC_SQR2_SQ10 15:19 SQ10[4:0] bits (10th conversion in regular sequence)
ADC_SQR2_SQ10_0 15 Bit 0
ADC_SQR2_SQ10_1 16 Bit 1
ADC_SQR2_SQ10_2 17 Bit 2
ADC_SQR2_SQ10_3 18 Bit 3
ADC_SQR2_SQ10_4 19 Bit 4
ADC_SQR2_SQ11 20:24 SQ11[4:0] bits (11th conversion in regular sequence)
ADC_SQR2_SQ11_0 20 Bit 0
ADC_SQR2_SQ11_1 21 Bit 1
ADC_SQR2_SQ11_2 22 Bit 2
ADC_SQR2_SQ11_3 23 Bit 3
ADC_SQR2_SQ11_4 24 Bit 4
ADC_SQR2_SQ12 25:29 SQ12[4:0] bits (12th conversion in regular sequence)
ADC_SQR2_SQ12_0 25 Bit 0
ADC_SQR2_SQ12_1 26 Bit 1
ADC_SQR2_SQ12_2 27 Bit 2
ADC_SQR2_SQ12_3 28 Bit 3
ADC_SQR2_SQ12_4 29 Bit 4
SQR3 0x34 32
ADC_SQR3_SQ1 0:4 SQ1[4:0] bits (1st conversion in regular sequence)
ADC_SQR3_SQ1_0 0 Bit 0
ADC_SQR3_SQ1_1 1 Bit 1
ADC_SQR3_SQ1_2 2 Bit 2
ADC_SQR3_SQ1_3 3 Bit 3
ADC_SQR3_SQ1_4 4 Bit 4
ADC_SQR3_SQ2 5:9 SQ2[4:0] bits (2nd conversion in regular sequence)
ADC_SQR3_SQ2_0 5 Bit 0
ADC_SQR3_SQ2_1 6 Bit 1
ADC_SQR3_SQ2_2 7 Bit 2
ADC_SQR3_SQ2_3 8 Bit 3
ADC_SQR3_SQ2_4 9 Bit 4
ADC_SQR3_SQ3 10:14 SQ3[4:0] bits (3rd conversion in regular sequence)
ADC_SQR3_SQ3_0 10 Bit 0
ADC_SQR3_SQ3_1 11 Bit 1
ADC_SQR3_SQ3_2 12 Bit 2
ADC_SQR3_SQ3_3 13 Bit 3
ADC_SQR3_SQ3_4 14 Bit 4
ADC_SQR3_SQ4 15:19 SQ4[4:0] bits (4th conversion in regular sequence)
ADC_SQR3_SQ4_0 15 Bit 0
ADC_SQR3_SQ4_1 16 Bit 1
ADC_SQR3_SQ4_2 17 Bit 2
ADC_SQR3_SQ4_3 18 Bit 3
ADC_SQR3_SQ4_4 19 Bit 4
ADC_SQR3_SQ5 20:24 SQ5[4:0] bits (5th conversion in regular sequence)
ADC_SQR3_SQ5_0 20 Bit 0
ADC_SQR3_SQ5_1 21 Bit 1
ADC_SQR3_SQ5_2 22 Bit 2
ADC_SQR3_SQ5_3 23 Bit 3
ADC_SQR3_SQ5_4 24 Bit 4
ADC_SQR3_SQ6 25:29 SQ6[4:0] bits (6th conversion in regular sequence)
ADC_SQR3_SQ6_0 25 Bit 0
ADC_SQR3_SQ6_1 26 Bit 1
ADC_SQR3_SQ6_2 27 Bit 2
ADC_SQR3_SQ6_3 28 Bit 3
ADC_SQR3_SQ6_4 29 Bit 4
JSQR 0x38 32
ADC_JSQR_JSQ1 0:4 JSQ1[4:0] bits (1st conversion in injected sequence)
ADC_JSQR_JSQ1_0 0 Bit 0
ADC_JSQR_JSQ1_1 1 Bit 1
ADC_JSQR_JSQ1_2 2 Bit 2
ADC_JSQR_JSQ1_3 3 Bit 3
ADC_JSQR_JSQ1_4 4 Bit 4
ADC_JSQR_JSQ2 5:9 JSQ2[4:0] bits (2nd conversion in injected sequence)
ADC_JSQR_JSQ2_0 5 Bit 0
ADC_JSQR_JSQ2_1 6 Bit 1
ADC_JSQR_JSQ2_2 7 Bit 2
ADC_JSQR_JSQ2_3 8 Bit 3
ADC_JSQR_JSQ2_4 9 Bit 4
ADC_JSQR_JSQ3 10:14 JSQ3[4:0] bits (3rd conversion in injected sequence)
ADC_JSQR_JSQ3_0 10 Bit 0
ADC_JSQR_JSQ3_1 11 Bit 1
ADC_JSQR_JSQ3_2 12 Bit 2
ADC_JSQR_JSQ3_3 13 Bit 3
ADC_JSQR_JSQ3_4 14 Bit 4
ADC_JSQR_JSQ4 15:19 JSQ4[4:0] bits (4th conversion in injected sequence)
ADC_JSQR_JSQ4_0 15 Bit 0
ADC_JSQR_JSQ4_1 16 Bit 1
ADC_JSQR_JSQ4_2 17 Bit 2
ADC_JSQR_JSQ4_3 18 Bit 3
ADC_JSQR_JSQ4_4 19 Bit 4
ADC_JSQR_JL 20:21 JL[1:0] bits (Injected Sequence length)
ADC_JSQR_JL_0 20 Bit 0
ADC_JSQR_JL_1 21 Bit 1
JDR1 0x3C 32
ADC_JDR1_JDATA 0:15 Injected data
JDR2 0x40 32
ADC_JDR2_JDATA 0:15 Injected data
JDR3 0x44 32
ADC_JDR3_JDATA 0:15 Injected data
JDR4 0x48 32
ADC_JDR4_JDATA 0:15 Injected data
DR 0x4C 32
ADC_DR_DATA 0:15 Regular data
ADC_DR_ADC2DATA 16:31 ADC2 data

DAC — DAC (section 15)

Register Offset Bits Purpose
CR 0x00 32
DAC_CR_EN1 0 DAC channel1 enable
DAC_CR_BOFF1 1 DAC channel1 output buffer disable
DAC_CR_TEN1 2 DAC channel1 Trigger enable
DAC_CR_TSEL1 3:5 TSEL1[2:0] (DAC channel1 Trigger selection)
DAC_CR_TSEL1_0 3 Bit 0
DAC_CR_TSEL1_1 4 Bit 1
DAC_CR_TSEL1_2 5 Bit 2
DAC_CR_WAVE1 6:7 WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
DAC_CR_WAVE1_0 6 Bit 0
DAC_CR_WAVE1_1 7 Bit 1
DAC_CR_MAMP1 8:11 MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
DAC_CR_MAMP1_0 8 Bit 0
DAC_CR_MAMP1_1 9 Bit 1
DAC_CR_MAMP1_2 10 Bit 2
DAC_CR_MAMP1_3 11 Bit 3
DAC_CR_DMAEN1 12 DAC channel1 DMA enable
DAC_CR_EN2 16 DAC channel2 enable
DAC_CR_BOFF2 17 DAC channel2 output buffer disable
DAC_CR_TEN2 18 DAC channel2 Trigger enable
DAC_CR_TSEL2 19:21 TSEL2[2:0] (DAC channel2 Trigger selection)
DAC_CR_TSEL2_0 19 Bit 0
DAC_CR_TSEL2_1 20 Bit 1
DAC_CR_TSEL2_2 21 Bit 2
DAC_CR_WAVE2 22:23 WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)
DAC_CR_WAVE2_0 22 Bit 0
DAC_CR_WAVE2_1 23 Bit 1
DAC_CR_MAMP2 24:27 MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)
DAC_CR_MAMP2_0 24 Bit 0
DAC_CR_MAMP2_1 25 Bit 1
DAC_CR_MAMP2_2 26 Bit 2
DAC_CR_MAMP2_3 27 Bit 3
DAC_CR_DMAEN2 28 DAC channel2 DMA enabled
DAC_CR_DMAUDRIE1 13 DAC channel1 DMA underrun interrupt enable
DAC_CR_DMAUDRIE2 29 DAC channel2 DMA underrun interrupt enable
SWTRIGR 0x04 32
DAC_SWTRIGR_SWTRIG1 0 DAC channel1 software trigger
DAC_SWTRIGR_SWTRIG2 1 DAC channel2 software trigger
DHR12R1 0x08 32
DAC_DHR12R1_DACC1DHR 0:11 DAC channel1 12-bit Right aligned data
DHR12L1 0x0C 32
DAC_DHR12L1_DACC1DHR 4:15 DAC channel1 12-bit Left aligned data
DHR8R1 0x10 32
DAC_DHR8R1_DACC1DHR 0:7 DAC channel1 8-bit Right aligned data
DHR12R2 0x14 32
DAC_DHR12R2_DACC2DHR 0:11 DAC channel2 12-bit Right aligned data
DHR12L2 0x18 32
DAC_DHR12L2_DACC2DHR 4:15 DAC channel2 12-bit Left aligned data
DHR8R2 0x1C 32
DAC_DHR8R2_DACC2DHR 0:7 DAC channel2 8-bit Right aligned data
DHR12RD 0x20 32
DAC_DHR12RD_DACC1DHR 0:11 DAC channel1 12-bit Right aligned data
DAC_DHR12RD_DACC2DHR 16:27 DAC channel2 12-bit Right aligned data
DHR12LD 0x24 32
DAC_DHR12LD_DACC1DHR 4:15 DAC channel1 12-bit Left aligned data
DAC_DHR12LD_DACC2DHR 20:31 DAC channel2 12-bit Left aligned data
DHR8RD 0x28 32
DAC_DHR8RD_DACC1DHR 0:7 DAC channel1 8-bit Right aligned data
DAC_DHR8RD_DACC2DHR 8:15 DAC channel2 8-bit Right aligned data
DOR1 0x2C 32
DAC_DOR1_DACC1DOR 0:11 DAC channel1 data output
DOR2 0x30 32
DAC_DOR2_DACC2DOR 0:11 DAC channel2 data output
SR 0x34 32
DAC_SR_DMAUDR1 13 DAC channel1 DMA underrun flag
DAC_SR_DMAUDR2 29 DAC channel2 DMA underrun flag

USART — UART / USART (section 16)

Register Offset Bits Purpose
SR 0x00 16
USART_SR_PE 0 Parity Error
USART_SR_FE 1 Framing Error
USART_SR_NE 2 Noise Error Flag
USART_SR_ORE 3 OverRun Error
USART_SR_IDLE 4 IDLE line detected
USART_SR_RXNE 5 Read Data Register Not Empty
USART_SR_TC 6 Transmission Complete
USART_SR_TXE 7 Transmit Data Register Empty
USART_SR_LBD 8 LIN Break Detection Flag
USART_SR_CTS 9 CTS Flag
DR 0x04 16
USART_DR_DR 0:8 Data value
BRR 0x08 16
USART_BRR_DIV_Fraction 0:3 Fraction of USARTDIV
USART_BRR_DIV_Mantissa 4:15 Mantissa of USARTDIV
CR1 0x0C 16
USART_CR1_SBK 0 Send Break
USART_CR1_RWU 1 Receiver wakeup
USART_CR1_RE 2 Receiver Enable
USART_CR1_TE 3 Transmitter Enable
USART_CR1_IDLEIE 4 IDLE Interrupt Enable
USART_CR1_RXNEIE 5 RXNE Interrupt Enable
USART_CR1_TCIE 6 Transmission Complete Interrupt Enable
USART_CR1_TXEIE 7 PE Interrupt Enable
USART_CR1_PEIE 8 PE Interrupt Enable
USART_CR1_PS 9 Parity Selection
USART_CR1_PCE 10 Parity Control Enable
USART_CR1_WAKE 11 Wakeup method
USART_CR1_M 12 Word length
USART_CR1_UE 13 USART Enable
USART_CR1_OVER8 15 USART Oversmapling 8-bits
CR2 0x10 16
USART_CR2_ADD 0:3 Address of the USART node
USART_CR2_LBDL 5 LIN Break Detection Length
USART_CR2_LBDIE 6 LIN Break Detection Interrupt Enable
USART_CR2_LBCL 8 Last Bit Clock pulse
USART_CR2_CPHA 9 Clock Phase
USART_CR2_CPOL 10 Clock Polarity
USART_CR2_CLKEN 11 Clock Enable
USART_CR2_STOP 12:13 STOP[1:0] bits (STOP bits)
USART_CR2_STOP_0 12 Bit 0
USART_CR2_STOP_1 13 Bit 1
USART_CR2_LINEN 14 LIN mode enable
CR3 0x14 16
USART_CR3_EIE 0 Error Interrupt Enable
USART_CR3_IREN 1 IrDA mode Enable
USART_CR3_IRLP 2 IrDA Low-Power
USART_CR3_HDSEL 3 Half-Duplex Selection
USART_CR3_NACK 4 Smartcard NACK enable
USART_CR3_SCEN 5 Smartcard mode enable
USART_CR3_DMAR 6 DMA Enable Receiver
USART_CR3_DMAT 7 DMA Enable Transmitter
USART_CR3_RTSE 8 RTS Enable
USART_CR3_CTSE 9 CTS Enable
USART_CR3_CTSIE 10 CTS Interrupt Enable
USART_CR3_ONEBIT 11 One Bit method
GTPR 0x18 16
USART_GTPR_PSC 0:7 PSC[7:0] bits (Prescaler value)
USART_GTPR_PSC_0 0 Bit 0
USART_GTPR_PSC_1 1 Bit 1
USART_GTPR_PSC_2 2 Bit 2
USART_GTPR_PSC_3 3 Bit 3
USART_GTPR_PSC_4 4 Bit 4
USART_GTPR_PSC_5 5 Bit 5
USART_GTPR_PSC_6 6 Bit 6
USART_GTPR_PSC_7 7 Bit 7
USART_GTPR_GT 8:15 Guard time value

I2C — I²C (section 17)

Register Offset Bits Purpose
CR1 0x00 16
I2C_CR1_PE 0 Peripheral Enable
I2C_CR1_SMBUS 1 SMBus Mode
I2C_CR1_SMBTYPE 3 SMBus Type
I2C_CR1_ENARP 4 ARP Enable
I2C_CR1_ENPEC 5 PEC Enable
I2C_CR1_ENGC 6 General Call Enable
I2C_CR1_NOSTRETCH 7 Clock Stretching Disable (Slave mode)
I2C_CR1_START 8 Start Generation
I2C_CR1_STOP 9 Stop Generation
I2C_CR1_ACK 10 Acknowledge Enable
I2C_CR1_POS 11 Acknowledge/PEC Position (for data reception)
I2C_CR1_PEC 12 Packet Error Checking
I2C_CR1_ALERT 13 SMBus Alert
I2C_CR1_SWRST 15 Software Reset
CR2 0x04 16
I2C_CR2_FREQ 0:5 FREQ[5:0] bits (Peripheral Clock Frequency)
I2C_CR2_FREQ_0 0 Bit 0
I2C_CR2_FREQ_1 1 Bit 1
I2C_CR2_FREQ_2 2 Bit 2
I2C_CR2_FREQ_3 3 Bit 3
I2C_CR2_FREQ_4 4 Bit 4
I2C_CR2_FREQ_5 5 Bit 5
I2C_CR2_ITERREN 8 Error Interrupt Enable
I2C_CR2_ITEVTEN 9 Event Interrupt Enable
I2C_CR2_ITBUFEN 10 Buffer Interrupt Enable
I2C_CR2_DMAEN 11 DMA Requests Enable
I2C_CR2_LAST 12 DMA Last Transfer
OAR1 0x08 16
I2C_OAR1_ADD1_7 1:7 Interface Address
I2C_OAR1_ADD8_9 8:9 Interface Address
I2C_OAR1_ADD0 0 Bit 0
I2C_OAR1_ADD1 1 Bit 1
I2C_OAR1_ADD2 2 Bit 2
I2C_OAR1_ADD3 3 Bit 3
I2C_OAR1_ADD4 4 Bit 4
I2C_OAR1_ADD5 5 Bit 5
I2C_OAR1_ADD6 6 Bit 6
I2C_OAR1_ADD7 7 Bit 7
I2C_OAR1_ADD8 8 Bit 8
I2C_OAR1_ADD9 9 Bit 9
I2C_OAR1_ADDMODE 15 Addressing Mode (Slave mode)
OAR2 0x0C 16
I2C_OAR2_ENDUAL 0 Dual addressing mode enable
I2C_OAR2_ADD2 1:7 Interface address
DR 0x10 16
I2C_DR_DR 0:7 8-bit Data Register
SR1 0x14 16
I2C_SR1_SB 0 Start Bit (Master mode)
I2C_SR1_ADDR 1 Address sent (master mode)/matched (slave mode)
I2C_SR1_BTF 2 Byte Transfer Finished
I2C_SR1_ADD10 3 10-bit header sent (Master mode)
I2C_SR1_STOPF 4 Stop detection (Slave mode)
I2C_SR1_RXNE 6 Data Register not Empty (receivers)
I2C_SR1_TXE 7 Data Register Empty (transmitters)
I2C_SR1_BERR 8 Bus Error
I2C_SR1_ARLO 9 Arbitration Lost (master mode)
I2C_SR1_AF 10 Acknowledge Failure
I2C_SR1_OVR 11 Overrun/Underrun
I2C_SR1_PECERR 12 PEC Error in reception
I2C_SR1_TIMEOUT 14 Timeout or Tlow Error
I2C_SR1_SMBALERT 15 SMBus Alert
SR2 0x18 16
I2C_SR2_MSL 0 Master/Slave
I2C_SR2_BUSY 1 Bus Busy
I2C_SR2_TRA 2 Transmitter/Receiver
I2C_SR2_GENCALL 4 General Call Address (Slave mode)
I2C_SR2_SMBDEFAULT 5 SMBus Device Default Address (Slave mode)
I2C_SR2_SMBHOST 6 SMBus Host Header (Slave mode)
I2C_SR2_DUALF 7 Dual Flag (Slave mode)
I2C_SR2_PEC 8:15 Packet Error Checking Register
CCR 0x1C 16
I2C_CCR_CCR 0:11 Clock Control Register in Fast/Standard mode (Master mode)
I2C_CCR_DUTY 14 Fast Mode Duty Cycle
I2C_CCR_FS 15 I2C Master Mode Selection
TRISE 0x20 16
I2C_TRISE_TRISE 0:5 Maximum Rise Time in Fast/Standard mode (Master mode)

SPI — SPI (section 18)

Register Offset Bits Purpose
CR1 0x00 16
SPI_CR1_CPHA 0 Clock Phase
SPI_CR1_CPOL 1 Clock Polarity
SPI_CR1_MSTR 2 Master Selection
SPI_CR1_BR 3:5 BR[2:0] bits (Baud Rate Control)
SPI_CR1_BR_0 3 Bit 0
SPI_CR1_BR_1 4 Bit 1
SPI_CR1_BR_2 5 Bit 2
SPI_CR1_SPE 6 SPI Enable
SPI_CR1_LSBFIRST 7 Frame Format
SPI_CR1_SSI 8 Internal slave select
SPI_CR1_SSM 9 Software slave management
SPI_CR1_RXONLY 10 Receive only
SPI_CR1_DFF 11 Data Frame Format
SPI_CR1_CRCNEXT 12 Transmit CRC next
SPI_CR1_CRCEN 13 Hardware CRC calculation enable
SPI_CR1_BIDIOE 14 Output enable in bidirectional mode
SPI_CR1_BIDIMODE 15 Bidirectional data mode enable
CR2 0x04 16
SPI_CR2_RXDMAEN 0 Rx Buffer DMA Enable
SPI_CR2_TXDMAEN 1 Tx Buffer DMA Enable
SPI_CR2_SSOE 2 SS Output Enable
SPI_CR2_ERRIE 5 Error Interrupt Enable
SPI_CR2_RXNEIE 6 RX buffer Not Empty Interrupt Enable
SPI_CR2_TXEIE 7 Tx buffer Empty Interrupt Enable
SR 0x08 16
SPI_SR_RXNE 0 Receive buffer Not Empty
SPI_SR_TXE 1 Transmit buffer Empty
SPI_SR_CHSIDE 2 Channel side
SPI_SR_UDR 3 Underrun flag
SPI_SR_CRCERR 4 CRC Error flag
SPI_SR_MODF 5 Mode fault
SPI_SR_OVR 6 Overrun flag
SPI_SR_BSY 7 Busy flag
DR 0x0C 16
SPI_DR_DR 0:15 Data Register
CRCPR 0x10 16
SPI_CRCPR_CRCPOLY 0:15 CRC polynomial register
RXCRCR 0x14 16
SPI_RXCRCR_RXCRC 0:15 Rx CRC Register
TXCRCR 0x18 16
SPI_TXCRCR_TXCRC 0:15 Tx CRC Register
I2SCFGR 0x1C 16
SPI_I2SCFGR_CHLEN 0 Channel length (number of bits per audio channel)
SPI_I2SCFGR_DATLEN 1:2 DATLEN[1:0] bits (Data length to be transferred)
SPI_I2SCFGR_DATLEN_0 1 Bit 0
SPI_I2SCFGR_DATLEN_1 2 Bit 1
SPI_I2SCFGR_CKPOL 3 steady state clock polarity
SPI_I2SCFGR_I2SSTD 4:5 I2SSTD[1:0] bits (I2S standard selection)
SPI_I2SCFGR_I2SSTD_0 4 Bit 0
SPI_I2SCFGR_I2SSTD_1 5 Bit 1
SPI_I2SCFGR_PCMSYNC 7 PCM frame synchronization
SPI_I2SCFGR_I2SCFG 8:9 I2SCFG[1:0] bits (I2S configuration mode)
SPI_I2SCFGR_I2SCFG_0 8 Bit 0
SPI_I2SCFGR_I2SCFG_1 9 Bit 1
SPI_I2SCFGR_I2SE 10 I2S Enable
SPI_I2SCFGR_I2SMOD 11 I2S mode selection
I2SPR 0x20 16
SPI_I2SPR_I2SDIV 0:7 I2S Linear prescaler
SPI_I2SPR_ODD 8 Odd factor for the prescaler
SPI_I2SPR_MCKOE 9 Master Clock Output Enable

CAN — CAN (section 19)

Register Offset Bits Purpose
MCR 0x00 32
CAN_MCR_INRQ 0 Initialization Request
CAN_MCR_SLEEP 1 Sleep Mode Request
CAN_MCR_TXFP 2 Transmit FIFO Priority
CAN_MCR_RFLM 3 Receive FIFO Locked Mode
CAN_MCR_NART 4 No Automatic Retransmission
CAN_MCR_AWUM 5 Automatic Wakeup Mode
CAN_MCR_ABOM 6 Automatic Bus-Off Management
CAN_MCR_TTCM 7 Time Triggered Communication Mode
CAN_MCR_RESET 15 CAN software master reset
MSR 0x04 32
CAN_MSR_INAK 0 Initialization Acknowledge
CAN_MSR_SLAK 1 Sleep Acknowledge
CAN_MSR_ERRI 2 Error Interrupt
CAN_MSR_WKUI 3 Wakeup Interrupt
CAN_MSR_SLAKI 4 Sleep Acknowledge Interrupt
CAN_MSR_TXM 8 Transmit Mode
CAN_MSR_RXM 9 Receive Mode
CAN_MSR_SAMP 10 Last Sample Point
CAN_MSR_RX 11 CAN Rx Signal
TSR 0x08 32
CAN_TSR_RQCP0 0 Request Completed Mailbox0
CAN_TSR_TXOK0 1 Transmission OK of Mailbox0
CAN_TSR_ALST0 2 Arbitration Lost for Mailbox0
CAN_TSR_TERR0 3 Transmission Error of Mailbox0
CAN_TSR_ABRQ0 7 Abort Request for Mailbox0
CAN_TSR_RQCP1 8 Request Completed Mailbox1
CAN_TSR_TXOK1 9 Transmission OK of Mailbox1
CAN_TSR_ALST1 10 Arbitration Lost for Mailbox1
CAN_TSR_TERR1 11 Transmission Error of Mailbox1
CAN_TSR_ABRQ1 15 Abort Request for Mailbox 1
CAN_TSR_RQCP2 16 Request Completed Mailbox2
CAN_TSR_TXOK2 17 Transmission OK of Mailbox 2
CAN_TSR_ALST2 18 Arbitration Lost for mailbox 2
CAN_TSR_TERR2 19 Transmission Error of Mailbox 2
CAN_TSR_ABRQ2 23 Abort Request for Mailbox 2
CAN_TSR_CODE 24:25 Mailbox Code
CAN_TSR_TME 26:28 TME[2:0] bits
CAN_TSR_TME0 26 Transmit Mailbox 0 Empty
CAN_TSR_TME1 27 Transmit Mailbox 1 Empty
CAN_TSR_TME2 28 Transmit Mailbox 2 Empty
CAN_TSR_LOW 29:31 LOW[2:0] bits
CAN_TSR_LOW0 29 Lowest Priority Flag for Mailbox 0
CAN_TSR_LOW1 30 Lowest Priority Flag for Mailbox 1
CAN_TSR_LOW2 31 Lowest Priority Flag for Mailbox 2
RF0R 0x0C 32
CAN_RF0R_FMP0 0:1 FIFO 0 Message Pending
CAN_RF0R_FULL0 3 FIFO 0 Full
CAN_RF0R_FOVR0 4 FIFO 0 Overrun
CAN_RF0R_RFOM0 5 Release FIFO 0 Output Mailbox
RF1R 0x10 32
CAN_RF1R_FMP1 0:1 FIFO 1 Message Pending
CAN_RF1R_FULL1 3 FIFO 1 Full
CAN_RF1R_FOVR1 4 FIFO 1 Overrun
CAN_RF1R_RFOM1 5 Release FIFO 1 Output Mailbox
IER 0x14 32
CAN_IER_TMEIE 0 Transmit Mailbox Empty Interrupt Enable
CAN_IER_FMPIE0 1 FIFO Message Pending Interrupt Enable
CAN_IER_FFIE0 2 FIFO Full Interrupt Enable
CAN_IER_FOVIE0 3 FIFO Overrun Interrupt Enable
CAN_IER_FMPIE1 4 FIFO Message Pending Interrupt Enable
CAN_IER_FFIE1 5 FIFO Full Interrupt Enable
CAN_IER_FOVIE1 6 FIFO Overrun Interrupt Enable
CAN_IER_EWGIE 8 Error Warning Interrupt Enable
CAN_IER_EPVIE 9 Error Passive Interrupt Enable
CAN_IER_BOFIE 10 Bus-Off Interrupt Enable
CAN_IER_LECIE 11 Last Error Code Interrupt Enable
CAN_IER_ERRIE 15 Error Interrupt Enable
CAN_IER_WKUIE 16 Wakeup Interrupt Enable
CAN_IER_SLKIE 17 Sleep Interrupt Enable
ESR 0x18 32
CAN_ESR_EWGF 0 Error Warning Flag
CAN_ESR_EPVF 1 Error Passive Flag
CAN_ESR_BOFF 2 Bus-Off Flag
CAN_ESR_LEC 4:6 LEC[2:0] bits (Last Error Code)
CAN_ESR_LEC_0 4 Bit 0
CAN_ESR_LEC_1 5 Bit 1
CAN_ESR_LEC_2 6 Bit 2
CAN_ESR_TEC 16:23 Least significant byte of the 9-bit Transmit Error Counter
CAN_ESR_REC 24:31 Receive Error Counter
BTR 0x1C 32
CAN_BTR_BRP 0:9 Baud Rate Prescaler
CAN_BTR_TS1 16:19 Time Segment 1
CAN_BTR_TS2 20:22 Time Segment 2
CAN_BTR_SJW 24:25 Resynchronization Jump Width
CAN_BTR_LBKM 30 Loop Back Mode (Debug)
CAN_BTR_SILM 31 Silent Mode
FMR 0x200 32
CAN_FMR_FINIT 0 Filter Init Mode
FM1R 0x204 32
CAN_FM1R_FBM 0:13 Filter Mode
CAN_FM1R_FBM0 0 Filter Init Mode bit 0
CAN_FM1R_FBM1 1 Filter Init Mode bit 1
CAN_FM1R_FBM2 2 Filter Init Mode bit 2
CAN_FM1R_FBM3 3 Filter Init Mode bit 3
CAN_FM1R_FBM4 4 Filter Init Mode bit 4
CAN_FM1R_FBM5 5 Filter Init Mode bit 5
CAN_FM1R_FBM6 6 Filter Init Mode bit 6
CAN_FM1R_FBM7 7 Filter Init Mode bit 7
CAN_FM1R_FBM8 8 Filter Init Mode bit 8
CAN_FM1R_FBM9 9 Filter Init Mode bit 9
CAN_FM1R_FBM10 10 Filter Init Mode bit 10
CAN_FM1R_FBM11 11 Filter Init Mode bit 11
CAN_FM1R_FBM12 12 Filter Init Mode bit 12
CAN_FM1R_FBM13 13 Filter Init Mode bit 13
FS1R 0x20C 32
CAN_FS1R_FSC 0:13 Filter Scale Configuration
CAN_FS1R_FSC0 0 Filter Scale Configuration bit 0
CAN_FS1R_FSC1 1 Filter Scale Configuration bit 1
CAN_FS1R_FSC2 2 Filter Scale Configuration bit 2
CAN_FS1R_FSC3 3 Filter Scale Configuration bit 3
CAN_FS1R_FSC4 4 Filter Scale Configuration bit 4
CAN_FS1R_FSC5 5 Filter Scale Configuration bit 5
CAN_FS1R_FSC6 6 Filter Scale Configuration bit 6
CAN_FS1R_FSC7 7 Filter Scale Configuration bit 7
CAN_FS1R_FSC8 8 Filter Scale Configuration bit 8
CAN_FS1R_FSC9 9 Filter Scale Configuration bit 9
CAN_FS1R_FSC10 10 Filter Scale Configuration bit 10
CAN_FS1R_FSC11 11 Filter Scale Configuration bit 11
CAN_FS1R_FSC12 12 Filter Scale Configuration bit 12
CAN_FS1R_FSC13 13 Filter Scale Configuration bit 13
FFA1R 0x214 32
CAN_FFA1R_FFA 0:13 Filter FIFO Assignment
CAN_FFA1R_FFA0 0 Filter FIFO Assignment for Filter 0
CAN_FFA1R_FFA1 1 Filter FIFO Assignment for Filter 1
CAN_FFA1R_FFA2 2 Filter FIFO Assignment for Filter 2
CAN_FFA1R_FFA3 3 Filter FIFO Assignment for Filter 3
CAN_FFA1R_FFA4 4 Filter FIFO Assignment for Filter 4
CAN_FFA1R_FFA5 5 Filter FIFO Assignment for Filter 5
CAN_FFA1R_FFA6 6 Filter FIFO Assignment for Filter 6
CAN_FFA1R_FFA7 7 Filter FIFO Assignment for Filter 7
CAN_FFA1R_FFA8 8 Filter FIFO Assignment for Filter 8
CAN_FFA1R_FFA9 9 Filter FIFO Assignment for Filter 9
CAN_FFA1R_FFA10 10 Filter FIFO Assignment for Filter 10
CAN_FFA1R_FFA11 11 Filter FIFO Assignment for Filter 11
CAN_FFA1R_FFA12 12 Filter FIFO Assignment for Filter 12
CAN_FFA1R_FFA13 13 Filter FIFO Assignment for Filter 13
FA1R 0x21C 32
CAN_FA1R_FACT 0:13 Filter Active
CAN_FA1R_FACT0 0 Filter 0 Active
CAN_FA1R_FACT1 1 Filter 1 Active
CAN_FA1R_FACT2 2 Filter 2 Active
CAN_FA1R_FACT3 3 Filter 3 Active
CAN_FA1R_FACT4 4 Filter 4 Active
CAN_FA1R_FACT5 5 Filter 5 Active
CAN_FA1R_FACT6 6 Filter 6 Active
CAN_FA1R_FACT7 7 Filter 7 Active
CAN_FA1R_FACT8 8 Filter 8 Active
CAN_FA1R_FACT9 9 Filter 9 Active
CAN_FA1R_FACT10 10 Filter 10 Active
CAN_FA1R_FACT11 11 Filter 11 Active
CAN_FA1R_FACT12 12 Filter 12 Active
CAN_FA1R_FACT13 13 Filter 13 Active

USB — USB (registers by address) (section 20)

Register Bits Position Purpose
ADDR0 USB_ADDR0_TX_ADDR0_TX 1:15 Transmission Buffer Address 0
ADDR0 USB_ADDR0_RX_ADDR0_RX 1:15 Reception Buffer Address 0
ADDR1 USB_ADDR1_TX_ADDR1_TX 1:15 Transmission Buffer Address 1
ADDR1 USB_ADDR1_RX_ADDR1_RX 1:15 Reception Buffer Address 1
ADDR2 USB_ADDR2_TX_ADDR2_TX 1:15 Transmission Buffer Address 2
ADDR2 USB_ADDR2_RX_ADDR2_RX 1:15 Reception Buffer Address 2
ADDR3 USB_ADDR3_TX_ADDR3_TX 1:15 Transmission Buffer Address 3
ADDR3 USB_ADDR3_RX_ADDR3_RX 1:15 Reception Buffer Address 3
ADDR4 USB_ADDR4_TX_ADDR4_TX 1:15 Transmission Buffer Address 4
ADDR4 USB_ADDR4_RX_ADDR4_RX 1:15 Reception Buffer Address 4
ADDR5 USB_ADDR5_TX_ADDR5_TX 1:15 Transmission Buffer Address 5
ADDR5 USB_ADDR5_RX_ADDR5_RX 1:15 Reception Buffer Address 5
ADDR6 USB_ADDR6_TX_ADDR6_TX 1:15 Transmission Buffer Address 6
ADDR6 USB_ADDR6_RX_ADDR6_RX 1:15 Reception Buffer Address 6
ADDR7 USB_ADDR7_TX_ADDR7_TX 1:15 Transmission Buffer Address 7
ADDR7 USB_ADDR7_RX_ADDR7_RX 1:15 Reception Buffer Address 7
BTABLE USB_BTABLE_BTABLE 3:15 Buffer Table
CNTR USB_CNTR_FRES 0 Force USB Reset
CNTR USB_CNTR_PDWN 1 Power down
CNTR USB_CNTR_LP_MODE 2 Low-power mode
CNTR USB_CNTR_FSUSP 3 Force suspend
CNTR USB_CNTR_RESUME 4 Resume request
CNTR USB_CNTR_ESOFM 8 Expected Start Of Frame Interrupt Mask
CNTR USB_CNTR_SOFM 9 Start Of Frame Interrupt Mask
CNTR USB_CNTR_RESETM 10 RESET Interrupt Mask
CNTR USB_CNTR_SUSPM 11 Suspend mode Interrupt Mask
CNTR USB_CNTR_WKUPM 12 Wakeup Interrupt Mask
CNTR USB_CNTR_ERRM 13 Error Interrupt Mask
CNTR USB_CNTR_PMAOVRM 14 Packet Memory Area Over / Underrun Interrupt Mask
CNTR USB_CNTR_CTRM 15 Correct Transfer Interrupt Mask
COUNT0 USB_COUNT0_TX_COUNT0_TX 0:9 Transmission Byte Count 0
COUNT0 USB_COUNT0_TX_0_COUNT0_TX_0 0:9 Transmission Byte Count 0 (low)
COUNT0 USB_COUNT0_TX_1_COUNT0_TX_1 16:25 Transmission Byte Count 0 (high)
COUNT0 USB_COUNT0_RX_COUNT0_RX 0:9 Reception Byte Count
COUNT0 USB_COUNT0_RX_NUM_BLOCK 10:14 NUM_BLOCK[4:0] bits (Number of blocks)
COUNT0 USB_COUNT0_RX_NUM_BLOCK_0 10 Bit 0
COUNT0 USB_COUNT0_RX_NUM_BLOCK_1 11 Bit 1
COUNT0 USB_COUNT0_RX_NUM_BLOCK_2 12 Bit 2
COUNT0 USB_COUNT0_RX_NUM_BLOCK_3 13 Bit 3
COUNT0 USB_COUNT0_RX_NUM_BLOCK_4 14 Bit 4
COUNT0 USB_COUNT0_RX_BLSIZE 15 BLock SIZE
COUNT0 USB_COUNT0_RX_0_COUNT0_RX_0 0:9 Reception Byte Count (low)
COUNT0 USB_COUNT0_RX_0_NUM_BLOCK_0 10:14 NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
COUNT0 USB_COUNT0_RX_0_NUM_BLOCK_0_0 10 Bit 0
COUNT0 USB_COUNT0_RX_0_NUM_BLOCK_0_1 11 Bit 1
COUNT0 USB_COUNT0_RX_0_NUM_BLOCK_0_2 12 Bit 2
COUNT0 USB_COUNT0_RX_0_NUM_BLOCK_0_3 13 Bit 3
COUNT0 USB_COUNT0_RX_0_NUM_BLOCK_0_4 14 Bit 4
COUNT0 USB_COUNT0_RX_0_BLSIZE_0 15 BLock SIZE (low)
COUNT0 USB_COUNT0_RX_1_COUNT0_RX_1 16:25 Reception Byte Count (high)
COUNT0 USB_COUNT0_RX_1_NUM_BLOCK_1 26:30 NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
COUNT0 USB_COUNT0_RX_1_NUM_BLOCK_1_0 26 Bit 1
COUNT0 USB_COUNT0_RX_1_NUM_BLOCK_1_1 27 Bit 1
COUNT0 USB_COUNT0_RX_1_NUM_BLOCK_1_2 28 Bit 2
COUNT0 USB_COUNT0_RX_1_NUM_BLOCK_1_3 29 Bit 3
COUNT0 USB_COUNT0_RX_1_NUM_BLOCK_1_4 30 Bit 4
COUNT0 USB_COUNT0_RX_1_BLSIZE_1 31 BLock SIZE (high)
COUNT1 USB_COUNT1_TX_COUNT1_TX 0:9 Transmission Byte Count 1
COUNT1 USB_COUNT1_TX_0_COUNT1_TX_0 0:9 Transmission Byte Count 1 (low)
COUNT1 USB_COUNT1_TX_1_COUNT1_TX_1 16:25 Transmission Byte Count 1 (high)
COUNT1 USB_COUNT1_RX_COUNT1_RX 0:9 Reception Byte Count
COUNT1 USB_COUNT1_RX_NUM_BLOCK 10:14 NUM_BLOCK[4:0] bits (Number of blocks)
COUNT1 USB_COUNT1_RX_NUM_BLOCK_0 10 Bit 0
COUNT1 USB_COUNT1_RX_NUM_BLOCK_1 11 Bit 1
COUNT1 USB_COUNT1_RX_NUM_BLOCK_2 12 Bit 2
COUNT1 USB_COUNT1_RX_NUM_BLOCK_3 13 Bit 3
COUNT1 USB_COUNT1_RX_NUM_BLOCK_4 14 Bit 4
COUNT1 USB_COUNT1_RX_BLSIZE 15 BLock SIZE
COUNT1 USB_COUNT1_RX_0_COUNT1_RX_0 0:9 Reception Byte Count (low)
COUNT1 USB_COUNT1_RX_0_NUM_BLOCK_0 10:14 NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
COUNT1 USB_COUNT1_RX_0_NUM_BLOCK_0_0 10 Bit 0
COUNT1 USB_COUNT1_RX_0_NUM_BLOCK_0_1 11 Bit 1
COUNT1 USB_COUNT1_RX_0_NUM_BLOCK_0_2 12 Bit 2
COUNT1 USB_COUNT1_RX_0_NUM_BLOCK_0_3 13 Bit 3
COUNT1 USB_COUNT1_RX_0_NUM_BLOCK_0_4 14 Bit 4
COUNT1 USB_COUNT1_RX_0_BLSIZE_0 15 BLock SIZE (low)
COUNT1 USB_COUNT1_RX_1_COUNT1_RX_1 16:25 Reception Byte Count (high)
COUNT1 USB_COUNT1_RX_1_NUM_BLOCK_1 26:30 NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
COUNT1 USB_COUNT1_RX_1_NUM_BLOCK_1_0 26 Bit 0
COUNT1 USB_COUNT1_RX_1_NUM_BLOCK_1_1 27 Bit 1
COUNT1 USB_COUNT1_RX_1_NUM_BLOCK_1_2 28 Bit 2
COUNT1 USB_COUNT1_RX_1_NUM_BLOCK_1_3 29 Bit 3
COUNT1 USB_COUNT1_RX_1_NUM_BLOCK_1_4 30 Bit 4
COUNT1 USB_COUNT1_RX_1_BLSIZE_1 31 BLock SIZE (high)
COUNT2 USB_COUNT2_TX_COUNT2_TX 0:9 Transmission Byte Count 2
COUNT2 USB_COUNT2_TX_0_COUNT2_TX_0 0:9 Transmission Byte Count 2 (low)
COUNT2 USB_COUNT2_TX_1_COUNT2_TX_1 16:25 Transmission Byte Count 2 (high)
COUNT2 USB_COUNT2_RX_COUNT2_RX 0:9 Reception Byte Count
COUNT2 USB_COUNT2_RX_NUM_BLOCK 10:14 NUM_BLOCK[4:0] bits (Number of blocks)
COUNT2 USB_COUNT2_RX_NUM_BLOCK_0 10 Bit 0
COUNT2 USB_COUNT2_RX_NUM_BLOCK_1 11 Bit 1
COUNT2 USB_COUNT2_RX_NUM_BLOCK_2 12 Bit 2
COUNT2 USB_COUNT2_RX_NUM_BLOCK_3 13 Bit 3
COUNT2 USB_COUNT2_RX_NUM_BLOCK_4 14 Bit 4
COUNT2 USB_COUNT2_RX_BLSIZE 15 BLock SIZE
COUNT2 USB_COUNT2_RX_0_COUNT2_RX_0 0:9 Reception Byte Count (low)
COUNT2 USB_COUNT2_RX_0_NUM_BLOCK_0 10:14 NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
COUNT2 USB_COUNT2_RX_0_NUM_BLOCK_0_0 10 Bit 0
COUNT2 USB_COUNT2_RX_0_NUM_BLOCK_0_1 11 Bit 1
COUNT2 USB_COUNT2_RX_0_NUM_BLOCK_0_2 12 Bit 2
COUNT2 USB_COUNT2_RX_0_NUM_BLOCK_0_3 13 Bit 3
COUNT2 USB_COUNT2_RX_0_NUM_BLOCK_0_4 14 Bit 4
COUNT2 USB_COUNT2_RX_0_BLSIZE_0 15 BLock SIZE (low)
COUNT2 USB_COUNT2_RX_1_COUNT2_RX_1 16:25 Reception Byte Count (high)
COUNT2 USB_COUNT2_RX_1_NUM_BLOCK_1 26:30 NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
COUNT2 USB_COUNT2_RX_1_NUM_BLOCK_1_0 26 Bit 0
COUNT2 USB_COUNT2_RX_1_NUM_BLOCK_1_1 27 Bit 1
COUNT2 USB_COUNT2_RX_1_NUM_BLOCK_1_2 28 Bit 2
COUNT2 USB_COUNT2_RX_1_NUM_BLOCK_1_3 29 Bit 3
COUNT2 USB_COUNT2_RX_1_NUM_BLOCK_1_4 30 Bit 4
COUNT2 USB_COUNT2_RX_1_BLSIZE_1 31 BLock SIZE (high)
COUNT3 USB_COUNT3_TX_COUNT3_TX 0:9 Transmission Byte Count 3
COUNT3 USB_COUNT3_TX_0_COUNT3_TX_0 0:9 Transmission Byte Count 3 (low)
COUNT3 USB_COUNT3_TX_1_COUNT3_TX_1 16:25 Transmission Byte Count 3 (high)
COUNT3 USB_COUNT3_RX_COUNT3_RX 0:9 Reception Byte Count
COUNT3 USB_COUNT3_RX_NUM_BLOCK 10:14 NUM_BLOCK[4:0] bits (Number of blocks)
COUNT3 USB_COUNT3_RX_NUM_BLOCK_0 10 Bit 0
COUNT3 USB_COUNT3_RX_NUM_BLOCK_1 11 Bit 1
COUNT3 USB_COUNT3_RX_NUM_BLOCK_2 12 Bit 2
COUNT3 USB_COUNT3_RX_NUM_BLOCK_3 13 Bit 3
COUNT3 USB_COUNT3_RX_NUM_BLOCK_4 14 Bit 4
COUNT3 USB_COUNT3_RX_BLSIZE 15 BLock SIZE
COUNT3 USB_COUNT3_RX_0_COUNT3_RX_0 0:9 Reception Byte Count (low)
COUNT3 USB_COUNT3_RX_0_NUM_BLOCK_0 10:14 NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
COUNT3 USB_COUNT3_RX_0_NUM_BLOCK_0_0 10 Bit 0
COUNT3 USB_COUNT3_RX_0_NUM_BLOCK_0_1 11 Bit 1
COUNT3 USB_COUNT3_RX_0_NUM_BLOCK_0_2 12 Bit 2
COUNT3 USB_COUNT3_RX_0_NUM_BLOCK_0_3 13 Bit 3
COUNT3 USB_COUNT3_RX_0_NUM_BLOCK_0_4 14 Bit 4
COUNT3 USB_COUNT3_RX_0_BLSIZE_0 15 BLock SIZE (low)
COUNT3 USB_COUNT3_RX_1_COUNT3_RX_1 16:25 Reception Byte Count (high)
COUNT3 USB_COUNT3_RX_1_NUM_BLOCK_1 26:30 NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
COUNT3 USB_COUNT3_RX_1_NUM_BLOCK_1_0 26 Bit 0
COUNT3 USB_COUNT3_RX_1_NUM_BLOCK_1_1 27 Bit 1
COUNT3 USB_COUNT3_RX_1_NUM_BLOCK_1_2 28 Bit 2
COUNT3 USB_COUNT3_RX_1_NUM_BLOCK_1_3 29 Bit 3
COUNT3 USB_COUNT3_RX_1_NUM_BLOCK_1_4 30 Bit 4
COUNT3 USB_COUNT3_RX_1_BLSIZE_1 31 BLock SIZE (high)
COUNT4 USB_COUNT4_TX_COUNT4_TX 0:9 Transmission Byte Count 4
COUNT4 USB_COUNT4_TX_0_COUNT4_TX_0 0:9 Transmission Byte Count 4 (low)
COUNT4 USB_COUNT4_TX_1_COUNT4_TX_1 16:25 Transmission Byte Count 4 (high)
COUNT4 USB_COUNT4_RX_COUNT4_RX 0:9 Reception Byte Count
COUNT4 USB_COUNT4_RX_NUM_BLOCK 10:14 NUM_BLOCK[4:0] bits (Number of blocks)
COUNT4 USB_COUNT4_RX_NUM_BLOCK_0 10 Bit 0
COUNT4 USB_COUNT4_RX_NUM_BLOCK_1 11 Bit 1
COUNT4 USB_COUNT4_RX_NUM_BLOCK_2 12 Bit 2
COUNT4 USB_COUNT4_RX_NUM_BLOCK_3 13 Bit 3
COUNT4 USB_COUNT4_RX_NUM_BLOCK_4 14 Bit 4
COUNT4 USB_COUNT4_RX_BLSIZE 15 BLock SIZE
COUNT4 USB_COUNT4_RX_0_COUNT4_RX_0 0:9 Reception Byte Count (low)
COUNT4 USB_COUNT4_RX_0_NUM_BLOCK_0 10:14 NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
COUNT4 USB_COUNT4_RX_0_NUM_BLOCK_0_0 10 Bit 0
COUNT4 USB_COUNT4_RX_0_NUM_BLOCK_0_1 11 Bit 1
COUNT4 USB_COUNT4_RX_0_NUM_BLOCK_0_2 12 Bit 2
COUNT4 USB_COUNT4_RX_0_NUM_BLOCK_0_3 13 Bit 3
COUNT4 USB_COUNT4_RX_0_NUM_BLOCK_0_4 14 Bit 4
COUNT4 USB_COUNT4_RX_0_BLSIZE_0 15 BLock SIZE (low)
COUNT4 USB_COUNT4_RX_1_COUNT4_RX_1 16:25 Reception Byte Count (high)
COUNT4 USB_COUNT4_RX_1_NUM_BLOCK_1 26:30 NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
COUNT4 USB_COUNT4_RX_1_NUM_BLOCK_1_0 26 Bit 0
COUNT4 USB_COUNT4_RX_1_NUM_BLOCK_1_1 27 Bit 1
COUNT4 USB_COUNT4_RX_1_NUM_BLOCK_1_2 28 Bit 2
COUNT4 USB_COUNT4_RX_1_NUM_BLOCK_1_3 29 Bit 3
COUNT4 USB_COUNT4_RX_1_NUM_BLOCK_1_4 30 Bit 4
COUNT4 USB_COUNT4_RX_1_BLSIZE_1 31 BLock SIZE (high)
COUNT5 USB_COUNT5_TX_COUNT5_TX 0:9 Transmission Byte Count 5
COUNT5 USB_COUNT5_TX_0_COUNT5_TX_0 0:9 Transmission Byte Count 5 (low)
COUNT5 USB_COUNT5_TX_1_COUNT5_TX_1 16:25 Transmission Byte Count 5 (high)
COUNT5 USB_COUNT5_RX_COUNT5_RX 0:9 Reception Byte Count
COUNT5 USB_COUNT5_RX_NUM_BLOCK 10:14 NUM_BLOCK[4:0] bits (Number of blocks)
COUNT5 USB_COUNT5_RX_NUM_BLOCK_0 10 Bit 0
COUNT5 USB_COUNT5_RX_NUM_BLOCK_1 11 Bit 1
COUNT5 USB_COUNT5_RX_NUM_BLOCK_2 12 Bit 2
COUNT5 USB_COUNT5_RX_NUM_BLOCK_3 13 Bit 3
COUNT5 USB_COUNT5_RX_NUM_BLOCK_4 14 Bit 4
COUNT5 USB_COUNT5_RX_BLSIZE 15 BLock SIZE
COUNT5 USB_COUNT5_RX_0_COUNT5_RX_0 0:9 Reception Byte Count (low)
COUNT5 USB_COUNT5_RX_0_NUM_BLOCK_0 10:14 NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
COUNT5 USB_COUNT5_RX_0_NUM_BLOCK_0_0 10 Bit 0
COUNT5 USB_COUNT5_RX_0_NUM_BLOCK_0_1 11 Bit 1
COUNT5 USB_COUNT5_RX_0_NUM_BLOCK_0_2 12 Bit 2
COUNT5 USB_COUNT5_RX_0_NUM_BLOCK_0_3 13 Bit 3
COUNT5 USB_COUNT5_RX_0_NUM_BLOCK_0_4 14 Bit 4
COUNT5 USB_COUNT5_RX_0_BLSIZE_0 15 BLock SIZE (low)
COUNT5 USB_COUNT5_RX_1_COUNT5_RX_1 16:25 Reception Byte Count (high)
COUNT5 USB_COUNT5_RX_1_NUM_BLOCK_1 26:30 NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
COUNT5 USB_COUNT5_RX_1_NUM_BLOCK_1_0 26 Bit 0
COUNT5 USB_COUNT5_RX_1_NUM_BLOCK_1_1 27 Bit 1
COUNT5 USB_COUNT5_RX_1_NUM_BLOCK_1_2 28 Bit 2
COUNT5 USB_COUNT5_RX_1_NUM_BLOCK_1_3 29 Bit 3
COUNT5 USB_COUNT5_RX_1_NUM_BLOCK_1_4 30 Bit 4
COUNT5 USB_COUNT5_RX_1_BLSIZE_1 31 BLock SIZE (high)
COUNT6 USB_COUNT6_TX_COUNT6_TX 0:9 Transmission Byte Count 6
COUNT6 USB_COUNT6_TX_0_COUNT6_TX_0 0:9 Transmission Byte Count 6 (low)
COUNT6 USB_COUNT6_TX_1_COUNT6_TX_1 16:25 Transmission Byte Count 6 (high)
COUNT6 USB_COUNT6_RX_COUNT6_RX 0:9 Reception Byte Count
COUNT6 USB_COUNT6_RX_NUM_BLOCK 10:14 NUM_BLOCK[4:0] bits (Number of blocks)
COUNT6 USB_COUNT6_RX_NUM_BLOCK_0 10 Bit 0
COUNT6 USB_COUNT6_RX_NUM_BLOCK_1 11 Bit 1
COUNT6 USB_COUNT6_RX_NUM_BLOCK_2 12 Bit 2
COUNT6 USB_COUNT6_RX_NUM_BLOCK_3 13 Bit 3
COUNT6 USB_COUNT6_RX_NUM_BLOCK_4 14 Bit 4
COUNT6 USB_COUNT6_RX_BLSIZE 15 BLock SIZE
COUNT6 USB_COUNT6_RX_0_COUNT6_RX_0 0:9 Reception Byte Count (low)
COUNT6 USB_COUNT6_RX_0_NUM_BLOCK_0 10:14 NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
COUNT6 USB_COUNT6_RX_0_NUM_BLOCK_0_0 10 Bit 0
COUNT6 USB_COUNT6_RX_0_NUM_BLOCK_0_1 11 Bit 1
COUNT6 USB_COUNT6_RX_0_NUM_BLOCK_0_2 12 Bit 2
COUNT6 USB_COUNT6_RX_0_NUM_BLOCK_0_3 13 Bit 3
COUNT6 USB_COUNT6_RX_0_NUM_BLOCK_0_4 14 Bit 4
COUNT6 USB_COUNT6_RX_0_BLSIZE_0 15 BLock SIZE (low)
COUNT6 USB_COUNT6_RX_1_COUNT6_RX_1 16:25 Reception Byte Count (high)
COUNT6 USB_COUNT6_RX_1_NUM_BLOCK_1 26:30 NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
COUNT6 USB_COUNT6_RX_1_NUM_BLOCK_1_0 26 Bit 0
COUNT6 USB_COUNT6_RX_1_NUM_BLOCK_1_1 27 Bit 1
COUNT6 USB_COUNT6_RX_1_NUM_BLOCK_1_2 28 Bit 2
COUNT6 USB_COUNT6_RX_1_NUM_BLOCK_1_3 29 Bit 3
COUNT6 USB_COUNT6_RX_1_NUM_BLOCK_1_4 30 Bit 4
COUNT6 USB_COUNT6_RX_1_BLSIZE_1 31 BLock SIZE (high)
COUNT7 USB_COUNT7_TX_COUNT7_TX 0:9 Transmission Byte Count 7
COUNT7 USB_COUNT7_TX_0_COUNT7_TX_0 0:9 Transmission Byte Count 7 (low)
COUNT7 USB_COUNT7_TX_1_COUNT7_TX_1 16:25 Transmission Byte Count 7 (high)
COUNT7 USB_COUNT7_RX_COUNT7_RX 0:9 Reception Byte Count
COUNT7 USB_COUNT7_RX_NUM_BLOCK 10:14 NUM_BLOCK[4:0] bits (Number of blocks)
COUNT7 USB_COUNT7_RX_NUM_BLOCK_0 10 Bit 0
COUNT7 USB_COUNT7_RX_NUM_BLOCK_1 11 Bit 1
COUNT7 USB_COUNT7_RX_NUM_BLOCK_2 12 Bit 2
COUNT7 USB_COUNT7_RX_NUM_BLOCK_3 13 Bit 3
COUNT7 USB_COUNT7_RX_NUM_BLOCK_4 14 Bit 4
COUNT7 USB_COUNT7_RX_BLSIZE 15 BLock SIZE
COUNT7 USB_COUNT7_RX_0_COUNT7_RX_0 0:9 Reception Byte Count (low)
COUNT7 USB_COUNT7_RX_0_NUM_BLOCK_0 10:14 NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
COUNT7 USB_COUNT7_RX_0_NUM_BLOCK_0_0 10 Bit 0
COUNT7 USB_COUNT7_RX_0_NUM_BLOCK_0_1 11 Bit 1
COUNT7 USB_COUNT7_RX_0_NUM_BLOCK_0_2 12 Bit 2
COUNT7 USB_COUNT7_RX_0_NUM_BLOCK_0_3 13 Bit 3
COUNT7 USB_COUNT7_RX_0_NUM_BLOCK_0_4 14 Bit 4
COUNT7 USB_COUNT7_RX_0_BLSIZE_0 15 BLock SIZE (low)
COUNT7 USB_COUNT7_RX_1_COUNT7_RX_1 16:25 Reception Byte Count (high)
COUNT7 USB_COUNT7_RX_1_NUM_BLOCK_1 26:30 NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
COUNT7 USB_COUNT7_RX_1_NUM_BLOCK_1_0 26 Bit 0
COUNT7 USB_COUNT7_RX_1_NUM_BLOCK_1_1 27 Bit 1
COUNT7 USB_COUNT7_RX_1_NUM_BLOCK_1_2 28 Bit 2
COUNT7 USB_COUNT7_RX_1_NUM_BLOCK_1_3 29 Bit 3
COUNT7 USB_COUNT7_RX_1_NUM_BLOCK_1_4 30 Bit 4
COUNT7 USB_COUNT7_RX_1_BLSIZE_1 31 BLock SIZE (high)
DADDR USB_DADDR_ADD 0:6 ADD[6:0] bits (Device Address)
DADDR USB_DADDR_ADD0 0 Bit 0
DADDR USB_DADDR_ADD1 1 Bit 1
DADDR USB_DADDR_ADD2 2 Bit 2
DADDR USB_DADDR_ADD3 3 Bit 3
DADDR USB_DADDR_ADD4 4 Bit 4
DADDR USB_DADDR_ADD5 5 Bit 5
DADDR USB_DADDR_ADD6 6 Bit 6
DADDR USB_DADDR_EF 7 Enable Function
EP0R USB_EP0R_EA 0:3 Endpoint Address
EP0R USB_EP0R_STAT_TX 4:5 STAT_TX[1:0] bits (Status bits, for transmission transfers)
EP0R USB_EP0R_STAT_TX_0 4 Bit 0
EP0R USB_EP0R_STAT_TX_1 5 Bit 1
EP0R USB_EP0R_DTOG_TX 6 Data Toggle, for transmission transfers
EP0R USB_EP0R_CTR_TX 7 Correct Transfer for transmission
EP0R USB_EP0R_EP_KIND 8 Endpoint Kind
EP0R USB_EP0R_EP_TYPE 9:10 EP_TYPE[1:0] bits (Endpoint type)
EP0R USB_EP0R_EP_TYPE_0 9 Bit 0
EP0R USB_EP0R_EP_TYPE_1 10 Bit 1
EP0R USB_EP0R_SETUP 11 Setup transaction completed
EP0R USB_EP0R_STAT_RX 12:13 STAT_RX[1:0] bits (Status bits, for reception transfers)
EP0R USB_EP0R_STAT_RX_0 12 Bit 0
EP0R USB_EP0R_STAT_RX_1 13 Bit 1
EP0R USB_EP0R_DTOG_RX 14 Data Toggle, for reception transfers
EP0R USB_EP0R_CTR_RX 15 Correct Transfer for reception
EP1R USB_EP1R_EA 0:3 Endpoint Address
EP1R USB_EP1R_STAT_TX 4:5 STAT_TX[1:0] bits (Status bits, for transmission transfers)
EP1R USB_EP1R_STAT_TX_0 4 Bit 0
EP1R USB_EP1R_STAT_TX_1 5 Bit 1
EP1R USB_EP1R_DTOG_TX 6 Data Toggle, for transmission transfers
EP1R USB_EP1R_CTR_TX 7 Correct Transfer for transmission
EP1R USB_EP1R_EP_KIND 8 Endpoint Kind
EP1R USB_EP1R_EP_TYPE 9:10 EP_TYPE[1:0] bits (Endpoint type)
EP1R USB_EP1R_EP_TYPE_0 9 Bit 0
EP1R USB_EP1R_EP_TYPE_1 10 Bit 1
EP1R USB_EP1R_SETUP 11 Setup transaction completed
EP1R USB_EP1R_STAT_RX 12:13 STAT_RX[1:0] bits (Status bits, for reception transfers)
EP1R USB_EP1R_STAT_RX_0 12 Bit 0
EP1R USB_EP1R_STAT_RX_1 13 Bit 1
EP1R USB_EP1R_DTOG_RX 14 Data Toggle, for reception transfers
EP1R USB_EP1R_CTR_RX 15 Correct Transfer for reception
EP2R USB_EP2R_EA 0:3 Endpoint Address
EP2R USB_EP2R_STAT_TX 4:5 STAT_TX[1:0] bits (Status bits, for transmission transfers)
EP2R USB_EP2R_STAT_TX_0 4 Bit 0
EP2R USB_EP2R_STAT_TX_1 5 Bit 1
EP2R USB_EP2R_DTOG_TX 6 Data Toggle, for transmission transfers
EP2R USB_EP2R_CTR_TX 7 Correct Transfer for transmission
EP2R USB_EP2R_EP_KIND 8 Endpoint Kind
EP2R USB_EP2R_EP_TYPE 9:10 EP_TYPE[1:0] bits (Endpoint type)
EP2R USB_EP2R_EP_TYPE_0 9 Bit 0
EP2R USB_EP2R_EP_TYPE_1 10 Bit 1
EP2R USB_EP2R_SETUP 11 Setup transaction completed
EP2R USB_EP2R_STAT_RX 12:13 STAT_RX[1:0] bits (Status bits, for reception transfers)
EP2R USB_EP2R_STAT_RX_0 12 Bit 0
EP2R USB_EP2R_STAT_RX_1 13 Bit 1
EP2R USB_EP2R_DTOG_RX 14 Data Toggle, for reception transfers
EP2R USB_EP2R_CTR_RX 15 Correct Transfer for reception
EP3R USB_EP3R_EA 0:3 Endpoint Address
EP3R USB_EP3R_STAT_TX 4:5 STAT_TX[1:0] bits (Status bits, for transmission transfers)
EP3R USB_EP3R_STAT_TX_0 4 Bit 0
EP3R USB_EP3R_STAT_TX_1 5 Bit 1
EP3R USB_EP3R_DTOG_TX 6 Data Toggle, for transmission transfers
EP3R USB_EP3R_CTR_TX 7 Correct Transfer for transmission
EP3R USB_EP3R_EP_KIND 8 Endpoint Kind
EP3R USB_EP3R_EP_TYPE 9:10 EP_TYPE[1:0] bits (Endpoint type)
EP3R USB_EP3R_EP_TYPE_0 9 Bit 0
EP3R USB_EP3R_EP_TYPE_1 10 Bit 1
EP3R USB_EP3R_SETUP 11 Setup transaction completed
EP3R USB_EP3R_STAT_RX 12:13 STAT_RX[1:0] bits (Status bits, for reception transfers)
EP3R USB_EP3R_STAT_RX_0 12 Bit 0
EP3R USB_EP3R_STAT_RX_1 13 Bit 1
EP3R USB_EP3R_DTOG_RX 14 Data Toggle, for reception transfers
EP3R USB_EP3R_CTR_RX 15 Correct Transfer for reception
EP4R USB_EP4R_EA 0:3 Endpoint Address
EP4R USB_EP4R_STAT_TX 4:5 STAT_TX[1:0] bits (Status bits, for transmission transfers)
EP4R USB_EP4R_STAT_TX_0 4 Bit 0
EP4R USB_EP4R_STAT_TX_1 5 Bit 1
EP4R USB_EP4R_DTOG_TX 6 Data Toggle, for transmission transfers
EP4R USB_EP4R_CTR_TX 7 Correct Transfer for transmission
EP4R USB_EP4R_EP_KIND 8 Endpoint Kind
EP4R USB_EP4R_EP_TYPE 9:10 EP_TYPE[1:0] bits (Endpoint type)
EP4R USB_EP4R_EP_TYPE_0 9 Bit 0
EP4R USB_EP4R_EP_TYPE_1 10 Bit 1
EP4R USB_EP4R_SETUP 11 Setup transaction completed
EP4R USB_EP4R_STAT_RX 12:13 STAT_RX[1:0] bits (Status bits, for reception transfers)
EP4R USB_EP4R_STAT_RX_0 12 Bit 0
EP4R USB_EP4R_STAT_RX_1 13 Bit 1
EP4R USB_EP4R_DTOG_RX 14 Data Toggle, for reception transfers
EP4R USB_EP4R_CTR_RX 15 Correct Transfer for reception
EP5R USB_EP5R_EA 0:3 Endpoint Address
EP5R USB_EP5R_STAT_TX 4:5 STAT_TX[1:0] bits (Status bits, for transmission transfers)
EP5R USB_EP5R_STAT_TX_0 4 Bit 0
EP5R USB_EP5R_STAT_TX_1 5 Bit 1
EP5R USB_EP5R_DTOG_TX 6 Data Toggle, for transmission transfers
EP5R USB_EP5R_CTR_TX 7 Correct Transfer for transmission
EP5R USB_EP5R_EP_KIND 8 Endpoint Kind
EP5R USB_EP5R_EP_TYPE 9:10 EP_TYPE[1:0] bits (Endpoint type)
EP5R USB_EP5R_EP_TYPE_0 9 Bit 0
EP5R USB_EP5R_EP_TYPE_1 10 Bit 1
EP5R USB_EP5R_SETUP 11 Setup transaction completed
EP5R USB_EP5R_STAT_RX 12:13 STAT_RX[1:0] bits (Status bits, for reception transfers)
EP5R USB_EP5R_STAT_RX_0 12 Bit 0
EP5R USB_EP5R_STAT_RX_1 13 Bit 1
EP5R USB_EP5R_DTOG_RX 14 Data Toggle, for reception transfers
EP5R USB_EP5R_CTR_RX 15 Correct Transfer for reception
EP6R USB_EP6R_EA 0:3 Endpoint Address
EP6R USB_EP6R_STAT_TX 4:5 STAT_TX[1:0] bits (Status bits, for transmission transfers)
EP6R USB_EP6R_STAT_TX_0 4 Bit 0
EP6R USB_EP6R_STAT_TX_1 5 Bit 1
EP6R USB_EP6R_DTOG_TX 6 Data Toggle, for transmission transfers
EP6R USB_EP6R_CTR_TX 7 Correct Transfer for transmission
EP6R USB_EP6R_EP_KIND 8 Endpoint Kind
EP6R USB_EP6R_EP_TYPE 9:10 EP_TYPE[1:0] bits (Endpoint type)
EP6R USB_EP6R_EP_TYPE_0 9 Bit 0
EP6R USB_EP6R_EP_TYPE_1 10 Bit 1
EP6R USB_EP6R_SETUP 11 Setup transaction completed
EP6R USB_EP6R_STAT_RX 12:13 STAT_RX[1:0] bits (Status bits, for reception transfers)
EP6R USB_EP6R_STAT_RX_0 12 Bit 0
EP6R USB_EP6R_STAT_RX_1 13 Bit 1
EP6R USB_EP6R_DTOG_RX 14 Data Toggle, for reception transfers
EP6R USB_EP6R_CTR_RX 15 Correct Transfer for reception
EP7R USB_EP7R_EA 0:3 Endpoint Address
EP7R USB_EP7R_STAT_TX 4:5 STAT_TX[1:0] bits (Status bits, for transmission transfers)
EP7R USB_EP7R_STAT_TX_0 4 Bit 0
EP7R USB_EP7R_STAT_TX_1 5 Bit 1
EP7R USB_EP7R_DTOG_TX 6 Data Toggle, for transmission transfers
EP7R USB_EP7R_CTR_TX 7 Correct Transfer for transmission
EP7R USB_EP7R_EP_KIND 8 Endpoint Kind
EP7R USB_EP7R_EP_TYPE 9:10 EP_TYPE[1:0] bits (Endpoint type)
EP7R USB_EP7R_EP_TYPE_0 9 Bit 0
EP7R USB_EP7R_EP_TYPE_1 10 Bit 1
EP7R USB_EP7R_SETUP 11 Setup transaction completed
EP7R USB_EP7R_STAT_RX 12:13 STAT_RX[1:0] bits (Status bits, for reception transfers)
EP7R USB_EP7R_STAT_RX_0 12 Bit 0
EP7R USB_EP7R_STAT_RX_1 13 Bit 1
EP7R USB_EP7R_DTOG_RX 14 Data Toggle, for reception transfers
EP7R USB_EP7R_CTR_RX 15 Correct Transfer for reception
FNR USB_FNR_FN 0:10 Frame Number
FNR USB_FNR_LSOF 11:12 Lost SOF
FNR USB_FNR_LCK 13 Locked
FNR USB_FNR_RXDM 14 Receive Data - Line Status
FNR USB_FNR_RXDP 15 Receive Data + Line Status
ISTR USB_ISTR_EP_ID 0:3 Endpoint Identifier
ISTR USB_ISTR_DIR 4 Direction of transaction
ISTR USB_ISTR_ESOF 8 Expected Start Of Frame
ISTR USB_ISTR_SOF 9 Start Of Frame
ISTR USB_ISTR_RESET 10 USB RESET request
ISTR USB_ISTR_SUSP 11 Suspend mode request
ISTR USB_ISTR_WKUP 12 Wake up
ISTR USB_ISTR_ERR 13 Error
ISTR USB_ISTR_PMAOVR 14 Packet Memory Area Over / Underrun
ISTR USB_ISTR_CTR 15 Correct Transfer
Open in the interactive handbook