STM32F407, STM32F401 · level reference · 69 min read

Appendix A2. STM32F4 register maps

Registers and bits of the main STM32F4 blocks, taken from the STM32F407 header the F4 layer of every section is written against. The F4 headers are newer and more generous: the purpose of each register and the description of each bit come from their own comments, offsets from the *_TypeDef structures. Each block is marked with whether the STM32F401 (Nucleo) has it: some F407 blocks — the DAC, CAN, Ethernet, the external memory controller — are missing there.

How to read: the offset is from the block's base address; 31:16 is a bit field from 16 to 31; a single number is a single bit. The number in brackets in a block heading is the section where the block is covered.

STM32F407 peripherals by bus: bus bases and the appendix block offsets, as in a debugger window

RCC — Clocks (section 6) · STM32F401: present

Register	Offset	Bits	Purpose
`CR`	`0x00`	32	RCC clock control register
`RCC_CR_HSION`		0
`RCC_CR_HSIRDY`		1
`RCC_CR_HSITRIM`		3:7
`RCC_CR_HSICAL`		8:15
`RCC_CR_HSEON`		16
`RCC_CR_HSERDY`		17
`RCC_CR_HSEBYP`		18
`RCC_CR_CSSON`		19
`RCC_CR_PLLON`		24
`RCC_CR_PLLRDY`		25
`RCC_CR_PLLI2SON`		26
`RCC_CR_PLLI2SRDY`		27
`PLLCFGR`	`0x04`	32	RCC PLL configuration register
`RCC_PLLCFGR_PLLM`		0:5
`RCC_PLLCFGR_PLLN`		6:14
`RCC_PLLCFGR_PLLP`		16:17
`RCC_PLLCFGR_PLLSRC`		22
`RCC_PLLCFGR_PLLSRC_HSE`		22
`RCC_PLLCFGR_PLLQ`		24:27
`CFGR`	`0x08`	32	RCC clock configuration register
`RCC_CFGR_SW`		0:1	SW[1:0] bits (System clock Switch)
`RCC_CFGR_SWS`		2:3	SWS[1:0] bits (System Clock Switch Status)
`RCC_CFGR_HPRE`		4:7	HPRE[3:0] bits (AHB prescaler)
`RCC_CFGR_PPRE1`		10:12	PRE1[2:0] bits (APB1 prescaler)
`RCC_CFGR_PPRE2`		13:15	PRE2[2:0] bits (APB2 prescaler)
`RCC_CFGR_RTCPRE`		16:20
`RCC_CFGR_MCO1`		21:22
`RCC_CFGR_I2SSRC`		23
`RCC_CFGR_MCO1PRE`		24:26
`RCC_CFGR_MCO2PRE`		27:29
`RCC_CFGR_MCO2`		30:31
`CIR`	`0x0C`	32	RCC clock interrupt register
`RCC_CIR_LSIRDYF`		0
`RCC_CIR_LSERDYF`		1
`RCC_CIR_HSIRDYF`		2
`RCC_CIR_HSERDYF`		3
`RCC_CIR_PLLRDYF`		4
`RCC_CIR_PLLI2SRDYF`		5
`RCC_CIR_CSSF`		7
`RCC_CIR_LSIRDYIE`		8
`RCC_CIR_LSERDYIE`		9
`RCC_CIR_HSIRDYIE`		10
`RCC_CIR_HSERDYIE`		11
`RCC_CIR_PLLRDYIE`		12
`RCC_CIR_PLLI2SRDYIE`		13
`RCC_CIR_LSIRDYC`		16
`RCC_CIR_LSERDYC`		17
`RCC_CIR_HSIRDYC`		18
`RCC_CIR_HSERDYC`		19
`RCC_CIR_PLLRDYC`		20
`RCC_CIR_PLLI2SRDYC`		21
`RCC_CIR_CSSC`		23
`AHB1RSTR`	`0x10`	32	RCC AHB1 peripheral reset register
`RCC_AHB1RSTR_GPIOARST`		0
`RCC_AHB1RSTR_GPIOBRST`		1
`RCC_AHB1RSTR_GPIOCRST`		2
`RCC_AHB1RSTR_GPIODRST`		3
`RCC_AHB1RSTR_GPIOERST`		4
`RCC_AHB1RSTR_GPIOFRST`		5
`RCC_AHB1RSTR_GPIOGRST`		6
`RCC_AHB1RSTR_GPIOHRST`		7
`RCC_AHB1RSTR_GPIOIRST`		8
`RCC_AHB1RSTR_CRCRST`		12
`RCC_AHB1RSTR_DMA1RST`		21
`RCC_AHB1RSTR_DMA2RST`		22
`RCC_AHB1RSTR_ETHMACRST`		25
`RCC_AHB1RSTR_OTGHRST`		29
`AHB2RSTR`	`0x14`	32	RCC AHB2 peripheral reset register
`RCC_AHB2RSTR_DCMIRST`		0
`RCC_AHB2RSTR_RNGRST`		6
`RCC_AHB2RSTR_OTGFSRST`		7
`AHB3RSTR`	`0x18`	32	RCC AHB3 peripheral reset register
`RCC_AHB3RSTR_FSMCRST`		0
`APB1RSTR`	`0x20`	32	RCC APB1 peripheral reset register
`RCC_APB1RSTR_TIM2RST`		0
`RCC_APB1RSTR_TIM3RST`		1
`RCC_APB1RSTR_TIM4RST`		2
`RCC_APB1RSTR_TIM5RST`		3
`RCC_APB1RSTR_TIM6RST`		4
`RCC_APB1RSTR_TIM7RST`		5
`RCC_APB1RSTR_TIM12RST`		6
`RCC_APB1RSTR_TIM13RST`		7
`RCC_APB1RSTR_TIM14RST`		8
`RCC_APB1RSTR_WWDGRST`		11
`RCC_APB1RSTR_SPI2RST`		14
`RCC_APB1RSTR_SPI3RST`		15
`RCC_APB1RSTR_USART2RST`		17
`RCC_APB1RSTR_USART3RST`		18
`RCC_APB1RSTR_UART4RST`		19
`RCC_APB1RSTR_UART5RST`		20
`RCC_APB1RSTR_I2C1RST`		21
`RCC_APB1RSTR_I2C2RST`		22
`RCC_APB1RSTR_I2C3RST`		23
`RCC_APB1RSTR_CAN1RST`		25
`RCC_APB1RSTR_CAN2RST`		26
`RCC_APB1RSTR_PWRRST`		28
`RCC_APB1RSTR_DACRST`		29
`APB2RSTR`	`0x24`	32	RCC APB2 peripheral reset register
`RCC_APB2RSTR_TIM1RST`		0
`RCC_APB2RSTR_TIM8RST`		1
`RCC_APB2RSTR_USART1RST`		4
`RCC_APB2RSTR_USART6RST`		5
`RCC_APB2RSTR_ADCRST`		8
`RCC_APB2RSTR_SDIORST`		11
`RCC_APB2RSTR_SPI1RST`		12
`RCC_APB2RSTR_SYSCFGRST`		14
`RCC_APB2RSTR_TIM9RST`		16
`RCC_APB2RSTR_TIM10RST`		17
`RCC_APB2RSTR_TIM11RST`		18
`AHB1ENR`	`0x30`	32	RCC AHB1 peripheral clock register
`RCC_AHB1ENR_GPIOAEN`		0
`RCC_AHB1ENR_GPIOBEN`		1
`RCC_AHB1ENR_GPIOCEN`		2
`RCC_AHB1ENR_GPIODEN`		3
`RCC_AHB1ENR_GPIOEEN`		4
`RCC_AHB1ENR_GPIOFEN`		5
`RCC_AHB1ENR_GPIOGEN`		6
`RCC_AHB1ENR_GPIOHEN`		7
`RCC_AHB1ENR_GPIOIEN`		8
`RCC_AHB1ENR_CRCEN`		12
`RCC_AHB1ENR_BKPSRAMEN`		18
`RCC_AHB1ENR_CCMDATARAMEN`		20
`RCC_AHB1ENR_DMA1EN`		21
`RCC_AHB1ENR_DMA2EN`		22
`RCC_AHB1ENR_ETHMACEN`		25
`RCC_AHB1ENR_ETHMACTXEN`		26
`RCC_AHB1ENR_ETHMACRXEN`		27
`RCC_AHB1ENR_ETHMACPTPEN`		28
`RCC_AHB1ENR_OTGHSEN`		29
`RCC_AHB1ENR_OTGHSULPIEN`		30
`AHB2ENR`	`0x34`	32	RCC AHB2 peripheral clock register
`RCC_AHB2ENR_DCMIEN`		0
`RCC_AHB2ENR_RNGEN`		6
`RCC_AHB2ENR_OTGFSEN`		7
`AHB3ENR`	`0x38`	32	RCC AHB3 peripheral clock register
`RCC_AHB3ENR_FSMCEN`		0
`APB1ENR`	`0x40`	32	RCC APB1 peripheral clock enable register
`RCC_APB1ENR_TIM2EN`		0
`RCC_APB1ENR_TIM3EN`		1
`RCC_APB1ENR_TIM4EN`		2
`RCC_APB1ENR_TIM5EN`		3
`RCC_APB1ENR_TIM6EN`		4
`RCC_APB1ENR_TIM7EN`		5
`RCC_APB1ENR_TIM12EN`		6
`RCC_APB1ENR_TIM13EN`		7
`RCC_APB1ENR_TIM14EN`		8
`RCC_APB1ENR_WWDGEN`		11
`RCC_APB1ENR_SPI2EN`		14
`RCC_APB1ENR_SPI3EN`		15
`RCC_APB1ENR_USART2EN`		17
`RCC_APB1ENR_USART3EN`		18
`RCC_APB1ENR_UART4EN`		19
`RCC_APB1ENR_UART5EN`		20
`RCC_APB1ENR_I2C1EN`		21
`RCC_APB1ENR_I2C2EN`		22
`RCC_APB1ENR_I2C3EN`		23
`RCC_APB1ENR_CAN1EN`		25
`RCC_APB1ENR_CAN2EN`		26
`RCC_APB1ENR_PWREN`		28
`RCC_APB1ENR_DACEN`		29
`APB2ENR`	`0x44`	32	RCC APB2 peripheral clock enable register
`RCC_APB2ENR_TIM1EN`		0
`RCC_APB2ENR_TIM8EN`		1
`RCC_APB2ENR_USART1EN`		4
`RCC_APB2ENR_USART6EN`		5
`RCC_APB2ENR_ADC1EN`		8
`RCC_APB2ENR_ADC2EN`		9
`RCC_APB2ENR_ADC3EN`		10
`RCC_APB2ENR_SDIOEN`		11
`RCC_APB2ENR_SPI1EN`		12
`RCC_APB2ENR_SYSCFGEN`		14
`RCC_APB2ENR_TIM9EN`		16
`RCC_APB2ENR_TIM10EN`		17
`RCC_APB2ENR_TIM11EN`		18
`AHB1LPENR`	`0x50`	32	RCC AHB1 peripheral clock enable in low power mode register
`RCC_AHB1LPENR_GPIOALPEN`		0
`RCC_AHB1LPENR_GPIOBLPEN`		1
`RCC_AHB1LPENR_GPIOCLPEN`		2
`RCC_AHB1LPENR_GPIODLPEN`		3
`RCC_AHB1LPENR_GPIOELPEN`		4
`RCC_AHB1LPENR_GPIOFLPEN`		5
`RCC_AHB1LPENR_GPIOGLPEN`		6
`RCC_AHB1LPENR_GPIOHLPEN`		7
`RCC_AHB1LPENR_GPIOILPEN`		8
`RCC_AHB1LPENR_CRCLPEN`		12
`RCC_AHB1LPENR_FLITFLPEN`		15
`RCC_AHB1LPENR_SRAM1LPEN`		16
`RCC_AHB1LPENR_SRAM2LPEN`		17
`RCC_AHB1LPENR_BKPSRAMLPEN`		18
`RCC_AHB1LPENR_DMA1LPEN`		21
`RCC_AHB1LPENR_DMA2LPEN`		22
`RCC_AHB1LPENR_ETHMACLPEN`		25
`RCC_AHB1LPENR_ETHMACTXLPEN`		26
`RCC_AHB1LPENR_ETHMACRXLPEN`		27
`RCC_AHB1LPENR_ETHMACPTPLPEN`		28
`RCC_AHB1LPENR_OTGHSLPEN`		29
`RCC_AHB1LPENR_OTGHSULPILPEN`		30
`AHB2LPENR`	`0x54`	32	RCC AHB2 peripheral clock enable in low power mode register
`RCC_AHB2LPENR_DCMILPEN`		0
`RCC_AHB2LPENR_RNGLPEN`		6
`RCC_AHB2LPENR_OTGFSLPEN`		7
`AHB3LPENR`	`0x58`	32	RCC AHB3 peripheral clock enable in low power mode register
`RCC_AHB3LPENR_FSMCLPEN`		0
`APB1LPENR`	`0x60`	32	RCC APB1 peripheral clock enable in low power mode register
`RCC_APB1LPENR_TIM2LPEN`		0
`RCC_APB1LPENR_TIM3LPEN`		1
`RCC_APB1LPENR_TIM4LPEN`		2
`RCC_APB1LPENR_TIM5LPEN`		3
`RCC_APB1LPENR_TIM6LPEN`		4
`RCC_APB1LPENR_TIM7LPEN`		5
`RCC_APB1LPENR_TIM12LPEN`		6
`RCC_APB1LPENR_TIM13LPEN`		7
`RCC_APB1LPENR_TIM14LPEN`		8
`RCC_APB1LPENR_WWDGLPEN`		11
`RCC_APB1LPENR_SPI2LPEN`		14
`RCC_APB1LPENR_SPI3LPEN`		15
`RCC_APB1LPENR_USART2LPEN`		17
`RCC_APB1LPENR_USART3LPEN`		18
`RCC_APB1LPENR_UART4LPEN`		19
`RCC_APB1LPENR_UART5LPEN`		20
`RCC_APB1LPENR_I2C1LPEN`		21
`RCC_APB1LPENR_I2C2LPEN`		22
`RCC_APB1LPENR_I2C3LPEN`		23
`RCC_APB1LPENR_CAN1LPEN`		25
`RCC_APB1LPENR_CAN2LPEN`		26
`RCC_APB1LPENR_PWRLPEN`		28
`RCC_APB1LPENR_DACLPEN`		29
`APB2LPENR`	`0x64`	32	RCC APB2 peripheral clock enable in low power mode register
`RCC_APB2LPENR_TIM1LPEN`		0
`RCC_APB2LPENR_TIM8LPEN`		1
`RCC_APB2LPENR_USART1LPEN`		4
`RCC_APB2LPENR_USART6LPEN`		5
`RCC_APB2LPENR_ADC1LPEN`		8
`RCC_APB2LPENR_ADC2LPEN`		9
`RCC_APB2LPENR_ADC3LPEN`		10
`RCC_APB2LPENR_SDIOLPEN`		11
`RCC_APB2LPENR_SPI1LPEN`		12
`RCC_APB2LPENR_SYSCFGLPEN`		14
`RCC_APB2LPENR_TIM9LPEN`		16
`RCC_APB2LPENR_TIM10LPEN`		17
`RCC_APB2LPENR_TIM11LPEN`		18
`BDCR`	`0x70`	32	RCC Backup domain control register
`RCC_BDCR_LSEON`		0
`RCC_BDCR_LSERDY`		1
`RCC_BDCR_LSEBYP`		2
`RCC_BDCR_RTCSEL`		8:9
`RCC_BDCR_RTCEN`		15
`RCC_BDCR_BDRST`		16
`CSR`	`0x74`	32	RCC clock control & status register
`RCC_CSR_LSION`		0
`RCC_CSR_LSIRDY`		1
`RCC_CSR_RMVF`		24
`RCC_CSR_BORRSTF`		25
`RCC_CSR_PINRSTF`		26
`RCC_CSR_PORRSTF`		27
`RCC_CSR_SFTRSTF`		28
`RCC_CSR_IWDGRSTF`		29
`RCC_CSR_WWDGRSTF`		30
`RCC_CSR_LPWRRSTF`		31
`SSCGR`	`0x80`	32	RCC spread spectrum clock generation register
`RCC_SSCGR_MODPER`		0:12
`RCC_SSCGR_INCSTEP`		13:27
`RCC_SSCGR_SPREADSEL`		30
`RCC_SSCGR_SSCGEN`		31
`PLLI2SCFGR`	`0x84`	32	RCC PLLI2S configuration register
`RCC_PLLI2SCFGR_PLLI2SN`		6:14
`RCC_PLLI2SCFGR_PLLI2SR`		28:30

GPIO — I/O ports (section 8) · STM32F401: present

Register	Offset	Bits	Purpose
`MODER`	`0x00`	32	GPIO port mode register
`GPIO_MODER_MODER0`		0:1
`GPIO_MODER_MODER1`		2:3
`GPIO_MODER_MODER2`		4:5
`GPIO_MODER_MODER3`		6:7
`GPIO_MODER_MODER4`		8:9
`GPIO_MODER_MODER5`		10:11
`GPIO_MODER_MODER6`		12:13
`GPIO_MODER_MODER7`		14:15
`GPIO_MODER_MODER8`		16:17
`GPIO_MODER_MODER9`		18:19
`GPIO_MODER_MODER10`		20:21
`GPIO_MODER_MODER11`		22:23
`GPIO_MODER_MODER12`		24:25
`GPIO_MODER_MODER13`		26:27
`GPIO_MODER_MODER14`		28:29
`GPIO_MODER_MODER15`		30:31
`OTYPER`	`0x04`	32	GPIO port output type register
`GPIO_OTYPER_OT0`		0
`GPIO_OTYPER_OT1`		1
`GPIO_OTYPER_OT2`		2
`GPIO_OTYPER_OT3`		3
`GPIO_OTYPER_OT4`		4
`GPIO_OTYPER_OT5`		5
`GPIO_OTYPER_OT6`		6
`GPIO_OTYPER_OT7`		7
`GPIO_OTYPER_OT8`		8
`GPIO_OTYPER_OT9`		9
`GPIO_OTYPER_OT10`		10
`GPIO_OTYPER_OT11`		11
`GPIO_OTYPER_OT12`		12
`GPIO_OTYPER_OT13`		13
`GPIO_OTYPER_OT14`		14
`GPIO_OTYPER_OT15`		15
`OSPEEDR`	`0x08`	32	GPIO port output speed register
`GPIO_OSPEEDR_OSPEED0`		0:1
`GPIO_OSPEEDR_OSPEED1`		2:3
`GPIO_OSPEEDR_OSPEED2`		4:5
`GPIO_OSPEEDR_OSPEED3`		6:7
`GPIO_OSPEEDR_OSPEED4`		8:9
`GPIO_OSPEEDR_OSPEED5`		10:11
`GPIO_OSPEEDR_OSPEED6`		12:13
`GPIO_OSPEEDR_OSPEED7`		14:15
`GPIO_OSPEEDR_OSPEED8`		16:17
`GPIO_OSPEEDR_OSPEED9`		18:19
`GPIO_OSPEEDR_OSPEED10`		20:21
`GPIO_OSPEEDR_OSPEED11`		22:23
`GPIO_OSPEEDR_OSPEED12`		24:25
`GPIO_OSPEEDR_OSPEED13`		26:27
`GPIO_OSPEEDR_OSPEED14`		28:29
`GPIO_OSPEEDR_OSPEED15`		30:31
`PUPDR`	`0x0C`	32	GPIO port pull-up/pull-down register
`GPIO_PUPDR_PUPD0`		0:1
`GPIO_PUPDR_PUPD1`		2:3
`GPIO_PUPDR_PUPD2`		4:5
`GPIO_PUPDR_PUPD3`		6:7
`GPIO_PUPDR_PUPD4`		8:9
`GPIO_PUPDR_PUPD5`		10:11
`GPIO_PUPDR_PUPD6`		12:13
`GPIO_PUPDR_PUPD7`		14:15
`GPIO_PUPDR_PUPD8`		16:17
`GPIO_PUPDR_PUPD9`		18:19
`GPIO_PUPDR_PUPD10`		20:21
`GPIO_PUPDR_PUPD11`		22:23
`GPIO_PUPDR_PUPD12`		24:25
`GPIO_PUPDR_PUPD13`		26:27
`GPIO_PUPDR_PUPD14`		28:29
`GPIO_PUPDR_PUPD15`		30:31
`IDR`	`0x10`	32	GPIO port input data register
`GPIO_IDR_ID0`		0
`GPIO_IDR_ID1`		1
`GPIO_IDR_ID2`		2
`GPIO_IDR_ID3`		3
`GPIO_IDR_ID4`		4
`GPIO_IDR_ID5`		5
`GPIO_IDR_ID6`		6
`GPIO_IDR_ID7`		7
`GPIO_IDR_ID8`		8
`GPIO_IDR_ID9`		9
`GPIO_IDR_ID10`		10
`GPIO_IDR_ID11`		11
`GPIO_IDR_ID12`		12
`GPIO_IDR_ID13`		13
`GPIO_IDR_ID14`		14
`GPIO_IDR_ID15`		15
`ODR`	`0x14`	32	GPIO port output data register
`GPIO_ODR_OD0`		0
`GPIO_ODR_OD1`		1
`GPIO_ODR_OD2`		2
`GPIO_ODR_OD3`		3
`GPIO_ODR_OD4`		4
`GPIO_ODR_OD5`		5
`GPIO_ODR_OD6`		6
`GPIO_ODR_OD7`		7
`GPIO_ODR_OD8`		8
`GPIO_ODR_OD9`		9
`GPIO_ODR_OD10`		10
`GPIO_ODR_OD11`		11
`GPIO_ODR_OD12`		12
`GPIO_ODR_OD13`		13
`GPIO_ODR_OD14`		14
`GPIO_ODR_OD15`		15
`BSRR`	`0x18`	32	GPIO port bit set/reset register
`GPIO_BSRR_BS0`		0
`GPIO_BSRR_BS1`		1
`GPIO_BSRR_BS2`		2
`GPIO_BSRR_BS3`		3
`GPIO_BSRR_BS4`		4
`GPIO_BSRR_BS5`		5
`GPIO_BSRR_BS6`		6
`GPIO_BSRR_BS7`		7
`GPIO_BSRR_BS8`		8
`GPIO_BSRR_BS9`		9
`GPIO_BSRR_BS10`		10
`GPIO_BSRR_BS11`		11
`GPIO_BSRR_BS12`		12
`GPIO_BSRR_BS13`		13
`GPIO_BSRR_BS14`		14
`GPIO_BSRR_BS15`		15
`GPIO_BSRR_BR0`		16
`GPIO_BSRR_BR1`		17
`GPIO_BSRR_BR2`		18
`GPIO_BSRR_BR3`		19
`GPIO_BSRR_BR4`		20
`GPIO_BSRR_BR5`		21
`GPIO_BSRR_BR6`		22
`GPIO_BSRR_BR7`		23
`GPIO_BSRR_BR8`		24
`GPIO_BSRR_BR9`		25
`GPIO_BSRR_BR10`		26
`GPIO_BSRR_BR11`		27
`GPIO_BSRR_BR12`		28
`GPIO_BSRR_BR13`		29
`GPIO_BSRR_BR14`		30
`GPIO_BSRR_BR15`		31
`LCKR`	`0x1C`	32	GPIO port configuration lock register
`GPIO_LCKR_LCK0`		0
`GPIO_LCKR_LCK1`		1
`GPIO_LCKR_LCK2`		2
`GPIO_LCKR_LCK3`		3
`GPIO_LCKR_LCK4`		4
`GPIO_LCKR_LCK5`		5
`GPIO_LCKR_LCK6`		6
`GPIO_LCKR_LCK7`		7
`GPIO_LCKR_LCK8`		8
`GPIO_LCKR_LCK9`		9
`GPIO_LCKR_LCK10`		10
`GPIO_LCKR_LCK11`		11
`GPIO_LCKR_LCK12`		12
`GPIO_LCKR_LCK13`		13
`GPIO_LCKR_LCK14`		14
`GPIO_LCKR_LCK15`		15
`GPIO_LCKR_LCKK`		16
`AFR`+2×4	`0x20`	32	GPIO alternate function registers

SYSCFG — System configuration: remap, EXTI to ports (section 8) · STM32F401: present

Register	Offset	Bits	Purpose
`MEMRMP`	`0x00`	32	SYSCFG memory remap register
`SYSCFG_MEMRMP_MEM_MODE`		0:1	SYSCFG_Memory Remap Config
`PMC`	`0x04`	32	SYSCFG peripheral mode configuration register
`SYSCFG_PMC_MII_RMII_SEL`		23	Ethernet PHY interface selection
`EXTICR`+4×4	`0x08`	32	SYSCFG external interrupt configuration registers
`CMPCR`	`0x20`	32	SYSCFG Compensation cell control register
`SYSCFG_CMPCR_CMP_PD`		0	Compensation cell ready flag
`SYSCFG_CMPCR_READY`		8	Compensation cell power-down

EXTI — External interrupts (section 7) · STM32F401: present

Register	Offset	Bits	Purpose
`IMR`	`0x00`	32	EXTI Interrupt mask register
`EXTI_IMR_MR0`		0	Interrupt Mask on line 0
`EXTI_IMR_IM`		0:22	Interrupt Mask All
`EXTI_IMR_MR1`		1	Interrupt Mask on line 1
`EXTI_IMR_MR2`		2	Interrupt Mask on line 2
`EXTI_IMR_MR3`		3	Interrupt Mask on line 3
`EXTI_IMR_MR4`		4	Interrupt Mask on line 4
`EXTI_IMR_MR5`		5	Interrupt Mask on line 5
`EXTI_IMR_MR6`		6	Interrupt Mask on line 6
`EXTI_IMR_MR7`		7	Interrupt Mask on line 7
`EXTI_IMR_MR8`		8	Interrupt Mask on line 8
`EXTI_IMR_MR9`		9	Interrupt Mask on line 9
`EXTI_IMR_MR10`		10	Interrupt Mask on line 10
`EXTI_IMR_MR11`		11	Interrupt Mask on line 11
`EXTI_IMR_MR12`		12	Interrupt Mask on line 12
`EXTI_IMR_MR13`		13	Interrupt Mask on line 13
`EXTI_IMR_MR14`		14	Interrupt Mask on line 14
`EXTI_IMR_MR15`		15	Interrupt Mask on line 15
`EXTI_IMR_MR16`		16	Interrupt Mask on line 16
`EXTI_IMR_MR17`		17	Interrupt Mask on line 17
`EXTI_IMR_MR18`		18	Interrupt Mask on line 18
`EXTI_IMR_MR19`		19	Interrupt Mask on line 19
`EXTI_IMR_MR20`		20	Interrupt Mask on line 20
`EXTI_IMR_MR21`		21	Interrupt Mask on line 21
`EXTI_IMR_MR22`		22	Interrupt Mask on line 22
`EMR`	`0x04`	32	EXTI Event mask register
`EXTI_EMR_MR0`		0	Event Mask on line 0
`EXTI_EMR_MR1`		1	Event Mask on line 1
`EXTI_EMR_MR2`		2	Event Mask on line 2
`EXTI_EMR_MR3`		3	Event Mask on line 3
`EXTI_EMR_MR4`		4	Event Mask on line 4
`EXTI_EMR_MR5`		5	Event Mask on line 5
`EXTI_EMR_MR6`		6	Event Mask on line 6
`EXTI_EMR_MR7`		7	Event Mask on line 7
`EXTI_EMR_MR8`		8	Event Mask on line 8
`EXTI_EMR_MR9`		9	Event Mask on line 9
`EXTI_EMR_MR10`		10	Event Mask on line 10
`EXTI_EMR_MR11`		11	Event Mask on line 11
`EXTI_EMR_MR12`		12	Event Mask on line 12
`EXTI_EMR_MR13`		13	Event Mask on line 13
`EXTI_EMR_MR14`		14	Event Mask on line 14
`EXTI_EMR_MR15`		15	Event Mask on line 15
`EXTI_EMR_MR16`		16	Event Mask on line 16
`EXTI_EMR_MR17`		17	Event Mask on line 17
`EXTI_EMR_MR18`		18	Event Mask on line 18
`EXTI_EMR_MR19`		19	Event Mask on line 19
`EXTI_EMR_MR20`		20	Event Mask on line 20
`EXTI_EMR_MR21`		21	Event Mask on line 21
`EXTI_EMR_MR22`		22	Event Mask on line 22
`RTSR`	`0x08`	32	EXTI Rising trigger selection register
`EXTI_RTSR_TR0`		0	Rising trigger event configuration bit of line 0
`EXTI_RTSR_TR1`		1	Rising trigger event configuration bit of line 1
`EXTI_RTSR_TR2`		2	Rising trigger event configuration bit of line 2
`EXTI_RTSR_TR3`		3	Rising trigger event configuration bit of line 3
`EXTI_RTSR_TR4`		4	Rising trigger event configuration bit of line 4
`EXTI_RTSR_TR5`		5	Rising trigger event configuration bit of line 5
`EXTI_RTSR_TR6`		6	Rising trigger event configuration bit of line 6
`EXTI_RTSR_TR7`		7	Rising trigger event configuration bit of line 7
`EXTI_RTSR_TR8`		8	Rising trigger event configuration bit of line 8
`EXTI_RTSR_TR9`		9	Rising trigger event configuration bit of line 9
`EXTI_RTSR_TR10`		10	Rising trigger event configuration bit of line 10
`EXTI_RTSR_TR11`		11	Rising trigger event configuration bit of line 11
`EXTI_RTSR_TR12`		12	Rising trigger event configuration bit of line 12
`EXTI_RTSR_TR13`		13	Rising trigger event configuration bit of line 13
`EXTI_RTSR_TR14`		14	Rising trigger event configuration bit of line 14
`EXTI_RTSR_TR15`		15	Rising trigger event configuration bit of line 15
`EXTI_RTSR_TR16`		16	Rising trigger event configuration bit of line 16
`EXTI_RTSR_TR17`		17	Rising trigger event configuration bit of line 17
`EXTI_RTSR_TR18`		18	Rising trigger event configuration bit of line 18
`EXTI_RTSR_TR19`		19	Rising trigger event configuration bit of line 19
`EXTI_RTSR_TR20`		20	Rising trigger event configuration bit of line 20
`EXTI_RTSR_TR21`		21	Rising trigger event configuration bit of line 21
`EXTI_RTSR_TR22`		22	Rising trigger event configuration bit of line 22
`FTSR`	`0x0C`	32	EXTI Falling trigger selection register
`EXTI_FTSR_TR0`		0	Falling trigger event configuration bit of line 0
`EXTI_FTSR_TR1`		1	Falling trigger event configuration bit of line 1
`EXTI_FTSR_TR2`		2	Falling trigger event configuration bit of line 2
`EXTI_FTSR_TR3`		3	Falling trigger event configuration bit of line 3
`EXTI_FTSR_TR4`		4	Falling trigger event configuration bit of line 4
`EXTI_FTSR_TR5`		5	Falling trigger event configuration bit of line 5
`EXTI_FTSR_TR6`		6	Falling trigger event configuration bit of line 6
`EXTI_FTSR_TR7`		7	Falling trigger event configuration bit of line 7
`EXTI_FTSR_TR8`		8	Falling trigger event configuration bit of line 8
`EXTI_FTSR_TR9`		9	Falling trigger event configuration bit of line 9
`EXTI_FTSR_TR10`		10	Falling trigger event configuration bit of line 10
`EXTI_FTSR_TR11`		11	Falling trigger event configuration bit of line 11
`EXTI_FTSR_TR12`		12	Falling trigger event configuration bit of line 12
`EXTI_FTSR_TR13`		13	Falling trigger event configuration bit of line 13
`EXTI_FTSR_TR14`		14	Falling trigger event configuration bit of line 14
`EXTI_FTSR_TR15`		15	Falling trigger event configuration bit of line 15
`EXTI_FTSR_TR16`		16	Falling trigger event configuration bit of line 16
`EXTI_FTSR_TR17`		17	Falling trigger event configuration bit of line 17
`EXTI_FTSR_TR18`		18	Falling trigger event configuration bit of line 18
`EXTI_FTSR_TR19`		19	Falling trigger event configuration bit of line 19
`EXTI_FTSR_TR20`		20	Falling trigger event configuration bit of line 20
`EXTI_FTSR_TR21`		21	Falling trigger event configuration bit of line 21
`EXTI_FTSR_TR22`		22	Falling trigger event configuration bit of line 22
`SWIER`	`0x10`	32	EXTI Software interrupt event register
`EXTI_SWIER_SWIER0`		0	Software Interrupt on line 0
`EXTI_SWIER_SWIER1`		1	Software Interrupt on line 1
`EXTI_SWIER_SWIER2`		2	Software Interrupt on line 2
`EXTI_SWIER_SWIER3`		3	Software Interrupt on line 3
`EXTI_SWIER_SWIER4`		4	Software Interrupt on line 4
`EXTI_SWIER_SWIER5`		5	Software Interrupt on line 5
`EXTI_SWIER_SWIER6`		6	Software Interrupt on line 6
`EXTI_SWIER_SWIER7`		7	Software Interrupt on line 7
`EXTI_SWIER_SWIER8`		8	Software Interrupt on line 8
`EXTI_SWIER_SWIER9`		9	Software Interrupt on line 9
`EXTI_SWIER_SWIER10`		10	Software Interrupt on line 10
`EXTI_SWIER_SWIER11`		11	Software Interrupt on line 11
`EXTI_SWIER_SWIER12`		12	Software Interrupt on line 12
`EXTI_SWIER_SWIER13`		13	Software Interrupt on line 13
`EXTI_SWIER_SWIER14`		14	Software Interrupt on line 14
`EXTI_SWIER_SWIER15`		15	Software Interrupt on line 15
`EXTI_SWIER_SWIER16`		16	Software Interrupt on line 16
`EXTI_SWIER_SWIER17`		17	Software Interrupt on line 17
`EXTI_SWIER_SWIER18`		18	Software Interrupt on line 18
`EXTI_SWIER_SWIER19`		19	Software Interrupt on line 19
`EXTI_SWIER_SWIER20`		20	Software Interrupt on line 20
`EXTI_SWIER_SWIER21`		21	Software Interrupt on line 21
`EXTI_SWIER_SWIER22`		22	Software Interrupt on line 22
`PR`	`0x14`	32	EXTI Pending register
`EXTI_PR_PR0`		0	Pending bit for line 0
`EXTI_PR_PR1`		1	Pending bit for line 1
`EXTI_PR_PR2`		2	Pending bit for line 2
`EXTI_PR_PR3`		3	Pending bit for line 3
`EXTI_PR_PR4`		4	Pending bit for line 4
`EXTI_PR_PR5`		5	Pending bit for line 5
`EXTI_PR_PR6`		6	Pending bit for line 6
`EXTI_PR_PR7`		7	Pending bit for line 7
`EXTI_PR_PR8`		8	Pending bit for line 8
`EXTI_PR_PR9`		9	Pending bit for line 9
`EXTI_PR_PR10`		10	Pending bit for line 10
`EXTI_PR_PR11`		11	Pending bit for line 11
`EXTI_PR_PR12`		12	Pending bit for line 12
`EXTI_PR_PR13`		13	Pending bit for line 13
`EXTI_PR_PR14`		14	Pending bit for line 14
`EXTI_PR_PR15`		15	Pending bit for line 15
`EXTI_PR_PR16`		16	Pending bit for line 16
`EXTI_PR_PR17`		17	Pending bit for line 17
`EXTI_PR_PR18`		18	Pending bit for line 18
`EXTI_PR_PR19`		19	Pending bit for line 19
`EXTI_PR_PR20`		20	Pending bit for line 20
`EXTI_PR_PR21`		21	Pending bit for line 21
`EXTI_PR_PR22`		22	Pending bit for line 22

DMA — DMA stream (section 9) · STM32F401: present

Register	Offset	Bits	Purpose
`CR`	`0x00`	32	DMA stream x configuration register
`NDTR`	`0x04`	32	DMA stream x number of data register
`PAR`	`0x08`	32	DMA stream x peripheral address register
`M0AR`	`0x0C`	32	DMA stream x memory 0 address register
`M1AR`	`0x10`	32	DMA stream x memory 1 address register
`FCR`	`0x14`	32	DMA stream x FIFO control register

PWR — Power (section 10) · STM32F401: present

Register	Offset	Bits	Purpose
`CR`	`0x00`	32	PWR power control register
`PWR_CR_LPDS`		0	Low-Power Deepsleep
`PWR_CR_PDDS`		1	Power Down Deepsleep
`PWR_CR_CWUF`		2	Clear Wakeup Flag
`PWR_CR_CSBF`		3	Clear Standby Flag
`PWR_CR_PVDE`		4	Power Voltage Detector Enable
`PWR_CR_PLS`		5:7	PLS[2:0] bits (PVD Level Selection)
`PWR_CR_DBP`		8	Disable Backup Domain write protection
`PWR_CR_FPDS`		9	Flash power down in Stop mode
`PWR_CR_VOS`		14	VOS bit (Regulator voltage scaling output selection)
`CSR`	`0x04`	32	PWR power control/status register
`PWR_CSR_WUF`		0	Wakeup Flag
`PWR_CSR_SBF`		1	Standby Flag
`PWR_CSR_PVDO`		2	PVD Output
`PWR_CSR_BRR`		3	Backup regulator ready
`PWR_CSR_EWUP`		8	Enable WKUP pin
`PWR_CSR_BRE`		9	Backup regulator enable
`PWR_CSR_VOSRDY`		14	Regulator voltage scaling output selection ready

FLASH — Flash controller (section 11) · STM32F401: present

Register	Offset	Bits	Purpose
`ACR`	`0x00`	32	FLASH access control register
`FLASH_ACR_LATENCY`		0:2
`FLASH_ACR_BYTE2_ADDRESS`		0:30
`FLASH_ACR_PRFTEN`		8
`FLASH_ACR_ICEN`		9
`FLASH_ACR_DCEN`		10
`FLASH_ACR_BYTE0_ADDRESS`		10:30
`FLASH_ACR_ICRST`		11
`FLASH_ACR_DCRST`		12
`KEYR`	`0x04`	32	FLASH key register
`OPTKEYR`	`0x08`	32	FLASH option key register
`SR`	`0x0C`	32	FLASH status register
`FLASH_SR_EOP`		0
`FLASH_SR_SOP`		1
`FLASH_SR_WRPERR`		4
`FLASH_SR_PGAERR`		5
`FLASH_SR_PGPERR`		6
`FLASH_SR_PGSERR`		7
`FLASH_SR_BSY`		16
`CR`	`0x10`	32	FLASH control register
`FLASH_CR_PG`		0
`FLASH_CR_SER`		1
`FLASH_CR_MER`		2
`FLASH_CR_SNB`		3:7
`FLASH_CR_PSIZE`		8:9
`FLASH_CR_STRT`		16
`FLASH_CR_EOPIE`		24
`FLASH_CR_LOCK`		31
`OPTCR`	`0x14`	32	FLASH option control register
`FLASH_OPTCR_OPTLOCK`		0
`FLASH_OPTCR_OPTSTRT`		1
`FLASH_OPTCR_BOR_LEV`		2:3
`FLASH_OPTCR_WDG_SW`		5
`FLASH_OPTCR_nRST_STOP`		6
`FLASH_OPTCR_nRST_STDBY`		7
`FLASH_OPTCR_RDP`		8:15
`FLASH_OPTCR_nWRP`		16:27
`OPTCR1`	`0x18`	32	FLASH option control register 1
`FLASH_OPTCR1_nWRP`		16:27

IWDG — Independent watchdog (section 12) · STM32F401: present

Register	Offset	Bits	Purpose
`KR`	`0x00`	32	IWDG Key register
`IWDG_KR_KEY`		0:15	Key value (write only, read 0000h)
`PR`	`0x04`	32	IWDG Prescaler register
`IWDG_PR_PR`		0:2	PR[2:0] (Prescaler divider)
`RLR`	`0x08`	32	IWDG Reload register
`IWDG_RLR_RL`		0:11	Watchdog counter reload value
`SR`	`0x0C`	32	IWDG Status register
`IWDG_SR_PVU`		0	Watchdog prescaler value update
`IWDG_SR_RVU`		1	Watchdog counter reload value update

WWDG — Window watchdog (section 12) · STM32F401: present

Register	Offset	Bits	Purpose
`CR`	`0x00`	32	WWDG Control register
`WWDG_CR_T`		0:6	T[6:0] bits (7-Bit counter (MSB to LSB))
`WWDG_CR_WDGA`		7	Activation bit
`CFR`	`0x04`	32	WWDG Configuration register
`WWDG_CFR_W`		0:6	W[6:0] bits (7-bit window value)
`WWDG_CFR_WDGTB`		7:8	WDGTB[1:0] bits (Timer Base)
`WWDG_CFR_EWI`		9	Early Wakeup Interrupt
`SR`	`0x08`	32	WWDG Status register
`WWDG_SR_EWIF`		0	Early Wakeup Interrupt Flag

CRC — Checksum (CRC) (section 12) · STM32F401: present

Register	Offset	Bits	Purpose
`DR`	`0x00`	32	CRC Data register
`CRC_DR_DR`		0:31	Data register bits
`IDR`	`0x04`	8	CRC Independent data register
`CRC_IDR_IDR`		0:7	General-purpose 8-bit data register bits
`CR`	`0x08`	32	CRC Control register
`CRC_CR_RESET`		0	RESET bit

RTC — Real-time clock (section 12) · STM32F401: present

Register	Offset	Bits	Purpose
`TR`	`0x00`	32	RTC time register
`RTC_TR_SU`		0:3
`RTC_TR_ST`		4:6
`RTC_TR_MNU`		8:11
`RTC_TR_MNT`		12:14
`RTC_TR_HU`		16:19
`RTC_TR_HT`		20:21
`RTC_TR_PM`		22
`DR`	`0x04`	32	RTC date register
`RTC_DR_DU`		0:3
`RTC_DR_DT`		4:5
`RTC_DR_MU`		8:11
`RTC_DR_MT`		12
`RTC_DR_WDU`		13:15
`RTC_DR_YU`		16:19
`RTC_DR_YT`		20:23
`CR`	`0x08`	32	RTC control register
`RTC_CR_WUCKSEL`		0:2
`RTC_CR_TSEDGE`		3
`RTC_CR_REFCKON`		4
`RTC_CR_BYPSHAD`		5
`RTC_CR_FMT`		6
`RTC_CR_DCE`		7
`RTC_CR_ALRAE`		8
`RTC_CR_ALRBE`		9
`RTC_CR_WUTE`		10
`RTC_CR_TSE`		11
`RTC_CR_ALRAIE`		12
`RTC_CR_ALRBIE`		13
`RTC_CR_WUTIE`		14
`RTC_CR_TSIE`		15
`RTC_CR_ADD1H`		16
`RTC_CR_SUB1H`		17
`RTC_CR_BKP`		18
`RTC_CR_COSEL`		19
`RTC_CR_POL`		20
`RTC_CR_OSEL`		21:22
`RTC_CR_COE`		23
`ISR`	`0x0C`	32	RTC initialization and status register
`RTC_ISR_ALRAWF`		0
`RTC_ISR_ALRBWF`		1
`RTC_ISR_WUTWF`		2
`RTC_ISR_SHPF`		3
`RTC_ISR_INITS`		4
`RTC_ISR_RSF`		5
`RTC_ISR_INITF`		6
`RTC_ISR_INIT`		7
`RTC_ISR_ALRAF`		8
`RTC_ISR_ALRBF`		9
`RTC_ISR_WUTF`		10
`RTC_ISR_TSF`		11
`RTC_ISR_TSOVF`		12
`RTC_ISR_TAMP1F`		13
`RTC_ISR_TAMP2F`		14
`RTC_ISR_RECALPF`		16
`PRER`	`0x10`	32	RTC prescaler register
`RTC_PRER_PREDIV_S`		0:14
`RTC_PRER_PREDIV_A`		16:22
`WUTR`	`0x14`	32	RTC wakeup timer register
`RTC_WUTR_WUT`		0:15
`CALIBR`	`0x18`	32	RTC calibration register
`RTC_CALIBR_DC`		0:4
`RTC_CALIBR_DCS`		7
`ALRMAR`	`0x1C`	32	RTC alarm A register
`RTC_ALRMAR_SU`		0:3
`RTC_ALRMAR_ST`		4:6
`RTC_ALRMAR_MSK1`		7
`RTC_ALRMAR_MNU`		8:11
`RTC_ALRMAR_MNT`		12:14
`RTC_ALRMAR_MSK2`		15
`RTC_ALRMAR_HU`		16:19
`RTC_ALRMAR_HT`		20:21
`RTC_ALRMAR_PM`		22
`RTC_ALRMAR_MSK3`		23
`RTC_ALRMAR_DU`		24:27
`RTC_ALRMAR_DT`		28:29
`RTC_ALRMAR_WDSEL`		30
`RTC_ALRMAR_MSK4`		31
`ALRMBR`	`0x20`	32	RTC alarm B register
`RTC_ALRMBR_SU`		0:3
`RTC_ALRMBR_ST`		4:6
`RTC_ALRMBR_MSK1`		7
`RTC_ALRMBR_MNU`		8:11
`RTC_ALRMBR_MNT`		12:14
`RTC_ALRMBR_MSK2`		15
`RTC_ALRMBR_HU`		16:19
`RTC_ALRMBR_HT`		20:21
`RTC_ALRMBR_PM`		22
`RTC_ALRMBR_MSK3`		23
`RTC_ALRMBR_DU`		24:27
`RTC_ALRMBR_DT`		28:29
`RTC_ALRMBR_WDSEL`		30
`RTC_ALRMBR_MSK4`		31
`WPR`	`0x24`	32	RTC write protection register
`RTC_WPR_KEY`		0:7
`SSR`	`0x28`	32	RTC sub second register
`RTC_SSR_SS`		0:15
`SHIFTR`	`0x2C`	32	RTC shift control register
`RTC_SHIFTR_SUBFS`		0:14
`RTC_SHIFTR_ADD1S`		31
`TSTR`	`0x30`	32	RTC time stamp time register
`RTC_TSTR_SU`		0:3
`RTC_TSTR_ST`		4:6
`RTC_TSTR_MNU`		8:11
`RTC_TSTR_MNT`		12:14
`RTC_TSTR_HU`		16:19
`RTC_TSTR_HT`		20:21
`RTC_TSTR_PM`		22
`TSDR`	`0x34`	32	RTC time stamp date register
`RTC_TSDR_DU`		0:3
`RTC_TSDR_DT`		4:5
`RTC_TSDR_MU`		8:11
`RTC_TSDR_MT`		12
`RTC_TSDR_WDU`		13:15
`TSSSR`	`0x38`	32	RTC time-stamp sub second register
`RTC_TSSSR_SS`		0:15
`CALR`	`0x3C`	32	RTC calibration register
`RTC_CALR_CALM`		0:8
`RTC_CALR_CALW16`		13
`RTC_CALR_CALW8`		14
`RTC_CALR_CALP`		15
`TAFCR`	`0x40`	32	RTC tamper and alternate function configuration register
`RTC_TAFCR_TAMP1E`		0
`RTC_TAFCR_TAMP1TRG`		1
`RTC_TAFCR_TAMPIE`		2
`RTC_TAFCR_TAMP2E`		3
`RTC_TAFCR_TAMP2TRG`		4
`RTC_TAFCR_TAMPTS`		7
`RTC_TAFCR_TAMPFREQ`		8:10
`RTC_TAFCR_TAMPFLT`		11:12
`RTC_TAFCR_TAMPPRCH`		13:14
`RTC_TAFCR_TAMPPUDIS`		15
`RTC_TAFCR_TAMP1INSEL`		16
`RTC_TAFCR_TSINSEL`		17
`RTC_TAFCR_ALARMOUTTYPE`		18
`ALRMASSR`	`0x44`	32	RTC alarm A sub second register
`RTC_ALRMASSR_SS`		0:14
`RTC_ALRMASSR_MASKSS`		24:27
`ALRMBSSR`	`0x48`	32	RTC alarm B sub second register
`RTC_ALRMBSSR_SS`		0:14
`RTC_ALRMBSSR_MASKSS`		24:27
`BKP0R`	`0x50`	32	RTC backup register 1
`BKP1R`	`0x54`	32	RTC backup register 1
`BKP2R`	`0x58`	32	RTC backup register 2
`BKP3R`	`0x5C`	32	RTC backup register 3
`BKP4R`	`0x60`	32	RTC backup register 4
`BKP5R`	`0x64`	32	RTC backup register 5
`BKP6R`	`0x68`	32	RTC backup register 6
`BKP7R`	`0x6C`	32	RTC backup register 7
`BKP8R`	`0x70`	32	RTC backup register 8
`BKP9R`	`0x74`	32	RTC backup register 9
`BKP10R`	`0x78`	32	RTC backup register 10
`BKP11R`	`0x7C`	32	RTC backup register 11
`BKP12R`	`0x80`	32	RTC backup register 12
`BKP13R`	`0x84`	32	RTC backup register 13
`BKP14R`	`0x88`	32	RTC backup register 14
`BKP15R`	`0x8C`	32	RTC backup register 15
`BKP16R`	`0x90`	32	RTC backup register 16
`BKP17R`	`0x94`	32	RTC backup register 17
`BKP18R`	`0x98`	32	RTC backup register 18
`BKP19R`	`0x9C`	32	RTC backup register 19

TIM — Timers (section 13) · STM32F401: present

Register	Offset	Bits	Purpose
`CR1`	`0x00`	32	TIM control register 1
`TIM_CR1_CEN`		0	Counter enable
`TIM_CR1_UDIS`		1	Update disable
`TIM_CR1_URS`		2	Update request source
`TIM_CR1_OPM`		3	One pulse mode
`TIM_CR1_DIR`		4	Direction
`TIM_CR1_CMS`		5:6	CMS[1:0] bits (Center-aligned mode selection)
`TIM_CR1_ARPE`		7	Auto-reload preload enable
`TIM_CR1_CKD`		8:9	CKD[1:0] bits (clock division)
`CR2`	`0x04`	32	TIM control register 2
`TIM_CR2_CCPC`		0	Capture/Compare Preloaded Control
`TIM_CR2_CCUS`		2	Capture/Compare Control Update Selection
`TIM_CR2_CCDS`		3	Capture/Compare DMA Selection
`TIM_CR2_MMS`		4:6	MMS[2:0] bits (Master Mode Selection)
`TIM_CR2_TI1S`		7	TI1 Selection
`TIM_CR2_OIS1`		8	Output Idle state 1 (OC1 output)
`TIM_CR2_OIS1N`		9	Output Idle state 1 (OC1N output)
`TIM_CR2_OIS2`		10	Output Idle state 2 (OC2 output)
`TIM_CR2_OIS2N`		11	Output Idle state 2 (OC2N output)
`TIM_CR2_OIS3`		12	Output Idle state 3 (OC3 output)
`TIM_CR2_OIS3N`		13	Output Idle state 3 (OC3N output)
`TIM_CR2_OIS4`		14	Output Idle state 4 (OC4 output)
`SMCR`	`0x08`	32	TIM slave mode control register
`TIM_SMCR_SMS`		0:2	SMS[2:0] bits (Slave mode selection)
`TIM_SMCR_TS`		4:6	TS[2:0] bits (Trigger selection)
`TIM_SMCR_MSM`		7	Master/slave mode
`TIM_SMCR_ETF`		8:11	ETF[3:0] bits (External trigger filter)
`TIM_SMCR_ETPS`		12:13	ETPS[1:0] bits (External trigger prescaler)
`TIM_SMCR_ECE`		14	External clock enable
`TIM_SMCR_ETP`		15	External trigger polarity
`DIER`	`0x0C`	32	TIM DMA/interrupt enable register
`TIM_DIER_UIE`		0	Update interrupt enable
`TIM_DIER_CC1IE`		1	Capture/Compare 1 interrupt enable
`TIM_DIER_CC2IE`		2	Capture/Compare 2 interrupt enable
`TIM_DIER_CC3IE`		3	Capture/Compare 3 interrupt enable
`TIM_DIER_CC4IE`		4	Capture/Compare 4 interrupt enable
`TIM_DIER_COMIE`		5	COM interrupt enable
`TIM_DIER_TIE`		6	Trigger interrupt enable
`TIM_DIER_BIE`		7	Break interrupt enable
`TIM_DIER_UDE`		8	Update DMA request enable
`TIM_DIER_CC1DE`		9	Capture/Compare 1 DMA request enable
`TIM_DIER_CC2DE`		10	Capture/Compare 2 DMA request enable
`TIM_DIER_CC3DE`		11	Capture/Compare 3 DMA request enable
`TIM_DIER_CC4DE`		12	Capture/Compare 4 DMA request enable
`TIM_DIER_COMDE`		13	COM DMA request enable
`TIM_DIER_TDE`		14	Trigger DMA request enable
`SR`	`0x10`	32	TIM status register
`TIM_SR_UIF`		0	Update interrupt Flag
`TIM_SR_CC1IF`		1	Capture/Compare 1 interrupt Flag
`TIM_SR_CC2IF`		2	Capture/Compare 2 interrupt Flag
`TIM_SR_CC3IF`		3	Capture/Compare 3 interrupt Flag
`TIM_SR_CC4IF`		4	Capture/Compare 4 interrupt Flag
`TIM_SR_COMIF`		5	COM interrupt Flag
`TIM_SR_TIF`		6	Trigger interrupt Flag
`TIM_SR_BIF`		7	Break interrupt Flag
`TIM_SR_CC1OF`		9	Capture/Compare 1 Overcapture Flag
`TIM_SR_CC2OF`		10	Capture/Compare 2 Overcapture Flag
`TIM_SR_CC3OF`		11	Capture/Compare 3 Overcapture Flag
`TIM_SR_CC4OF`		12	Capture/Compare 4 Overcapture Flag
`EGR`	`0x14`	32	TIM event generation register
`TIM_EGR_UG`		0	Update Generation
`TIM_EGR_CC1G`		1	Capture/Compare 1 Generation
`TIM_EGR_CC2G`		2	Capture/Compare 2 Generation
`TIM_EGR_CC3G`		3	Capture/Compare 3 Generation
`TIM_EGR_CC4G`		4	Capture/Compare 4 Generation
`TIM_EGR_COMG`		5	Capture/Compare Control Update Generation
`TIM_EGR_TG`		6	Trigger Generation
`TIM_EGR_BG`		7	Break Generation
`CCMR1`	`0x18`	32	TIM capture/compare mode register 1
`TIM_CCMR1_CC1S`		0:1	CC1S[1:0] bits (Capture/Compare 1 Selection)
`TIM_CCMR1_OC1FE`		2	Output Compare 1 Fast enable
`TIM_CCMR1_IC1PSC`		2:3	IC1PSC[1:0] bits (Input Capture 1 Prescaler)
`TIM_CCMR1_OC1PE`		3	Output Compare 1 Preload enable
`TIM_CCMR1_OC1M`		4:6	OC1M[2:0] bits (Output Compare 1 Mode)
`TIM_CCMR1_IC1F`		4:7	IC1F[3:0] bits (Input Capture 1 Filter)
`TIM_CCMR1_OC1CE`		7	Output Compare 1Clear Enable
`TIM_CCMR1_CC2S`		8:9	CC2S[1:0] bits (Capture/Compare 2 Selection)
`TIM_CCMR1_OC2FE`		10	Output Compare 2 Fast enable
`TIM_CCMR1_IC2PSC`		10:11	IC2PSC[1:0] bits (Input Capture 2 Prescaler)
`TIM_CCMR1_OC2PE`		11	Output Compare 2 Preload enable
`TIM_CCMR1_OC2M`		12:14	OC2M[2:0] bits (Output Compare 2 Mode)
`TIM_CCMR1_IC2F`		12:15	IC2F[3:0] bits (Input Capture 2 Filter)
`TIM_CCMR1_OC2CE`		15	Output Compare 2 Clear Enable
`CCMR2`	`0x1C`	32	TIM capture/compare mode register 2
`TIM_CCMR2_CC3S`		0:1	CC3S[1:0] bits (Capture/Compare 3 Selection)
`TIM_CCMR2_OC3FE`		2	Output Compare 3 Fast enable
`TIM_CCMR2_IC3PSC`		2:3	IC3PSC[1:0] bits (Input Capture 3 Prescaler)
`TIM_CCMR2_OC3PE`		3	Output Compare 3 Preload enable
`TIM_CCMR2_OC3M`		4:6	OC3M[2:0] bits (Output Compare 3 Mode)
`TIM_CCMR2_IC3F`		4:7	IC3F[3:0] bits (Input Capture 3 Filter)
`TIM_CCMR2_OC3CE`		7	Output Compare 3 Clear Enable
`TIM_CCMR2_CC4S`		8:9	CC4S[1:0] bits (Capture/Compare 4 Selection)
`TIM_CCMR2_OC4FE`		10	Output Compare 4 Fast enable
`TIM_CCMR2_IC4PSC`		10:11	IC4PSC[1:0] bits (Input Capture 4 Prescaler)
`TIM_CCMR2_OC4PE`		11	Output Compare 4 Preload enable
`TIM_CCMR2_OC4M`		12:14	OC4M[2:0] bits (Output Compare 4 Mode)
`TIM_CCMR2_IC4F`		12:15	IC4F[3:0] bits (Input Capture 4 Filter)
`TIM_CCMR2_OC4CE`		15	Output Compare 4 Clear Enable
`CCER`	`0x20`	32	TIM capture/compare enable register
`TIM_CCER_CC1E`		0	Capture/Compare 1 output enable
`TIM_CCER_CC1P`		1	Capture/Compare 1 output Polarity
`TIM_CCER_CC1NE`		2	Capture/Compare 1 Complementary output enable
`TIM_CCER_CC1NP`		3	Capture/Compare 1 Complementary output Polarity
`TIM_CCER_CC2E`		4	Capture/Compare 2 output enable
`TIM_CCER_CC2P`		5	Capture/Compare 2 output Polarity
`TIM_CCER_CC2NE`		6	Capture/Compare 2 Complementary output enable
`TIM_CCER_CC2NP`		7	Capture/Compare 2 Complementary output Polarity
`TIM_CCER_CC3E`		8	Capture/Compare 3 output enable
`TIM_CCER_CC3P`		9	Capture/Compare 3 output Polarity
`TIM_CCER_CC3NE`		10	Capture/Compare 3 Complementary output enable
`TIM_CCER_CC3NP`		11	Capture/Compare 3 Complementary output Polarity
`TIM_CCER_CC4E`		12	Capture/Compare 4 output enable
`TIM_CCER_CC4P`		13	Capture/Compare 4 output Polarity
`TIM_CCER_CC4NP`		15	Capture/Compare 4 Complementary output Polarity
`CNT`	`0x24`	32	TIM counter register
`TIM_CNT_CNT`		0:31	Counter Value
`PSC`	`0x28`	32	TIM prescaler
`TIM_PSC_PSC`		0:15	Prescaler Value
`ARR`	`0x2C`	32	TIM auto-reload register
`TIM_ARR_ARR`		0:31	actual auto-reload Value
`RCR`	`0x30`	32	TIM repetition counter register
`TIM_RCR_REP`		0:7	Repetition Counter Value
`CCR1`	`0x34`	32	TIM capture/compare register 1
`TIM_CCR1_CCR1`		0:15	Capture/Compare 1 Value
`CCR2`	`0x38`	32	TIM capture/compare register 2
`TIM_CCR2_CCR2`		0:15	Capture/Compare 2 Value
`CCR3`	`0x3C`	32	TIM capture/compare register 3
`TIM_CCR3_CCR3`		0:15	Capture/Compare 3 Value
`CCR4`	`0x40`	32	TIM capture/compare register 4
`TIM_CCR4_CCR4`		0:15	Capture/Compare 4 Value
`BDTR`	`0x44`	32	TIM break and dead-time register
`TIM_BDTR_DTG`		0:7	DTG[0:7] bits (Dead-Time Generator set-up)
`TIM_BDTR_LOCK`		8:9	LOCK[1:0] bits (Lock Configuration)
`TIM_BDTR_OSSI`		10	Off-State Selection for Idle mode
`TIM_BDTR_OSSR`		11	Off-State Selection for Run mode
`TIM_BDTR_BKE`		12	Break enable
`TIM_BDTR_BKP`		13	Break Polarity
`TIM_BDTR_AOE`		14	Automatic Output enable
`TIM_BDTR_MOE`		15	Main Output enable
`DCR`	`0x48`	32	TIM DMA control register
`TIM_DCR_DBA`		0:4	DBA[4:0] bits (DMA Base Address)
`TIM_DCR_DBL`		8:12	DBL[4:0] bits (DMA Burst Length)
`DMAR`	`0x4C`	32	TIM DMA address for full transfer
`TIM_DMAR_DMAB`		0:15	DMA register for burst accesses
`OR`	`0x50`	32	TIM option register
`TIM_OR_TI1_RMP`		0:1	TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap)
`TIM_OR_TI4_RMP`		6:7	TI4_RMP[1:0] bits (TIM5 Input 4 remap)
`TIM_OR_ITR1_RMP`		10:11	ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap)

ADC — ADC (section 14) · STM32F401: present

Register	Offset	Bits	Purpose
`SR`	`0x00`	32	ADC status register
`ADC_SR_AWD`		0	Analog watchdog flag
`ADC_SR_EOC`		1	End of conversion
`ADC_SR_JEOC`		2	Injected channel end of conversion
`ADC_SR_JSTRT`		3	Injected channel Start flag
`ADC_SR_STRT`		4	Regular channel Start flag
`ADC_SR_OVR`		5	Overrun flag
`CR1`	`0x04`	32	ADC control register 1
`ADC_CR1_AWDCH`		0:4	AWDCH[4:0] bits (Analog watchdog channel select bits)
`ADC_CR1_EOCIE`		5	Interrupt enable for EOC
`ADC_CR1_AWDIE`		6	AAnalog Watchdog interrupt enable
`ADC_CR1_JEOCIE`		7	Interrupt enable for injected channels
`ADC_CR1_SCAN`		8	Scan mode
`ADC_CR1_AWDSGL`		9	Enable the watchdog on a single channel in scan mode
`ADC_CR1_JAUTO`		10	Automatic injected group conversion
`ADC_CR1_DISCEN`		11	Discontinuous mode on regular channels
`ADC_CR1_JDISCEN`		12	Discontinuous mode on injected channels
`ADC_CR1_DISCNUM`		13:15	DISCNUM[2:0] bits (Discontinuous mode channel count)
`ADC_CR1_JAWDEN`		22	Analog watchdog enable on injected channels
`ADC_CR1_AWDEN`		23	Analog watchdog enable on regular channels
`ADC_CR1_RES`		24:25	RES[2:0] bits (Resolution)
`ADC_CR1_OVRIE`		26	overrun interrupt enable
`CR2`	`0x08`	32	ADC control register 2
`ADC_CR2_ADON`		0	A/D Converter ON / OFF
`ADC_CR2_CONT`		1	Continuous Conversion
`ADC_CR2_DMA`		8	Direct Memory access mode
`ADC_CR2_DDS`		9	DMA disable selection (Single ADC)
`ADC_CR2_EOCS`		10	End of conversion selection
`ADC_CR2_ALIGN`		11	Data Alignment
`ADC_CR2_JEXTSEL`		16:19	JEXTSEL[3:0] bits (External event select for injected group)
`ADC_CR2_JEXTEN`		20:21	JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp)
`ADC_CR2_JSWSTART`		22	Start Conversion of injected channels
`ADC_CR2_EXTSEL`		24:27	EXTSEL[3:0] bits (External Event Select for regular group)
`ADC_CR2_EXTEN`		28:29	EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp)
`ADC_CR2_SWSTART`		30	Start Conversion of regular channels
`SMPR1`	`0x0C`	32	ADC sample time register 1
`ADC_SMPR1_SMP10`		0:2	SMP10[2:0] bits (Channel 10 Sample time selection)
`ADC_SMPR1_SMP11`		3:5	SMP11[2:0] bits (Channel 11 Sample time selection)
`ADC_SMPR1_SMP12`		6:8	SMP12[2:0] bits (Channel 12 Sample time selection)
`ADC_SMPR1_SMP13`		9:11	SMP13[2:0] bits (Channel 13 Sample time selection)
`ADC_SMPR1_SMP14`		12:14	SMP14[2:0] bits (Channel 14 Sample time selection)
`ADC_SMPR1_SMP15`		15:17	SMP15[2:0] bits (Channel 15 Sample time selection)
`ADC_SMPR1_SMP16`		18:20	SMP16[2:0] bits (Channel 16 Sample time selection)
`ADC_SMPR1_SMP17`		21:23	SMP17[2:0] bits (Channel 17 Sample time selection)
`ADC_SMPR1_SMP18`		24:26	SMP18[2:0] bits (Channel 18 Sample time selection)
`SMPR2`	`0x10`	32	ADC sample time register 2
`ADC_SMPR2_SMP0`		0:2	SMP0[2:0] bits (Channel 0 Sample time selection)
`ADC_SMPR2_SMP1`		3:5	SMP1[2:0] bits (Channel 1 Sample time selection)
`ADC_SMPR2_SMP2`		6:8	SMP2[2:0] bits (Channel 2 Sample time selection)
`ADC_SMPR2_SMP3`		9:11	SMP3[2:0] bits (Channel 3 Sample time selection)
`ADC_SMPR2_SMP4`		12:14	SMP4[2:0] bits (Channel 4 Sample time selection)
`ADC_SMPR2_SMP5`		15:17	SMP5[2:0] bits (Channel 5 Sample time selection)
`ADC_SMPR2_SMP6`		18:20	SMP6[2:0] bits (Channel 6 Sample time selection)
`ADC_SMPR2_SMP7`		21:23	SMP7[2:0] bits (Channel 7 Sample time selection)
`ADC_SMPR2_SMP8`		24:26	SMP8[2:0] bits (Channel 8 Sample time selection)
`ADC_SMPR2_SMP9`		27:29	SMP9[2:0] bits (Channel 9 Sample time selection)
`JOFR1`	`0x14`	32	ADC injected channel data offset register 1
`ADC_JOFR1_JOFFSET1`		0:11	Data offset for injected channel 1
`JOFR2`	`0x18`	32	ADC injected channel data offset register 2
`ADC_JOFR2_JOFFSET2`		0:11	Data offset for injected channel 2
`JOFR3`	`0x1C`	32	ADC injected channel data offset register 3
`ADC_JOFR3_JOFFSET3`		0:11	Data offset for injected channel 3
`JOFR4`	`0x20`	32	ADC injected channel data offset register 4
`ADC_JOFR4_JOFFSET4`		0:11	Data offset for injected channel 4
`HTR`	`0x24`	32	ADC watchdog higher threshold register
`ADC_HTR_HT`		0:11	Analog watchdog high threshold
`LTR`	`0x28`	32	ADC watchdog lower threshold register
`ADC_LTR_LT`		0:11	Analog watchdog low threshold
`SQR1`	`0x2C`	32	ADC regular sequence register 1
`ADC_SQR1_SQ13`		0:4	SQ13[4:0] bits (13th conversion in regular sequence)
`ADC_SQR1_SQ14`		5:9	SQ14[4:0] bits (14th conversion in regular sequence)
`ADC_SQR1_SQ15`		10:14	SQ15[4:0] bits (15th conversion in regular sequence)
`ADC_SQR1_SQ16`		15:19	SQ16[4:0] bits (16th conversion in regular sequence)
`ADC_SQR1_L`		20:23	L[3:0] bits (Regular channel sequence length)
`SQR2`	`0x30`	32	ADC regular sequence register 2
`ADC_SQR2_SQ7`		0:4	SQ7[4:0] bits (7th conversion in regular sequence)
`ADC_SQR2_SQ8`		5:9	SQ8[4:0] bits (8th conversion in regular sequence)
`ADC_SQR2_SQ9`		10:14	SQ9[4:0] bits (9th conversion in regular sequence)
`ADC_SQR2_SQ10`		15:19	SQ10[4:0] bits (10th conversion in regular sequence)
`ADC_SQR2_SQ11`		20:24	SQ11[4:0] bits (11th conversion in regular sequence)
`ADC_SQR2_SQ12`		25:29	SQ12[4:0] bits (12th conversion in regular sequence)
`SQR3`	`0x34`	32	ADC regular sequence register 3
`ADC_SQR3_SQ1`		0:4	SQ1[4:0] bits (1st conversion in regular sequence)
`ADC_SQR3_SQ2`		5:9	SQ2[4:0] bits (2nd conversion in regular sequence)
`ADC_SQR3_SQ3`		10:14	SQ3[4:0] bits (3rd conversion in regular sequence)
`ADC_SQR3_SQ4`		15:19	SQ4[4:0] bits (4th conversion in regular sequence)
`ADC_SQR3_SQ5`		20:24	SQ5[4:0] bits (5th conversion in regular sequence)
`ADC_SQR3_SQ6`		25:29	SQ6[4:0] bits (6th conversion in regular sequence)
`JSQR`	`0x38`	32	ADC injected sequence register
`ADC_JSQR_JSQ1`		0:4	JSQ1[4:0] bits (1st conversion in injected sequence)
`ADC_JSQR_JSQ2`		5:9	JSQ2[4:0] bits (2nd conversion in injected sequence)
`ADC_JSQR_JSQ3`		10:14	JSQ3[4:0] bits (3rd conversion in injected sequence)
`ADC_JSQR_JSQ4`		15:19	JSQ4[4:0] bits (4th conversion in injected sequence)
`ADC_JSQR_JL`		20:21	JL[1:0] bits (Injected Sequence length)
`JDR1`	`0x3C`	32	ADC injected data register 1
`ADC_JDR1_JDATA`		0:15	Injected data
`JDR2`	`0x40`	32	ADC injected data register 2
`ADC_JDR2_JDATA`		0:15	Injected data
`JDR3`	`0x44`	32	ADC injected data register 3
`ADC_JDR3_JDATA`		0:15	Injected data
`JDR4`	`0x48`	32	ADC injected data register 4
`ADC_JDR4_JDATA`		0:15	Injected data
`DR`	`0x4C`	32	ADC regular data register
`ADC_DR_DATA`		0:15	Regular data
`ADC_DR_ADC2DATA`		16:31	ADC2 data

ADC_Common — ADC: registers common to the three units (section 14) · STM32F401: present

Register	Offset	Bits	Purpose
`CSR`	`0x00`	32	ADC Common status register
`ADC_CSR_AWD1`		0	ADC1 Analog watchdog flag
`ADC_CSR_EOC1`		1	ADC1 End of conversion
`ADC_CSR_JEOC1`		2	ADC1 Injected channel end of conversion
`ADC_CSR_JSTRT1`		3	ADC1 Injected channel Start flag
`ADC_CSR_STRT1`		4	ADC1 Regular channel Start flag
`ADC_CSR_OVR1`		5	ADC1 DMA overrun flag
`ADC_CSR_AWD2`		8	ADC2 Analog watchdog flag
`ADC_CSR_EOC2`		9	ADC2 End of conversion
`ADC_CSR_JEOC2`		10	ADC2 Injected channel end of conversion
`ADC_CSR_JSTRT2`		11	ADC2 Injected channel Start flag
`ADC_CSR_STRT2`		12	ADC2 Regular channel Start flag
`ADC_CSR_OVR2`		13	ADC2 DMA overrun flag
`ADC_CSR_AWD3`		16	ADC3 Analog watchdog flag
`ADC_CSR_EOC3`		17	ADC3 End of conversion
`ADC_CSR_JEOC3`		18	ADC3 Injected channel end of conversion
`ADC_CSR_JSTRT3`		19	ADC3 Injected channel Start flag
`ADC_CSR_STRT3`		20	ADC3 Regular channel Start flag
`ADC_CSR_OVR3`		21	ADC3 DMA overrun flag
`CCR`	`0x04`	32	ADC common control register
`ADC_CCR_MULTI`		0:4	MULTI[4:0] bits (Multi-ADC mode selection)
`ADC_CCR_DELAY`		8:11	DELAY[3:0] bits (Delay between 2 sampling phases)
`ADC_CCR_DDS`		13	DMA disable selection (Multi-ADC mode)
`ADC_CCR_DMA`		14:15	DMA[1:0] bits (Direct Memory Access mode for multimode)
`ADC_CCR_ADCPRE`		16:17	ADCPRE[1:0] bits (ADC prescaler)
`ADC_CCR_VBATE`		22	VBAT Enable
`ADC_CCR_TSVREFE`		23	Temperature Sensor and VREFINT Enable
`CDR`	`0x08`	32
`ADC_CDR_DATA1`		0:15	1st data of a pair of regular conversions
`ADC_CDR_DATA2`		16:31	2nd data of a pair of regular conversions

DAC — DAC (section 15) · STM32F401: absent

Register	Offset	Bits	Purpose
`CR`	`0x00`	32	DAC control register
`DAC_CR_EN1`		0	DAC channel1 enable
`DAC_CR_BOFF1`		1	DAC channel1 output buffer disable
`DAC_CR_TEN1`		2	DAC channel1 Trigger enable
`DAC_CR_TSEL1`		3:5	TSEL1[2:0] (DAC channel1 Trigger selection)
`DAC_CR_WAVE1`		6:7	WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
`DAC_CR_MAMP1`		8:11	MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
`DAC_CR_DMAEN1`		12	DAC channel1 DMA enable
`DAC_CR_DMAUDRIE1`		13	DAC channel1 DMA underrun interrupt enable
`DAC_CR_EN2`		16	DAC channel2 enable
`DAC_CR_BOFF2`		17	DAC channel2 output buffer disable
`DAC_CR_TEN2`		18	DAC channel2 Trigger enable
`DAC_CR_TSEL2`		19:21	TSEL2[2:0] (DAC channel2 Trigger selection)
`DAC_CR_WAVE2`		22:23	WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)
`DAC_CR_MAMP2`		24:27	MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)
`DAC_CR_DMAEN2`		28	DAC channel2 DMA enabled
`DAC_CR_DMAUDRIE2`		29	DAC channel2 DMA underrun interrupt enable
`SWTRIGR`	`0x04`	32	DAC software trigger register
`DAC_SWTRIGR_SWTRIG1`		0	DAC channel1 software trigger
`DAC_SWTRIGR_SWTRIG2`		1	DAC channel2 software trigger
`DHR12R1`	`0x08`	32	DAC channel1 12-bit right-aligned data holding register
`DAC_DHR12R1_DACC1DHR`		0:11	DAC channel1 12-bit Right aligned data
`DHR12L1`	`0x0C`	32	DAC channel1 12-bit left aligned data holding register
`DAC_DHR12L1_DACC1DHR`		4:15	DAC channel1 12-bit Left aligned data
`DHR8R1`	`0x10`	32	DAC channel1 8-bit right aligned data holding register
`DAC_DHR8R1_DACC1DHR`		0:7	DAC channel1 8-bit Right aligned data
`DHR12R2`	`0x14`	32	DAC channel2 12-bit right aligned data holding register
`DAC_DHR12R2_DACC2DHR`		0:11	DAC channel2 12-bit Right aligned data
`DHR12L2`	`0x18`	32	DAC channel2 12-bit left aligned data holding register
`DAC_DHR12L2_DACC2DHR`		4:15	DAC channel2 12-bit Left aligned data
`DHR8R2`	`0x1C`	32	DAC channel2 8-bit right-aligned data holding register
`DAC_DHR8R2_DACC2DHR`		0:7	DAC channel2 8-bit Right aligned data
`DHR12RD`	`0x20`	32	Dual DAC 12-bit right-aligned data holding register
`DAC_DHR12RD_DACC1DHR`		0:11	DAC channel1 12-bit Right aligned data
`DAC_DHR12RD_DACC2DHR`		16:27	DAC channel2 12-bit Right aligned data
`DHR12LD`	`0x24`	32	DUAL DAC 12-bit left aligned data holding register
`DAC_DHR12LD_DACC1DHR`		4:15	DAC channel1 12-bit Left aligned data
`DAC_DHR12LD_DACC2DHR`		20:31	DAC channel2 12-bit Left aligned data
`DHR8RD`	`0x28`	32	DUAL DAC 8-bit right aligned data holding register
`DAC_DHR8RD_DACC1DHR`		0:7	DAC channel1 8-bit Right aligned data
`DAC_DHR8RD_DACC2DHR`		8:15	DAC channel2 8-bit Right aligned data
`DOR1`	`0x2C`	32	DAC channel1 data output register
`DAC_DOR1_DACC1DOR`		0:11	DAC channel1 data output
`DOR2`	`0x30`	32	DAC channel2 data output register
`DAC_DOR2_DACC2DOR`		0:11	DAC channel2 data output
`SR`	`0x34`	32	DAC status register
`DAC_SR_DMAUDR1`		13	DAC channel1 DMA underrun flag
`DAC_SR_DMAUDR2`		29	DAC channel2 DMA underrun flag

USART — UART / USART (section 16) · STM32F401: present

Register	Offset	Bits	Purpose
`SR`	`0x00`	32	USART Status register
`USART_SR_PE`		0	Parity Error
`USART_SR_FE`		1	Framing Error
`USART_SR_NE`		2	Noise Error Flag
`USART_SR_ORE`		3	OverRun Error
`USART_SR_IDLE`		4	IDLE line detected
`USART_SR_RXNE`		5	Read Data Register Not Empty
`USART_SR_TC`		6	Transmission Complete
`USART_SR_TXE`		7	Transmit Data Register Empty
`USART_SR_LBD`		8	LIN Break Detection Flag
`USART_SR_CTS`		9	CTS Flag
`DR`	`0x04`	32	USART Data register
`USART_DR_DR`		0:8	Data value
`BRR`	`0x08`	32	USART Baud rate register
`USART_BRR_DIV_Fraction`		0:3	Fraction of USARTDIV
`USART_BRR_DIV_Mantissa`		4:15	Mantissa of USARTDIV
`CR1`	`0x0C`	32	USART Control register 1
`USART_CR1_SBK`		0	Send Break
`USART_CR1_RWU`		1	Receiver wakeup
`USART_CR1_RE`		2	Receiver Enable
`USART_CR1_TE`		3	Transmitter Enable
`USART_CR1_IDLEIE`		4	IDLE Interrupt Enable
`USART_CR1_RXNEIE`		5	RXNE Interrupt Enable
`USART_CR1_TCIE`		6	Transmission Complete Interrupt Enable
`USART_CR1_TXEIE`		7	TXE Interrupt Enable
`USART_CR1_PEIE`		8	PE Interrupt Enable
`USART_CR1_PS`		9	Parity Selection
`USART_CR1_PCE`		10	Parity Control Enable
`USART_CR1_WAKE`		11	Wakeup method
`USART_CR1_M`		12	Word length
`USART_CR1_UE`		13	USART Enable
`USART_CR1_OVER8`		15	USART Oversampling by 8 enable
`CR2`	`0x10`	32	USART Control register 2
`USART_CR2_ADD`		0:3	Address of the USART node
`USART_CR2_LBDL`		5	LIN Break Detection Length
`USART_CR2_LBDIE`		6	LIN Break Detection Interrupt Enable
`USART_CR2_LBCL`		8	Last Bit Clock pulse
`USART_CR2_CPHA`		9	Clock Phase
`USART_CR2_CPOL`		10	Clock Polarity
`USART_CR2_CLKEN`		11	Clock Enable
`USART_CR2_STOP`		12:13	STOP[1:0] bits (STOP bits)
`USART_CR2_LINEN`		14	LIN mode enable
`CR3`	`0x14`	32	USART Control register 3
`USART_CR3_EIE`		0	Error Interrupt Enable
`USART_CR3_IREN`		1	IrDA mode Enable
`USART_CR3_IRLP`		2	IrDA Low-Power
`USART_CR3_HDSEL`		3	Half-Duplex Selection
`USART_CR3_NACK`		4	Smartcard NACK enable
`USART_CR3_SCEN`		5	Smartcard mode enable
`USART_CR3_DMAR`		6	DMA Enable Receiver
`USART_CR3_DMAT`		7	DMA Enable Transmitter
`USART_CR3_RTSE`		8	RTS Enable
`USART_CR3_CTSE`		9	CTS Enable
`USART_CR3_CTSIE`		10	CTS Interrupt Enable
`USART_CR3_ONEBIT`		11	USART One bit method enable
`GTPR`	`0x18`	32	USART Guard time and prescaler register
`USART_GTPR_PSC`		0:7	PSC[7:0] bits (Prescaler value)
`USART_GTPR_GT`		8:15	Guard time value

I2C — I²C (section 17) · STM32F401: present

Register	Offset	Bits	Purpose
`CR1`	`0x00`	32	I2C Control register 1
`I2C_CR1_PE`		0	Peripheral Enable
`I2C_CR1_SMBUS`		1	SMBus Mode
`I2C_CR1_SMBTYPE`		3	SMBus Type
`I2C_CR1_ENARP`		4	ARP Enable
`I2C_CR1_ENPEC`		5	PEC Enable
`I2C_CR1_ENGC`		6	General Call Enable
`I2C_CR1_NOSTRETCH`		7	Clock Stretching Disable (Slave mode)
`I2C_CR1_START`		8	Start Generation
`I2C_CR1_STOP`		9	Stop Generation
`I2C_CR1_ACK`		10	Acknowledge Enable
`I2C_CR1_POS`		11	Acknowledge/PEC Position (for data reception)
`I2C_CR1_PEC`		12	Packet Error Checking
`I2C_CR1_ALERT`		13	SMBus Alert
`I2C_CR1_SWRST`		15	Software Reset
`CR2`	`0x04`	32	I2C Control register 2
`I2C_CR2_FREQ`		0:5	FREQ[5:0] bits (Peripheral Clock Frequency)
`I2C_CR2_ITERREN`		8	Error Interrupt Enable
`I2C_CR2_ITEVTEN`		9	Event Interrupt Enable
`I2C_CR2_ITBUFEN`		10	Buffer Interrupt Enable
`I2C_CR2_DMAEN`		11	DMA Requests Enable
`I2C_CR2_LAST`		12	DMA Last Transfer
`OAR1`	`0x08`	32	I2C Own address register 1
`I2C_OAR1_ADD0`		0	Bit 0
`I2C_OAR1_ADD1`		1	Bit 1
`I2C_OAR1_ADD2`		2	Bit 2
`I2C_OAR1_ADD3`		3	Bit 3
`I2C_OAR1_ADD4`		4	Bit 4
`I2C_OAR1_ADD5`		5	Bit 5
`I2C_OAR1_ADD6`		6	Bit 6
`I2C_OAR1_ADD7`		7	Bit 7
`I2C_OAR1_ADD8`		8	Bit 8
`I2C_OAR1_ADD9`		9	Bit 9
`I2C_OAR1_ADDMODE`		15	Addressing Mode (Slave mode)
`OAR2`	`0x0C`	32	I2C Own address register 2
`I2C_OAR2_ENDUAL`		0	Dual addressing mode enable
`I2C_OAR2_ADD2`		1:7	Interface address
`DR`	`0x10`	32	I2C Data register
`I2C_DR_DR`		0:7	8-bit Data Register
`SR1`	`0x14`	32	I2C Status register 1
`I2C_SR1_SB`		0	Start Bit (Master mode)
`I2C_SR1_ADDR`		1	Address sent (master mode)/matched (slave mode)
`I2C_SR1_BTF`		2	Byte Transfer Finished
`I2C_SR1_ADD10`		3	10-bit header sent (Master mode)
`I2C_SR1_STOPF`		4	Stop detection (Slave mode)
`I2C_SR1_RXNE`		6	Data Register not Empty (receivers)
`I2C_SR1_TXE`		7	Data Register Empty (transmitters)
`I2C_SR1_BERR`		8	Bus Error
`I2C_SR1_ARLO`		9	Arbitration Lost (master mode)
`I2C_SR1_AF`		10	Acknowledge Failure
`I2C_SR1_OVR`		11	Overrun/Underrun
`I2C_SR1_PECERR`		12	PEC Error in reception
`I2C_SR1_TIMEOUT`		14	Timeout or Tlow Error
`I2C_SR1_SMBALERT`		15	SMBus Alert
`SR2`	`0x18`	32	I2C Status register 2
`I2C_SR2_MSL`		0	Master/Slave
`I2C_SR2_BUSY`		1	Bus Busy
`I2C_SR2_TRA`		2	Transmitter/Receiver
`I2C_SR2_GENCALL`		4	General Call Address (Slave mode)
`I2C_SR2_SMBDEFAULT`		5	SMBus Device Default Address (Slave mode)
`I2C_SR2_SMBHOST`		6	SMBus Host Header (Slave mode)
`I2C_SR2_DUALF`		7	Dual Flag (Slave mode)
`I2C_SR2_PEC`		8:15	Packet Error Checking Register
`CCR`	`0x1C`	32	I2C Clock control register
`I2C_CCR_CCR`		0:11	Clock Control Register in Fast/Standard mode (Master mode)
`I2C_CCR_DUTY`		14	Fast Mode Duty Cycle
`I2C_CCR_FS`		15	I2C Master Mode Selection
`TRISE`	`0x20`	32	I2C TRISE register
`I2C_TRISE_TRISE`		0:5	Maximum Rise Time in Fast/Standard mode (Master mode)

SPI — SPI / I²S (section 18) · STM32F401: present

Register	Offset	Bits	Purpose
`CR1`	`0x00`	32	SPI control register 1 (not used in I2S mode)
`SPI_CR1_CPHA`		0	Clock Phase
`SPI_CR1_CPOL`		1	Clock Polarity
`SPI_CR1_MSTR`		2	Master Selection
`SPI_CR1_BR`		3:5	BR[2:0] bits (Baud Rate Control)
`SPI_CR1_SPE`		6	SPI Enable
`SPI_CR1_LSBFIRST`		7	Frame Format
`SPI_CR1_SSI`		8	Internal slave select
`SPI_CR1_SSM`		9	Software slave management
`SPI_CR1_RXONLY`		10	Receive only
`SPI_CR1_DFF`		11	Data Frame Format
`SPI_CR1_CRCNEXT`		12	Transmit CRC next
`SPI_CR1_CRCEN`		13	Hardware CRC calculation enable
`SPI_CR1_BIDIOE`		14	Output enable in bidirectional mode
`SPI_CR1_BIDIMODE`		15	Bidirectional data mode enable
`CR2`	`0x04`	32	SPI control register 2
`SPI_CR2_RXDMAEN`		0	Rx Buffer DMA Enable
`SPI_CR2_TXDMAEN`		1	Tx Buffer DMA Enable
`SPI_CR2_SSOE`		2	SS Output Enable
`SPI_CR2_FRF`		4	Frame Format
`SPI_CR2_ERRIE`		5	Error Interrupt Enable
`SPI_CR2_RXNEIE`		6	RX buffer Not Empty Interrupt Enable
`SPI_CR2_TXEIE`		7	Tx buffer Empty Interrupt Enable
`SR`	`0x08`	32	SPI status register
`SPI_SR_RXNE`		0	Receive buffer Not Empty
`SPI_SR_TXE`		1	Transmit buffer Empty
`SPI_SR_CHSIDE`		2	Channel side
`SPI_SR_UDR`		3	Underrun flag
`SPI_SR_CRCERR`		4	CRC Error flag
`SPI_SR_MODF`		5	Mode fault
`SPI_SR_OVR`		6	Overrun flag
`SPI_SR_BSY`		7	Busy flag
`SPI_SR_FRE`		8	Frame format error flag
`DR`	`0x0C`	32	SPI data register
`SPI_DR_DR`		0:15	Data Register
`CRCPR`	`0x10`	32	SPI CRC polynomial register (not used in I2S mode)
`SPI_CRCPR_CRCPOLY`		0:15	CRC polynomial register
`RXCRCR`	`0x14`	32	SPI RX CRC register (not used in I2S mode)
`SPI_RXCRCR_RXCRC`		0:15	Rx CRC Register
`TXCRCR`	`0x18`	32	SPI TX CRC register (not used in I2S mode)
`SPI_TXCRCR_TXCRC`		0:15	Tx CRC Register
`I2SCFGR`	`0x1C`	32	SPI_I2S configuration register
`SPI_I2SCFGR_CHLEN`		0	Channel length (number of bits per audio channel)
`SPI_I2SCFGR_DATLEN`		1:2	DATLEN[1:0] bits (Data length to be transferred)
`SPI_I2SCFGR_CKPOL`		3	steady state clock polarity
`SPI_I2SCFGR_I2SSTD`		4:5	I2SSTD[1:0] bits (I2S standard selection)
`SPI_I2SCFGR_PCMSYNC`		7	PCM frame synchronization
`SPI_I2SCFGR_I2SCFG`		8:9	I2SCFG[1:0] bits (I2S configuration mode)
`SPI_I2SCFGR_I2SE`		10	I2S Enable
`SPI_I2SCFGR_I2SMOD`		11	I2S mode selection
`I2SPR`	`0x20`	32	SPI_I2S prescaler register
`SPI_I2SPR_I2SDIV`		0:7	I2S Linear prescaler
`SPI_I2SPR_ODD`		8	Odd factor for the prescaler
`SPI_I2SPR_MCKOE`		9	Master Clock Output Enable

CAN — CAN (section 19) · STM32F401: absent

Register	Offset	Bits	Purpose
`MCR`	`0x00`	32	CAN master control register
`CAN_MCR_INRQ`		0	Initialization Request
`CAN_MCR_SLEEP`		1	Sleep Mode Request
`CAN_MCR_TXFP`		2	Transmit FIFO Priority
`CAN_MCR_RFLM`		3	Receive FIFO Locked Mode
`CAN_MCR_NART`		4	No Automatic Retransmission
`CAN_MCR_AWUM`		5	Automatic Wakeup Mode
`CAN_MCR_ABOM`		6	Automatic Bus-Off Management
`CAN_MCR_TTCM`		7	Time Triggered Communication Mode
`CAN_MCR_RESET`		15	bxCAN software master reset
`CAN_MCR_DBF`		16	bxCAN Debug freeze
`MSR`	`0x04`	32	CAN master status register
`CAN_MSR_INAK`		0	Initialization Acknowledge
`CAN_MSR_SLAK`		1	Sleep Acknowledge
`CAN_MSR_ERRI`		2	Error Interrupt
`CAN_MSR_WKUI`		3	Wakeup Interrupt
`CAN_MSR_SLAKI`		4	Sleep Acknowledge Interrupt
`CAN_MSR_TXM`		8	Transmit Mode
`CAN_MSR_RXM`		9	Receive Mode
`CAN_MSR_SAMP`		10	Last Sample Point
`CAN_MSR_RX`		11	CAN Rx Signal
`TSR`	`0x08`	32	CAN transmit status register
`CAN_TSR_RQCP0`		0	Request Completed Mailbox0
`CAN_TSR_TXOK0`		1	Transmission OK of Mailbox0
`CAN_TSR_ALST0`		2	Arbitration Lost for Mailbox0
`CAN_TSR_TERR0`		3	Transmission Error of Mailbox0
`CAN_TSR_ABRQ0`		7	Abort Request for Mailbox0
`CAN_TSR_RQCP1`		8	Request Completed Mailbox1
`CAN_TSR_TXOK1`		9	Transmission OK of Mailbox1
`CAN_TSR_ALST1`		10	Arbitration Lost for Mailbox1
`CAN_TSR_TERR1`		11	Transmission Error of Mailbox1
`CAN_TSR_ABRQ1`		15	Abort Request for Mailbox 1
`CAN_TSR_RQCP2`		16	Request Completed Mailbox2
`CAN_TSR_TXOK2`		17	Transmission OK of Mailbox 2
`CAN_TSR_ALST2`		18	Arbitration Lost for mailbox 2
`CAN_TSR_TERR2`		19	Transmission Error of Mailbox 2
`CAN_TSR_ABRQ2`		23	Abort Request for Mailbox 2
`CAN_TSR_CODE`		24:25	Mailbox Code
`CAN_TSR_TME`		26:28	TME[2:0] bits
`CAN_TSR_TME0`		26	Transmit Mailbox 0 Empty
`CAN_TSR_TME1`		27	Transmit Mailbox 1 Empty
`CAN_TSR_TME2`		28	Transmit Mailbox 2 Empty
`CAN_TSR_LOW`		29:31	LOW[2:0] bits
`CAN_TSR_LOW0`		29	Lowest Priority Flag for Mailbox 0
`CAN_TSR_LOW1`		30	Lowest Priority Flag for Mailbox 1
`CAN_TSR_LOW2`		31	Lowest Priority Flag for Mailbox 2
`RF0R`	`0x0C`	32	CAN receive FIFO 0 register
`CAN_RF0R_FMP0`		0:1	FIFO 0 Message Pending
`CAN_RF0R_FULL0`		3	FIFO 0 Full
`CAN_RF0R_FOVR0`		4	FIFO 0 Overrun
`CAN_RF0R_RFOM0`		5	Release FIFO 0 Output Mailbox
`RF1R`	`0x10`	32	CAN receive FIFO 1 register
`CAN_RF1R_FMP1`		0:1	FIFO 1 Message Pending
`CAN_RF1R_FULL1`		3	FIFO 1 Full
`CAN_RF1R_FOVR1`		4	FIFO 1 Overrun
`CAN_RF1R_RFOM1`		5	Release FIFO 1 Output Mailbox
`IER`	`0x14`	32	CAN interrupt enable register
`CAN_IER_TMEIE`		0	Transmit Mailbox Empty Interrupt Enable
`CAN_IER_FMPIE0`		1	FIFO Message Pending Interrupt Enable
`CAN_IER_FFIE0`		2	FIFO Full Interrupt Enable
`CAN_IER_FOVIE0`		3	FIFO Overrun Interrupt Enable
`CAN_IER_FMPIE1`		4	FIFO Message Pending Interrupt Enable
`CAN_IER_FFIE1`		5	FIFO Full Interrupt Enable
`CAN_IER_FOVIE1`		6	FIFO Overrun Interrupt Enable
`CAN_IER_EWGIE`		8	Error Warning Interrupt Enable
`CAN_IER_EPVIE`		9	Error Passive Interrupt Enable
`CAN_IER_BOFIE`		10	Bus-Off Interrupt Enable
`CAN_IER_LECIE`		11	Last Error Code Interrupt Enable
`CAN_IER_ERRIE`		15	Error Interrupt Enable
`CAN_IER_WKUIE`		16	Wakeup Interrupt Enable
`CAN_IER_SLKIE`		17	Sleep Interrupt Enable
`ESR`	`0x18`	32	CAN error status register
`CAN_ESR_EWGF`		0	Error Warning Flag
`CAN_ESR_EPVF`		1	Error Passive Flag
`CAN_ESR_BOFF`		2	Bus-Off Flag
`CAN_ESR_LEC`		4:6	LEC[2:0] bits (Last Error Code)
`CAN_ESR_TEC`		16:23	Least significant byte of the 9-bit Transmit Error Counter
`CAN_ESR_REC`		24:31	Receive Error Counter
`BTR`	`0x1C`	32	CAN bit timing register
`CAN_BTR_BRP`		0:9	Baud Rate Prescaler
`CAN_BTR_TS1`		16:19	Time Segment 1
`CAN_BTR_TS2`		20:22	Time Segment 2
`CAN_BTR_SJW`		24:25	Resynchronization Jump Width
`CAN_BTR_LBKM`		30	Loop Back Mode (Debug)
`CAN_BTR_SILM`		31	Silent Mode
`FMR`	`0x200`	32	CAN filter master register
`CAN_FMR_FINIT`		0	Filter Init Mode
`CAN_FMR_CAN2SB`		8:13	CAN2 start bank
`FM1R`	`0x204`	32	CAN filter mode register
`CAN_FM1R_FBM`		0:27	Filter Mode
`CAN_FM1R_FBM0`		0	Filter Init Mode bit 0
`CAN_FM1R_FBM1`		1	Filter Init Mode bit 1
`CAN_FM1R_FBM2`		2	Filter Init Mode bit 2
`CAN_FM1R_FBM3`		3	Filter Init Mode bit 3
`CAN_FM1R_FBM4`		4	Filter Init Mode bit 4
`CAN_FM1R_FBM5`		5	Filter Init Mode bit 5
`CAN_FM1R_FBM6`		6	Filter Init Mode bit 6
`CAN_FM1R_FBM7`		7	Filter Init Mode bit 7
`CAN_FM1R_FBM8`		8	Filter Init Mode bit 8
`CAN_FM1R_FBM9`		9	Filter Init Mode bit 9
`CAN_FM1R_FBM10`		10	Filter Init Mode bit 10
`CAN_FM1R_FBM11`		11	Filter Init Mode bit 11
`CAN_FM1R_FBM12`		12	Filter Init Mode bit 12
`CAN_FM1R_FBM13`		13	Filter Init Mode bit 13
`CAN_FM1R_FBM14`		14	Filter Init Mode bit 14
`CAN_FM1R_FBM15`		15	Filter Init Mode bit 15
`CAN_FM1R_FBM16`		16	Filter Init Mode bit 16
`CAN_FM1R_FBM17`		17	Filter Init Mode bit 17
`CAN_FM1R_FBM18`		18	Filter Init Mode bit 18
`CAN_FM1R_FBM19`		19	Filter Init Mode bit 19
`CAN_FM1R_FBM20`		20	Filter Init Mode bit 20
`CAN_FM1R_FBM21`		21	Filter Init Mode bit 21
`CAN_FM1R_FBM22`		22	Filter Init Mode bit 22
`CAN_FM1R_FBM23`		23	Filter Init Mode bit 23
`CAN_FM1R_FBM24`		24	Filter Init Mode bit 24
`CAN_FM1R_FBM25`		25	Filter Init Mode bit 25
`CAN_FM1R_FBM26`		26	Filter Init Mode bit 26
`CAN_FM1R_FBM27`		27	Filter Init Mode bit 27
`FS1R`	`0x20C`	32	CAN filter scale register
`CAN_FS1R_FSC`		0:27	Filter Scale Configuration
`CAN_FS1R_FSC0`		0	Filter Scale Configuration bit 0
`CAN_FS1R_FSC1`		1	Filter Scale Configuration bit 1
`CAN_FS1R_FSC2`		2	Filter Scale Configuration bit 2
`CAN_FS1R_FSC3`		3	Filter Scale Configuration bit 3
`CAN_FS1R_FSC4`		4	Filter Scale Configuration bit 4
`CAN_FS1R_FSC5`		5	Filter Scale Configuration bit 5
`CAN_FS1R_FSC6`		6	Filter Scale Configuration bit 6
`CAN_FS1R_FSC7`		7	Filter Scale Configuration bit 7
`CAN_FS1R_FSC8`		8	Filter Scale Configuration bit 8
`CAN_FS1R_FSC9`		9	Filter Scale Configuration bit 9
`CAN_FS1R_FSC10`		10	Filter Scale Configuration bit 10
`CAN_FS1R_FSC11`		11	Filter Scale Configuration bit 11
`CAN_FS1R_FSC12`		12	Filter Scale Configuration bit 12
`CAN_FS1R_FSC13`		13	Filter Scale Configuration bit 13
`CAN_FS1R_FSC14`		14	Filter Scale Configuration bit 14
`CAN_FS1R_FSC15`		15	Filter Scale Configuration bit 15
`CAN_FS1R_FSC16`		16	Filter Scale Configuration bit 16
`CAN_FS1R_FSC17`		17	Filter Scale Configuration bit 17
`CAN_FS1R_FSC18`		18	Filter Scale Configuration bit 18
`CAN_FS1R_FSC19`		19	Filter Scale Configuration bit 19
`CAN_FS1R_FSC20`		20	Filter Scale Configuration bit 20
`CAN_FS1R_FSC21`		21	Filter Scale Configuration bit 21
`CAN_FS1R_FSC22`		22	Filter Scale Configuration bit 22
`CAN_FS1R_FSC23`		23	Filter Scale Configuration bit 23
`CAN_FS1R_FSC24`		24	Filter Scale Configuration bit 24
`CAN_FS1R_FSC25`		25	Filter Scale Configuration bit 25
`CAN_FS1R_FSC26`		26	Filter Scale Configuration bit 26
`CAN_FS1R_FSC27`		27	Filter Scale Configuration bit 27
`FFA1R`	`0x214`	32	CAN filter FIFO assignment register
`CAN_FFA1R_FFA`		0:27	Filter FIFO Assignment
`CAN_FFA1R_FFA0`		0	Filter FIFO Assignment bit 0
`CAN_FFA1R_FFA1`		1	Filter FIFO Assignment bit 1
`CAN_FFA1R_FFA2`		2	Filter FIFO Assignment bit 2
`CAN_FFA1R_FFA3`		3	Filter FIFO Assignment bit 3
`CAN_FFA1R_FFA4`		4	Filter FIFO Assignment bit 4
`CAN_FFA1R_FFA5`		5	Filter FIFO Assignment bit 5
`CAN_FFA1R_FFA6`		6	Filter FIFO Assignment bit 6
`CAN_FFA1R_FFA7`		7	Filter FIFO Assignment bit 7
`CAN_FFA1R_FFA8`		8	Filter FIFO Assignment bit 8
`CAN_FFA1R_FFA9`		9	Filter FIFO Assignment bit 9
`CAN_FFA1R_FFA10`		10	Filter FIFO Assignment bit 10
`CAN_FFA1R_FFA11`		11	Filter FIFO Assignment bit 11
`CAN_FFA1R_FFA12`		12	Filter FIFO Assignment bit 12
`CAN_FFA1R_FFA13`		13	Filter FIFO Assignment bit 13
`CAN_FFA1R_FFA14`		14	Filter FIFO Assignment bit 14
`CAN_FFA1R_FFA15`		15	Filter FIFO Assignment bit 15
`CAN_FFA1R_FFA16`		16	Filter FIFO Assignment bit 16
`CAN_FFA1R_FFA17`		17	Filter FIFO Assignment bit 17
`CAN_FFA1R_FFA18`		18	Filter FIFO Assignment bit 18
`CAN_FFA1R_FFA19`		19	Filter FIFO Assignment bit 19
`CAN_FFA1R_FFA20`		20	Filter FIFO Assignment bit 20
`CAN_FFA1R_FFA21`		21	Filter FIFO Assignment bit 21
`CAN_FFA1R_FFA22`		22	Filter FIFO Assignment bit 22
`CAN_FFA1R_FFA23`		23	Filter FIFO Assignment bit 23
`CAN_FFA1R_FFA24`		24	Filter FIFO Assignment bit 24
`CAN_FFA1R_FFA25`		25	Filter FIFO Assignment bit 25
`CAN_FFA1R_FFA26`		26	Filter FIFO Assignment bit 26
`CAN_FFA1R_FFA27`		27	Filter FIFO Assignment bit 27
`FA1R`	`0x21C`	32	CAN filter activation register
`CAN_FA1R_FACT`		0:27	Filter Active
`CAN_FA1R_FACT0`		0	Filter Active bit 0
`CAN_FA1R_FACT1`		1	Filter Active bit 1
`CAN_FA1R_FACT2`		2	Filter Active bit 2
`CAN_FA1R_FACT3`		3	Filter Active bit 3
`CAN_FA1R_FACT4`		4	Filter Active bit 4
`CAN_FA1R_FACT5`		5	Filter Active bit 5
`CAN_FA1R_FACT6`		6	Filter Active bit 6
`CAN_FA1R_FACT7`		7	Filter Active bit 7
`CAN_FA1R_FACT8`		8	Filter Active bit 8
`CAN_FA1R_FACT9`		9	Filter Active bit 9
`CAN_FA1R_FACT10`		10	Filter Active bit 10
`CAN_FA1R_FACT11`		11	Filter Active bit 11
`CAN_FA1R_FACT12`		12	Filter Active bit 12
`CAN_FA1R_FACT13`		13	Filter Active bit 13
`CAN_FA1R_FACT14`		14	Filter Active bit 14
`CAN_FA1R_FACT15`		15	Filter Active bit 15
`CAN_FA1R_FACT16`		16	Filter Active bit 16
`CAN_FA1R_FACT17`		17	Filter Active bit 17
`CAN_FA1R_FACT18`		18	Filter Active bit 18
`CAN_FA1R_FACT19`		19	Filter Active bit 19
`CAN_FA1R_FACT20`		20	Filter Active bit 20
`CAN_FA1R_FACT21`		21	Filter Active bit 21
`CAN_FA1R_FACT22`		22	Filter Active bit 22
`CAN_FA1R_FACT23`		23	Filter Active bit 23
`CAN_FA1R_FACT24`		24	Filter Active bit 24
`CAN_FA1R_FACT25`		25	Filter Active bit 25
`CAN_FA1R_FACT26`		26	Filter Active bit 26
`CAN_FA1R_FACT27`		27	Filter Active bit 27

USB_OTG — USB OTG: global registers (section 20) · STM32F401: present

Register	Offset	Bits	Purpose
`GOTGCTL`	`0x00`	32	USB_OTG Control and Status Register 000h
`USB_OTG_GOTGCTL_SRQSCS`		0	Session request success
`USB_OTG_GOTGCTL_SRQ`		1	Session request
`USB_OTG_GOTGCTL_HNGSCS`		8	Host set HNP enable
`USB_OTG_GOTGCTL_HNPRQ`		9	HNP request
`USB_OTG_GOTGCTL_HSHNPEN`		10	Host set HNP enable
`USB_OTG_GOTGCTL_DHNPEN`		11	Device HNP enabled
`USB_OTG_GOTGCTL_CIDSTS`		16	Connector ID status
`USB_OTG_GOTGCTL_DBCT`		17	Long/short debounce time
`USB_OTG_GOTGCTL_ASVLD`		18	A-session valid
`USB_OTG_GOTGCTL_BSVLD`		19	B-session valid
`GOTGINT`	`0x04`	32	USB_OTG Interrupt Register 004h
`USB_OTG_GOTGINT_SEDET`		2	Session end detected
`USB_OTG_GOTGINT_SRSSCHG`		8	Session request success status change
`USB_OTG_GOTGINT_HNSSCHG`		9	Host negotiation success status change
`USB_OTG_GOTGINT_HNGDET`		17	Host negotiation detected
`USB_OTG_GOTGINT_ADTOCHG`		18	A-device timeout change
`USB_OTG_GOTGINT_DBCDNE`		19	Debounce done
`GAHBCFG`	`0x08`	32	Core AHB Configuration Register 008h
`USB_OTG_GAHBCFG_GINT`		0	Global interrupt mask
`USB_OTG_GAHBCFG_HBSTLEN`		1:4	Burst length/type
`USB_OTG_GAHBCFG_DMAEN`		5	DMA enable
`USB_OTG_GAHBCFG_TXFELVL`		7	TxFIFO empty level
`USB_OTG_GAHBCFG_PTXFELVL`		8	Periodic TxFIFO empty level
`GUSBCFG`	`0x0C`	32	Core USB Configuration Register 00Ch
`USB_OTG_GUSBCFG_TOCAL`		0:2	FS timeout calibration
`USB_OTG_GUSBCFG_PHYSEL`		6	USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
`USB_OTG_GUSBCFG_SRPCAP`		8	SRP-capable
`USB_OTG_GUSBCFG_HNPCAP`		9	HNP-capable
`USB_OTG_GUSBCFG_TRDT`		10:13	USB turnaround time
`USB_OTG_GUSBCFG_PHYLPCS`		15	PHY Low-power clock select
`USB_OTG_GUSBCFG_ULPIFSLS`		17	ULPI FS/LS select
`USB_OTG_GUSBCFG_ULPIAR`		18	ULPI Auto-resume
`USB_OTG_GUSBCFG_ULPICSM`		19	ULPI Clock SuspendM
`USB_OTG_GUSBCFG_ULPIEVBUSD`		20	ULPI External VBUS Drive
`USB_OTG_GUSBCFG_ULPIEVBUSI`		21	ULPI external VBUS indicator
`USB_OTG_GUSBCFG_TSDPS`		22	TermSel DLine pulsing selection
`USB_OTG_GUSBCFG_PCCI`		23	Indicator complement
`USB_OTG_GUSBCFG_PTCI`		24	Indicator pass through
`USB_OTG_GUSBCFG_ULPIIPD`		25	ULPI interface protect disable
`USB_OTG_GUSBCFG_FHMOD`		29	Forced host mode
`USB_OTG_GUSBCFG_FDMOD`		30	Forced peripheral mode
`USB_OTG_GUSBCFG_CTXPKT`		31	Corrupt Tx packet
`GRSTCTL`	`0x10`	32	Core Reset Register 010h
`USB_OTG_GRSTCTL_CSRST`		0	Core soft reset
`USB_OTG_GRSTCTL_HSRST`		1	HCLK soft reset
`USB_OTG_GRSTCTL_FCRST`		2	Host frame counter reset
`USB_OTG_GRSTCTL_RXFFLSH`		4	RxFIFO flush
`USB_OTG_GRSTCTL_TXFFLSH`		5	TxFIFO flush
`USB_OTG_GRSTCTL_TXFNUM`		6:10	TxFIFO number
`USB_OTG_GRSTCTL_DMAREQ`		30	DMA request signal
`USB_OTG_GRSTCTL_AHBIDL`		31	AHB master idle
`GINTSTS`	`0x14`	32	Core Interrupt Register 014h
`USB_OTG_GINTSTS_CMOD`		0	Current mode of operation
`USB_OTG_GINTSTS_MMIS`		1	Mode mismatch interrupt
`USB_OTG_GINTSTS_OTGINT`		2	OTG interrupt
`USB_OTG_GINTSTS_SOF`		3	Start of frame
`USB_OTG_GINTSTS_RXFLVL`		4	RxFIFO nonempty
`USB_OTG_GINTSTS_NPTXFE`		5	Nonperiodic TxFIFO empty
`USB_OTG_GINTSTS_GINAKEFF`		6	Global IN nonperiodic NAK effective
`USB_OTG_GINTSTS_BOUTNAKEFF`		7	Global OUT NAK effective
`USB_OTG_GINTSTS_ESUSP`		10	Early suspend
`USB_OTG_GINTSTS_USBSUSP`		11	USB suspend
`USB_OTG_GINTSTS_USBRST`		12	USB reset
`USB_OTG_GINTSTS_ENUMDNE`		13	Enumeration done
`USB_OTG_GINTSTS_ISOODRP`		14	Isochronous OUT packet dropped interrupt
`USB_OTG_GINTSTS_EOPF`		15	End of periodic frame interrupt
`USB_OTG_GINTSTS_IEPINT`		18	IN endpoint interrupt
`USB_OTG_GINTSTS_OEPINT`		19	OUT endpoint interrupt
`USB_OTG_GINTSTS_IISOIXFR`		20	Incomplete isochronous IN transfer
`USB_OTG_GINTSTS_PXFR_INCOMPISOOUT`		21	Incomplete periodic transfer
`USB_OTG_GINTSTS_DATAFSUSP`		22	Data fetch suspended
`USB_OTG_GINTSTS_HPRTINT`		24	Host port interrupt
`USB_OTG_GINTSTS_HCINT`		25	Host channels interrupt
`USB_OTG_GINTSTS_PTXFE`		26	Periodic TxFIFO empty
`USB_OTG_GINTSTS_CIDSCHG`		28	Connector ID status change
`USB_OTG_GINTSTS_DISCINT`		29	Disconnect detected interrupt
`USB_OTG_GINTSTS_SRQINT`		30	Session request/new session detected interrupt
`USB_OTG_GINTSTS_WKUINT`		31	Resume/remote wakeup detected interrupt
`GINTMSK`	`0x18`	32	Core Interrupt Mask Register 018h
`USB_OTG_GINTMSK_MMISM`		1	Mode mismatch interrupt mask
`USB_OTG_GINTMSK_OTGINT`		2	OTG interrupt mask
`USB_OTG_GINTMSK_SOFM`		3	Start of frame mask
`USB_OTG_GINTMSK_RXFLVLM`		4	Receive FIFO nonempty mask
`USB_OTG_GINTMSK_NPTXFEM`		5	Nonperiodic TxFIFO empty mask
`USB_OTG_GINTMSK_GINAKEFFM`		6	Global nonperiodic IN NAK effective mask
`USB_OTG_GINTMSK_GONAKEFFM`		7	Global OUT NAK effective mask
`USB_OTG_GINTMSK_ESUSPM`		10	Early suspend mask
`USB_OTG_GINTMSK_USBSUSPM`		11	USB suspend mask
`USB_OTG_GINTMSK_USBRST`		12	USB reset mask
`USB_OTG_GINTMSK_ENUMDNEM`		13	Enumeration done mask
`USB_OTG_GINTMSK_ISOODRPM`		14	Isochronous OUT packet dropped interrupt mask
`USB_OTG_GINTMSK_EOPFM`		15	End of periodic frame interrupt mask
`USB_OTG_GINTMSK_EPMISM`		17	Endpoint mismatch interrupt mask
`USB_OTG_GINTMSK_IEPINT`		18	IN endpoints interrupt mask
`USB_OTG_GINTMSK_OEPINT`		19	OUT endpoints interrupt mask
`USB_OTG_GINTMSK_IISOIXFRM`		20	Incomplete isochronous IN transfer mask
`USB_OTG_GINTMSK_PXFRM_IISOOXFRM`		21	Incomplete periodic transfer mask
`USB_OTG_GINTMSK_FSUSPM`		22	Data fetch suspended mask
`USB_OTG_GINTMSK_PRTIM`		24	Host port interrupt mask
`USB_OTG_GINTMSK_HCIM`		25	Host channels interrupt mask
`USB_OTG_GINTMSK_PTXFEM`		26	Periodic TxFIFO empty mask
`USB_OTG_GINTMSK_CIDSCHGM`		28	Connector ID status change mask
`USB_OTG_GINTMSK_DISCINT`		29	Disconnect detected interrupt mask
`USB_OTG_GINTMSK_SRQIM`		30	Session request/new session detected interrupt mask
`USB_OTG_GINTMSK_WUIM`		31	Resume/remote wakeup detected interrupt mask
`GRXSTSR`	`0x1C`	32	Receive Sts Q Read Register 01Ch
`GRXSTSP`	`0x20`	32	Receive Sts Q Read & POP Register 020h
`USB_OTG_GRXSTSP_EPNUM`		0:3	IN EP interrupt mask bits
`USB_OTG_GRXSTSP_BCNT`		4:14	OUT EP interrupt mask bits
`USB_OTG_GRXSTSP_DPID`		15:16	OUT EP interrupt mask bits
`USB_OTG_GRXSTSP_PKTSTS`		17:20	OUT EP interrupt mask bits
`GRXFSIZ`	`0x24`	32	Receive FIFO Size Register 024h
`USB_OTG_GRXFSIZ_RXFD`		0:15	RxFIFO depth
`DIEPTXF0_HNPTXFSIZ`	`0x28`	32	EP0 / Non Periodic Tx FIFO Size Register 028h
`HNPTXSTS`	`0x2C`	32	Non Periodic Tx FIFO/Queue Sts reg 02Ch
`GCCFG`	`0x38`	32	General Purpose IO Register 038h
`USB_OTG_GCCFG_PWRDWN`		16	Power down
`USB_OTG_GCCFG_I2CPADEN`		17	Enable I2C bus connection for the external I2C PHY interface
`USB_OTG_GCCFG_VBUSASEN`		18	Enable the VBUS sensing device
`USB_OTG_GCCFG_VBUSBSEN`		19	Enable the VBUS sensing device
`USB_OTG_GCCFG_SOFOUTEN`		20	SOF output enable
`USB_OTG_GCCFG_NOVBUSSENS`		21	VBUS sensing disable option
`CID`	`0x3C`	32	User ID Register 03Ch
`USB_OTG_CID_PRODUCT_ID`		0:31	Product ID field
`HPTXFSIZ`	`0x100`	32	Host Periodic Tx FIFO Size Reg 100h
`USB_OTG_HPTXFSIZ_PTXSA`		0:15	Host periodic TxFIFO start address
`USB_OTG_HPTXFSIZ_PTXFD`		16:31	Host periodic TxFIFO depth

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