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STM32WLE5 · уровень справочник · 81 мин чтения
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Приложение A18. Карты регистров STM32WL

Серия STM32WL: Cortex-M4 с радио LoRa на кристалле (раздел 93). Регистры и биты основных блоков — из заголовка STM32WLE5, тем же генератором, что карты F1 и F4: смещения — по структурам *_TypeDef, назначение регистра и описание бита — из комментариев заголовка. Блоки, которых в серии нет, опущены. Для малого потребления смотрите PWR (режимы сна), RCC (генераторы LSE/LSI/MSI), LPTIM и LPUART — они работают во сне. Разделы справочника написаны для F103 и F407; имена регистров и битов у серий в основном те же — карта помогает перенести код и увидеть, что устроено иначе.

Как читать: смещение — от базового адреса блока; 31:16 — поле битов с 16 по 31; одно число — отдельный бит. Цифра в скобках у заголовка блока — раздел, где блок разобран.

Периферия STM32WLE5 по шинам: базы шин и смещения блоков приложения, как в окне отладчика

RCC — Тактирование (раздел 6)

Регистр Смещение Бит Назначение
CR 0x00 32 RCC clock Control Register
RCC_CR_MSION 0 Internal Multi Speed oscillator (MSI) clock enable
RCC_CR_MSIRDY 1 Internal Multi Speed oscillator (MSI) clock ready flag
RCC_CR_MSIPLLEN 2 Internal Multi Speed oscillator (MSI) PLL enable
RCC_CR_MSIRGSEL 3 Internal Multi Speed oscillator (MSI) range selection
RCC_CR_MSIRANGE 4:7 Internal Multi Speed oscillator (MSI) clock Range
RCC_CR_HSION 8 Internal High Speed oscillator (HSI16) clock enable
RCC_CR_HSIKERON 9 Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel
RCC_CR_HSIRDY 10 Internal High Speed oscillator (HSI16) clock ready flag
RCC_CR_HSIASFS 11 HSI16 Automatic Start from Stop
RCC_CR_HSIKERDY 12 Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel ready flag
RCC_CR_HSEON 16 External High Speed oscillator (HSE) clock enable
RCC_CR_HSERDY 17 External High Speed oscillator (HSE) clock ready
RCC_CR_CSSON 19 HSE Clock Security System enable
RCC_CR_HSEPRE 20 HSE sysclk prescaler
RCC_CR_HSEBYPPWR 21 Enable HSE32 VDDTCXO
RCC_CR_PLLON 24 System PLL clock enable
RCC_CR_PLLRDY 25 System PLL clock ready
ICSCR 0x04 32 RCC Internal Clock Sources Calibration Register
RCC_ICSCR_MSICAL 0:7 MSICAL[7:0] bits
RCC_ICSCR_MSITRIM 8:15 MSITRIM[7:0] bits
RCC_ICSCR_HSICAL 16:23 HSICAL[7:0] bits
RCC_ICSCR_HSITRIM 24:30 HSITRIM[6:0] bits
CFGR 0x08 32 RCC Clocks Configuration Register
RCC_CFGR_SW 0:1 SW[1:0] bits (System clock Switch)
RCC_CFGR_SWS 2:3 SWS[1:0] bits (System Clock Switch Status)
RCC_CFGR_HPRE 4:7 HPRE[3:0] bits (AHB prescaler)
RCC_CFGR_PPRE1 8:10 PRE1[2:0] bits (APB1 prescaler)
RCC_CFGR_PPRE2 11:13 PRE2[2:0] bits (APB2 prescaler)
RCC_CFGR_STOPWUCK 15 Wake Up from stop and CSS backup clock selection
RCC_CFGR_HPREF 16 AHB prescaler flag
RCC_CFGR_PPRE1F 17 CPU1 APB1 prescaler flag
RCC_CFGR_PPRE2F 18 APB2 prescaler flag
RCC_CFGR_MCOSEL 24:27 MCOSEL [3:0] bits (Clock output selection)
RCC_CFGR_MCOPRE 28:30 MCO prescaler
PLLCFGR 0x0C 32 RCC System PLL configuration Register
RCC_PLLCFGR_PLLSRC 0:1
RCC_PLLCFGR_PLLM 4:6
RCC_PLLCFGR_PLLN 8:14
RCC_PLLCFGR_PLLPEN 16
RCC_PLLCFGR_PLLP 17:21
RCC_PLLCFGR_PLLQEN 24
RCC_PLLCFGR_PLLQ 25:27
RCC_PLLCFGR_PLLREN 28
RCC_PLLCFGR_PLLR 29:31
CIER 0x18 32 RCC Clock Interrupt Enable Register
RCC_CIER_LSIRDYIE 0
RCC_CIER_LSERDYIE 1
RCC_CIER_MSIRDYIE 2
RCC_CIER_HSIRDYIE 3
RCC_CIER_HSERDYIE 4
RCC_CIER_PLLRDYIE 5
RCC_CIER_LSECSSIE 9
CIFR 0x1C 32 RCC Clock Interrupt Flag Register
RCC_CIFR_LSIRDYF 0
RCC_CIFR_LSERDYF 1
RCC_CIFR_MSIRDYF 2
RCC_CIFR_HSIRDYF 3
RCC_CIFR_HSERDYF 4
RCC_CIFR_PLLRDYF 5
RCC_CIFR_CSSF 8
RCC_CIFR_LSECSSF 9
CICR 0x20 32 RCC Clock Interrupt Clear Register
RCC_CICR_LSIRDYC 0
RCC_CICR_LSERDYC 1
RCC_CICR_MSIRDYC 2
RCC_CICR_HSIRDYC 3
RCC_CICR_HSERDYC 4
RCC_CICR_PLLRDYC 5
RCC_CICR_CSSC 8
RCC_CICR_LSECSSC 9
AHB1RSTR 0x28 32 RCC AHB1 peripheral reset register
RCC_AHB1RSTR_DMA1RST 0
RCC_AHB1RSTR_DMA2RST 1
RCC_AHB1RSTR_DMAMUX1RST 2
RCC_AHB1RSTR_CRCRST 12
AHB2RSTR 0x2C 32 RCC AHB2 peripheral reset register
RCC_AHB2RSTR_GPIOARST 0
RCC_AHB2RSTR_GPIOBRST 1
RCC_AHB2RSTR_GPIOCRST 2
RCC_AHB2RSTR_GPIOHRST 7
AHB3RSTR 0x30 32 RCC AHB3 peripheral reset register
RCC_AHB3RSTR_PKARST 16
RCC_AHB3RSTR_AESRST 17
RCC_AHB3RSTR_RNGRST 18
RCC_AHB3RSTR_HSEMRST 19
RCC_AHB3RSTR_FLASHRST 25
APB1RSTR1 0x38 32 RCC APB1 peripheral reset register 1
RCC_APB1RSTR1_TIM2RST 0
RCC_APB1RSTR1_SPI2RST 14
RCC_APB1RSTR1_USART2RST 17
RCC_APB1RSTR1_I2C1RST 21
RCC_APB1RSTR1_I2C2RST 22
RCC_APB1RSTR1_I2C3RST 23
RCC_APB1RSTR1_DACRST 29
RCC_APB1RSTR1_LPTIM1RST 31
APB1RSTR2 0x3C 32 RCC APB1 peripheral reset register 2
RCC_APB1RSTR2_LPUART1RST 0
RCC_APB1RSTR2_LPTIM2RST 5
RCC_APB1RSTR2_LPTIM3RST 6
APB2RSTR 0x40 32 RCC APB2 peripheral reset register
RCC_APB2RSTR_ADCRST 9
RCC_APB2RSTR_TIM1RST 11
RCC_APB2RSTR_SPI1RST 12
RCC_APB2RSTR_USART1RST 14
RCC_APB2RSTR_TIM16RST 17
RCC_APB2RSTR_TIM17RST 18
APB3RSTR 0x44 32 RCC APB3 peripheral reset register
RCC_APB3RSTR_SUBGHZSPIRST 0
AHB1ENR 0x48 32 RCC AHB1 peripheral clocks enable register
RCC_AHB1ENR_DMA1EN 0
RCC_AHB1ENR_DMA2EN 1
RCC_AHB1ENR_DMAMUX1EN 2
RCC_AHB1ENR_CRCEN 12
AHB2ENR 0x4C 32 RCC AHB2 peripheral clocks enable register
RCC_AHB2ENR_GPIOAEN 0
RCC_AHB2ENR_GPIOBEN 1
RCC_AHB2ENR_GPIOCEN 2
RCC_AHB2ENR_GPIOHEN 7
AHB3ENR 0x50 32 RCC AHB3 peripheral clocks enable register
RCC_AHB3ENR_PKAEN 16
RCC_AHB3ENR_AESEN 17
RCC_AHB3ENR_RNGEN 18
RCC_AHB3ENR_HSEMEN 19
RCC_AHB3ENR_FLASHEN 25
APB1ENR1 0x58 32 RCC APB1 peripheral clocks enable register 1
RCC_APB1ENR1_TIM2EN 0
RCC_APB1ENR1_RTCAPBEN 10
RCC_APB1ENR1_WWDGEN 11
RCC_APB1ENR1_SPI2EN 14
RCC_APB1ENR1_USART2EN 17
RCC_APB1ENR1_I2C1EN 21
RCC_APB1ENR1_I2C2EN 22
RCC_APB1ENR1_I2C3EN 23
RCC_APB1ENR1_DACEN 29
RCC_APB1ENR1_LPTIM1EN 31
APB1ENR2 0x5C 32 RCC APB1 peripheral clocks enable register 2
RCC_APB1ENR2_LPUART1EN 0
RCC_APB1ENR2_LPTIM2EN 5
RCC_APB1ENR2_LPTIM3EN 6
APB2ENR 0x60 32 RCC APB2 peripheral clocks enable register
RCC_APB2ENR_ADCEN 9
RCC_APB2ENR_TIM1EN 11
RCC_APB2ENR_SPI1EN 12
RCC_APB2ENR_USART1EN 14
RCC_APB2ENR_TIM16EN 17
RCC_APB2ENR_TIM17EN 18
APB3ENR 0x64 32 RCC APB3 peripheral clocks enable register
RCC_APB3ENR_SUBGHZSPIEN 0
AHB1SMENR 0x68 32 RCC AHB1 peripheral clocks enable in sleep and stop modes register
RCC_AHB1SMENR_DMA1SMEN 0
RCC_AHB1SMENR_DMA2SMEN 1
RCC_AHB1SMENR_DMAMUX1SMEN 2
RCC_AHB1SMENR_CRCSMEN 12
AHB2SMENR 0x6C 32 RCC AHB2 peripheral clocks enable in sleep and stop modes register
RCC_AHB2SMENR_GPIOASMEN 0
RCC_AHB2SMENR_GPIOBSMEN 1
RCC_AHB2SMENR_GPIOCSMEN 2
RCC_AHB2SMENR_GPIOHSMEN 7
AHB3SMENR 0x70 32 RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register
RCC_AHB3SMENR_PKASMEN 16
RCC_AHB3SMENR_AESSMEN 17
RCC_AHB3SMENR_RNGSMEN 18
RCC_AHB3SMENR_SRAM1SMEN 23
RCC_AHB3SMENR_SRAM2SMEN 24
RCC_AHB3SMENR_FLASHSMEN 25
APB1SMENR1 0x78 32 RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1
RCC_APB1SMENR1_TIM2SMEN 0
RCC_APB1SMENR1_RTCAPBSMEN 10
RCC_APB1SMENR1_WWDGSMEN 11
RCC_APB1SMENR1_SPI2SMEN 14
RCC_APB1SMENR1_USART2SMEN 17
RCC_APB1SMENR1_I2C1SMEN 21
RCC_APB1SMENR1_I2C2SMEN 22
RCC_APB1SMENR1_I2C3SMEN 23
RCC_APB1SMENR1_DACSMEN 29
RCC_APB1SMENR1_LPTIM1SMEN 31
APB1SMENR2 0x7C 32 RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2
RCC_APB1SMENR2_LPUART1SMEN 0
RCC_APB1SMENR2_LPTIM2SMEN 5
RCC_APB1SMENR2_LPTIM3SMEN 6
APB2SMENR 0x80 32 RCC APB2 peripheral clocks enable in sleep mode and stop modes register
RCC_APB2SMENR_ADCSMEN 9
RCC_APB2SMENR_TIM1SMEN 11
RCC_APB2SMENR_SPI1SMEN 12
RCC_APB2SMENR_USART1SMEN 14
RCC_APB2SMENR_TIM16SMEN 17
RCC_APB2SMENR_TIM17SMEN 18
APB3SMENR 0x84 32 RCC APB3 peripheral clocks enable in sleep mode and stop modes register
RCC_APB3SMENR_SUBGHZSPISMEN 0
CCIPR 0x88 32 RCC Peripherals Clock Configuration Independent Register
RCC_CCIPR_USART1SEL 0:1
RCC_CCIPR_USART2SEL 2:3
RCC_CCIPR_I2S2SEL 8:9
RCC_CCIPR_LPUART1SEL 10:11
RCC_CCIPR_I2C1SEL 12:13
RCC_CCIPR_I2C2SEL 14:15
RCC_CCIPR_I2C3SEL 16:17
RCC_CCIPR_LPTIM1SEL 18:19
RCC_CCIPR_LPTIM2SEL 20:21
RCC_CCIPR_LPTIM3SEL 22:23
RCC_CCIPR_ADCSEL 28:29
RCC_CCIPR_RNGSEL 30:31
BDCR 0x90 32 RCC Backup Domain Control Register
RCC_BDCR_LSEON 0
RCC_BDCR_LSERDY 1
RCC_BDCR_LSEBYP 2
RCC_BDCR_LSEDRV 3:4
RCC_BDCR_LSECSSON 5
RCC_BDCR_LSECSSD 6
RCC_BDCR_LSESYSEN 7
RCC_BDCR_RTCSEL 8:9
RCC_BDCR_LSESYSRDY 11
RCC_BDCR_RTCEN 15
RCC_BDCR_BDRST 16
RCC_BDCR_LSCOEN 24
RCC_BDCR_LSCOSEL 25
CSR 0x94 32 RCC Control and Status Register
RCC_CSR_LSION 0
RCC_CSR_LSIRDY 1
RCC_CSR_LSIPRE 4
RCC_CSR_MSISRANGE 8:11
RCC_CSR_RFRSTF 14
RCC_CSR_RFRST 15
RCC_CSR_RMVF 23
RCC_CSR_RFILARSTF 24
RCC_CSR_OBLRSTF 25
RCC_CSR_PINRSTF 26
RCC_CSR_BORRSTF 27
RCC_CSR_SFTRSTF 28
RCC_CSR_IWDGRSTF 29
RCC_CSR_WWDGRSTF 30
RCC_CSR_LPWRRSTF 31
EXTCFGR 0x108 32 RCC Extended Clock Recovery Register
RCC_EXTCFGR_SHDHPRE 0:3
RCC_EXTCFGR_SHDHPREF 16

GPIO — Порты ввода-вывода (раздел 8)

Регистр Смещение Бит Назначение
MODER 0x00 32 GPIO port mode register
GPIO_MODER_MODE0 0:1
GPIO_MODER_MODE1 2:3
GPIO_MODER_MODE2 4:5
GPIO_MODER_MODE3 6:7
GPIO_MODER_MODE4 8:9
GPIO_MODER_MODE5 10:11
GPIO_MODER_MODE6 12:13
GPIO_MODER_MODE7 14:15
GPIO_MODER_MODE8 16:17
GPIO_MODER_MODE9 18:19
GPIO_MODER_MODE10 20:21
GPIO_MODER_MODE11 22:23
GPIO_MODER_MODE12 24:25
GPIO_MODER_MODE13 26:27
GPIO_MODER_MODE14 28:29
GPIO_MODER_MODE15 30:31
OTYPER 0x04 32 GPIO port output type register
GPIO_OTYPER_OT0 0
GPIO_OTYPER_OT1 1
GPIO_OTYPER_OT2 2
GPIO_OTYPER_OT3 3
GPIO_OTYPER_OT4 4
GPIO_OTYPER_OT5 5
GPIO_OTYPER_OT6 6
GPIO_OTYPER_OT7 7
GPIO_OTYPER_OT8 8
GPIO_OTYPER_OT9 9
GPIO_OTYPER_OT10 10
GPIO_OTYPER_OT11 11
GPIO_OTYPER_OT12 12
GPIO_OTYPER_OT13 13
GPIO_OTYPER_OT14 14
GPIO_OTYPER_OT15 15
OSPEEDR 0x08 32 GPIO port output speed register
GPIO_OSPEEDR_OSPEED0 0:1
GPIO_OSPEEDR_OSPEED1 2:3
GPIO_OSPEEDR_OSPEED2 4:5
GPIO_OSPEEDR_OSPEED3 6:7
GPIO_OSPEEDR_OSPEED4 8:9
GPIO_OSPEEDR_OSPEED5 10:11
GPIO_OSPEEDR_OSPEED6 12:13
GPIO_OSPEEDR_OSPEED7 14:15
GPIO_OSPEEDR_OSPEED8 16:17
GPIO_OSPEEDR_OSPEED9 18:19
GPIO_OSPEEDR_OSPEED10 20:21
GPIO_OSPEEDR_OSPEED11 22:23
GPIO_OSPEEDR_OSPEED12 24:25
GPIO_OSPEEDR_OSPEED13 26:27
GPIO_OSPEEDR_OSPEED14 28:29
GPIO_OSPEEDR_OSPEED15 30:31
PUPDR 0x0C 32 GPIO port pull-up/pull-down register
GPIO_PUPDR_PUPD0 0:1
GPIO_PUPDR_PUPD1 2:3
GPIO_PUPDR_PUPD2 4:5
GPIO_PUPDR_PUPD3 6:7
GPIO_PUPDR_PUPD4 8:9
GPIO_PUPDR_PUPD5 10:11
GPIO_PUPDR_PUPD6 12:13
GPIO_PUPDR_PUPD7 14:15
GPIO_PUPDR_PUPD8 16:17
GPIO_PUPDR_PUPD9 18:19
GPIO_PUPDR_PUPD10 20:21
GPIO_PUPDR_PUPD11 22:23
GPIO_PUPDR_PUPD12 24:25
GPIO_PUPDR_PUPD13 26:27
GPIO_PUPDR_PUPD14 28:29
GPIO_PUPDR_PUPD15 30:31
IDR 0x10 32 GPIO port input data register
GPIO_IDR_ID0 0
GPIO_IDR_ID1 1
GPIO_IDR_ID2 2
GPIO_IDR_ID3 3
GPIO_IDR_ID4 4
GPIO_IDR_ID5 5
GPIO_IDR_ID6 6
GPIO_IDR_ID7 7
GPIO_IDR_ID8 8
GPIO_IDR_ID9 9
GPIO_IDR_ID10 10
GPIO_IDR_ID11 11
GPIO_IDR_ID12 12
GPIO_IDR_ID13 13
GPIO_IDR_ID14 14
GPIO_IDR_ID15 15
ODR 0x14 32 GPIO port output data register
GPIO_ODR_OD0 0
GPIO_ODR_OD1 1
GPIO_ODR_OD2 2
GPIO_ODR_OD3 3
GPIO_ODR_OD4 4
GPIO_ODR_OD5 5
GPIO_ODR_OD6 6
GPIO_ODR_OD7 7
GPIO_ODR_OD8 8
GPIO_ODR_OD9 9
GPIO_ODR_OD10 10
GPIO_ODR_OD11 11
GPIO_ODR_OD12 12
GPIO_ODR_OD13 13
GPIO_ODR_OD14 14
GPIO_ODR_OD15 15
BSRR 0x18 32 GPIO port bit set/reset register
GPIO_BSRR_BS0 0
GPIO_BSRR_BS1 1
GPIO_BSRR_BS2 2
GPIO_BSRR_BS3 3
GPIO_BSRR_BS4 4
GPIO_BSRR_BS5 5
GPIO_BSRR_BS6 6
GPIO_BSRR_BS7 7
GPIO_BSRR_BS8 8
GPIO_BSRR_BS9 9
GPIO_BSRR_BS10 10
GPIO_BSRR_BS11 11
GPIO_BSRR_BS12 12
GPIO_BSRR_BS13 13
GPIO_BSRR_BS14 14
GPIO_BSRR_BS15 15
GPIO_BSRR_BR0 16
GPIO_BSRR_BR1 17
GPIO_BSRR_BR2 18
GPIO_BSRR_BR3 19
GPIO_BSRR_BR4 20
GPIO_BSRR_BR5 21
GPIO_BSRR_BR6 22
GPIO_BSRR_BR7 23
GPIO_BSRR_BR8 24
GPIO_BSRR_BR9 25
GPIO_BSRR_BR10 26
GPIO_BSRR_BR11 27
GPIO_BSRR_BR12 28
GPIO_BSRR_BR13 29
GPIO_BSRR_BR14 30
GPIO_BSRR_BR15 31
LCKR 0x1C 32 GPIO port configuration lock register
GPIO_LCKR_LCK0 0
GPIO_LCKR_LCK1 1
GPIO_LCKR_LCK2 2
GPIO_LCKR_LCK3 3
GPIO_LCKR_LCK4 4
GPIO_LCKR_LCK5 5
GPIO_LCKR_LCK6 6
GPIO_LCKR_LCK7 7
GPIO_LCKR_LCK8 8
GPIO_LCKR_LCK9 9
GPIO_LCKR_LCK10 10
GPIO_LCKR_LCK11 11
GPIO_LCKR_LCK12 12
GPIO_LCKR_LCK13 13
GPIO_LCKR_LCK14 14
GPIO_LCKR_LCK15 15
GPIO_LCKR_LCKK 16
AFR+2×4 0x20 32 GPIO alternate function registers
BRR 0x28 32 GPIO Bit Reset register
GPIO_BRR_BR0 0
GPIO_BRR_BR1 1
GPIO_BRR_BR2 2
GPIO_BRR_BR3 3
GPIO_BRR_BR4 4
GPIO_BRR_BR5 5
GPIO_BRR_BR6 6
GPIO_BRR_BR7 7
GPIO_BRR_BR8 8
GPIO_BRR_BR9 9
GPIO_BRR_BR10 10
GPIO_BRR_BR11 11
GPIO_BRR_BR12 12
GPIO_BRR_BR13 13
GPIO_BRR_BR14 14
GPIO_BRR_BR15 15

SYSCFG — Системная конфигурация (раздел 8)

Регистр Смещение Бит Назначение
MEMRMP 0x00 32 SYSCFG memory remap register
SYSCFG_MEMRMP_MEM_MODE 0:2 SYSCFG_Memory Remap Config
CFGR1 0x04 32 SYSCFG configuration register 1
SYSCFG_CFGR1_BOOSTEN 8 I/O analog switch voltage booster enable
SYSCFG_CFGR1_I2C_PB6_FMP 16 Fast-mode Plus (Fm+) driving capability activation on PB6
SYSCFG_CFGR1_I2C_PB7_FMP 17 Fast-mode Plus (Fm+) driving capability activation on PB7
SYSCFG_CFGR1_I2C_PB8_FMP 18 Fast-mode Plus (Fm+) driving capability activation on PB8
SYSCFG_CFGR1_I2C_PB9_FMP 19 Fast-mode Plus (Fm+) driving capability activation on PB9
SYSCFG_CFGR1_I2C1_FMP 20 I2C1 Fast-mode Plus (Fm+) driving capability activation
SYSCFG_CFGR1_I2C2_FMP 21 I2C2 Fast-mode Plus (Fm+) driving capability activation
SYSCFG_CFGR1_I2C3_FMP 22 I2C3 Fast-mode Plus (Fm+) driving capability activation
EXTICR+4×4 0x08 32 SYSCFG external interrupt configuration registers
SCSR 0x18 32 SYSCFG SRAM2 control and status register
SYSCFG_SCSR_SRAM2ER 0 SRAM2 Erase
SYSCFG_SCSR_SRAMBSY 1 SRAM2 and SRAM1 busy by erase operation
SYSCFG_SCSR_PKASRAMBSY 8 PKA SRAM busy by erase operation
CFGR2 0x1C 32 SYSCFG configuration register 2
SYSCFG_CFGR2_CLL 0 Cortex M4 LOCKUP (hardfault) output enable
SYSCFG_CFGR2_SPL 1 SRAM2 Parity Lock
SYSCFG_CFGR2_PVDL 2 PVD Lock
SYSCFG_CFGR2_ECCL 3 ECC Lock
SYSCFG_CFGR2_SPF 8 SRAM2 Parity Lock
SWPR 0x20 32 SYSCFG SRAM2 write protection register part
SYSCFG_SWPR_PAGE0 0 SRAM2 Write protection page 0 (0x20008000 - 0x200083FF)
SYSCFG_SWPR_PAGE1 1 SRAM2 Write protection page 1 (0x20008400 - 0x200087FF)
SYSCFG_SWPR_PAGE2 2 SRAM2 Write protection page 2 (0x20008800 - 0x20008BFF)
SYSCFG_SWPR_PAGE3 3 SRAM2 Write protection page 3 (0x20008C00 - 0x20008FFF)
SYSCFG_SWPR_PAGE4 4 SRAM2 Write protection page 4 (0x20009000 - 0x200093FF)
SYSCFG_SWPR_PAGE5 5 SRAM2 Write protection page 5 (0x20009400 - 0x200097FF)
SYSCFG_SWPR_PAGE6 6 SRAM2 Write protection page 6 (0x20009800 - 0x20009BFF)
SYSCFG_SWPR_PAGE7 7 SRAM2 Write protection page 7 (0x20009C00 - 0x20009FFF)
SYSCFG_SWPR_PAGE8 8 SRAM2 Write protection page 8 (0x2000A000 - 0x2000A3FF)
SYSCFG_SWPR_PAGE9 9 SRAM2 Write protection page 9 (0x2000A400 - 0x2000A7FF)
SYSCFG_SWPR_PAGE10 10 SRAM2 Write protection page 10 (0x2000A800 - 0x2000ABFF)
SYSCFG_SWPR_PAGE11 11 SRAM2 Write protection page 11 (0x2000AC00 - 0x2000AFFF)
SYSCFG_SWPR_PAGE12 12 SRAM2 Write protection page 12 (0x2000B000 - 0x2000B3FF)
SYSCFG_SWPR_PAGE13 13 SRAM2 Write protection page 13 (0x2000B400 - 0x2000B7FF)
SYSCFG_SWPR_PAGE14 14 SRAM2 Write protection page 14 (0x2000B800 - 0x2000BBFF)
SYSCFG_SWPR_PAGE15 15 SRAM2 Write protection page 15 (0x2000BC00 - 0x2000BFFF)
SYSCFG_SWPR_PAGE16 16 SRAM2 Write protection page 16 (0x2000C000 - 0x2000C3FF)
SYSCFG_SWPR_PAGE17 17 SRAM2 Write protection page 17 (0x2000C400 - 0x2000C7FF)
SYSCFG_SWPR_PAGE18 18 SRAM2 Write protection page 18 (0x2000C800 - 0x2000CBFF)
SYSCFG_SWPR_PAGE19 19 SRAM2 Write protection page 19 (0x2000CC00 - 0x2000CFFF)
SYSCFG_SWPR_PAGE20 20 SRAM2 Write protection page 20 (0x2000D000 - 0x2000D3FF)
SYSCFG_SWPR_PAGE21 21 SRAM2 Write protection page 21 (0x2000D400 - 0x2000D7FF)
SYSCFG_SWPR_PAGE22 22 SRAM2 Write protection page 22 (0x2000D800 - 0x2000DBFF)
SYSCFG_SWPR_PAGE23 23 SRAM2 Write protection page 23 (0x2000DC00 - 0x2000DFFF)
SYSCFG_SWPR_PAGE24 24 SRAM2 Write protection page 24 (0x2000E000 - 0x2000E3FF)
SYSCFG_SWPR_PAGE25 25 SRAM2 Write protection page 25 (0x2000E400 - 0x2000E7FF)
SYSCFG_SWPR_PAGE26 26 SRAM2 Write protection page 26 (0x2000E800 - 0x2000EBFF)
SYSCFG_SWPR_PAGE27 27 SRAM2 Write protection page 27 (0x2000EC00 - 0x2000EFFF)
SYSCFG_SWPR_PAGE28 28 SRAM2 Write protection page 28 (0x2000F000 - 0x2000F3FF)
SYSCFG_SWPR_PAGE29 29 SRAM2 Write protection page 29 (0x2000F400 - 0x2000F7FF)
SYSCFG_SWPR_PAGE30 30 SRAM2 Write protection page 30 (0x2000F800 - 0x2000FBFF)
SYSCFG_SWPR_PAGE31 31 SRAM2 Write protection page 31 (0x2000FC00 - 0x2000FFFF)
SKR 0x24 32 SYSCFG SRAM2 key register
SYSCFG_SKR_KEY 0:7 SRAM2 write protection key for software erase
RFDCR 0x208 32 SYSCFG CPU2 radio debug control register
SYSCFG_RFDCR_RFTBSEL 0 Radio debug test bus selection

EXTI — Внешние прерывания (раздел 7)

Регистр Смещение Бит Назначение
RTSR1 0x00 32 EXTI rising trigger selection register [31:0]
EXTI_RTSR1_RT0 0 Rising trigger event configuration bit of line 0
EXTI_RTSR1_RT1 1 Rising trigger event configuration bit of line 1
EXTI_RTSR1_RT2 2 Rising trigger event configuration bit of line 2
EXTI_RTSR1_RT3 3 Rising trigger event configuration bit of line 3
EXTI_RTSR1_RT4 4 Rising trigger event configuration bit of line 4
EXTI_RTSR1_RT5 5 Rising trigger event configuration bit of line 5
EXTI_RTSR1_RT6 6 Rising trigger event configuration bit of line 6
EXTI_RTSR1_RT7 7 Rising trigger event configuration bit of line 7
EXTI_RTSR1_RT8 8 Rising trigger event configuration bit of line 8
EXTI_RTSR1_RT9 9 Rising trigger event configuration bit of line 9
EXTI_RTSR1_RT10 10 Rising trigger event configuration bit of line 10
EXTI_RTSR1_RT11 11 Rising trigger event configuration bit of line 11
EXTI_RTSR1_RT12 12 Rising trigger event configuration bit of line 12
EXTI_RTSR1_RT13 13 Rising trigger event configuration bit of line 13
EXTI_RTSR1_RT14 14 Rising trigger event configuration bit of line 14
EXTI_RTSR1_RT15 15 Rising trigger event configuration bit of line 15
EXTI_RTSR1_RT16 16 Rising trigger event configuration bit of line 16
EXTI_RTSR1_RT21 21 Rising trigger event configuration bit of line 21
EXTI_RTSR1_RT22 22 Rising trigger event configuration bit of line 22
FTSR1 0x04 32 EXTI falling trigger selection register [31:0]
EXTI_FTSR1_FT0 0 Falling trigger event configuration bit of line 0
EXTI_FTSR1_FT1 1 Falling trigger event configuration bit of line 1
EXTI_FTSR1_FT2 2 Falling trigger event configuration bit of line 2
EXTI_FTSR1_FT3 3 Falling trigger event configuration bit of line 3
EXTI_FTSR1_FT4 4 Falling trigger event configuration bit of line 4
EXTI_FTSR1_FT5 5 Falling trigger event configuration bit of line 5
EXTI_FTSR1_FT6 6 Falling trigger event configuration bit of line 6
EXTI_FTSR1_FT7 7 Falling trigger event configuration bit of line 7
EXTI_FTSR1_FT8 8 Falling trigger event configuration bit of line 8
EXTI_FTSR1_FT9 9 Falling trigger event configuration bit of line 9
EXTI_FTSR1_FT10 10 Falling trigger event configuration bit of line 10
EXTI_FTSR1_FT11 11 Falling trigger event configuration bit of line 11
EXTI_FTSR1_FT12 12 Falling trigger event configuration bit of line 12
EXTI_FTSR1_FT13 13 Falling trigger event configuration bit of line 13
EXTI_FTSR1_FT14 14 Falling trigger event configuration bit of line 14
EXTI_FTSR1_FT15 15 Falling trigger event configuration bit of line 15
EXTI_FTSR1_FT16 16 Falling trigger event configuration bit of line 16
EXTI_FTSR1_FT21 21 Falling trigger event configuration bit of line 21
EXTI_FTSR1_FT22 22 Falling trigger event configuration bit of line 22
SWIER1 0x08 32 EXTI software interrupt event register [31:0]
EXTI_SWIER1_SWI0 0 Software Interrupt on line 0
EXTI_SWIER1_SWI1 1 Software Interrupt on line 1
EXTI_SWIER1_SWI2 2 Software Interrupt on line 2
EXTI_SWIER1_SWI3 3 Software Interrupt on line 3
EXTI_SWIER1_SWI4 4 Software Interrupt on line 4
EXTI_SWIER1_SWI5 5 Software Interrupt on line 5
EXTI_SWIER1_SWI6 6 Software Interrupt on line 6
EXTI_SWIER1_SWI7 7 Software Interrupt on line 7
EXTI_SWIER1_SWI8 8 Software Interrupt on line 8
EXTI_SWIER1_SWI9 9 Software Interrupt on line 9
EXTI_SWIER1_SWI10 10 Software Interrupt on line 10
EXTI_SWIER1_SWI11 11 Software Interrupt on line 11
EXTI_SWIER1_SWI12 12 Software Interrupt on line 12
EXTI_SWIER1_SWI13 13 Software Interrupt on line 13
EXTI_SWIER1_SWI14 14 Software Interrupt on line 14
EXTI_SWIER1_SWI15 15 Software Interrupt on line 15
EXTI_SWIER1_SWI16 16 Software Interrupt on line 16
EXTI_SWIER1_SWI21 21 Software Interrupt on line 21
EXTI_SWIER1_SWI22 22 Software Interrupt on line 22
PR1 0x0C 32 EXTI pending register [31:0]
EXTI_PR1_PIF0 0 Pending bit for line 0
EXTI_PR1_PIF1 1 Pending bit for line 1
EXTI_PR1_PIF2 2 Pending bit for line 2
EXTI_PR1_PIF3 3 Pending bit for line 3
EXTI_PR1_PIF4 4 Pending bit for line 4
EXTI_PR1_PIF5 5 Pending bit for line 5
EXTI_PR1_PIF6 6 Pending bit for line 6
EXTI_PR1_PIF7 7 Pending bit for line 7
EXTI_PR1_PIF8 8 Pending bit for line 8
EXTI_PR1_PIF9 9 Pending bit for line 9
EXTI_PR1_PIF10 10 Pending bit for line 10
EXTI_PR1_PIF11 11 Pending bit for line 11
EXTI_PR1_PIF12 12 Pending bit for line 12
EXTI_PR1_PIF13 13 Pending bit for line 13
EXTI_PR1_PIF14 14 Pending bit for line 14
EXTI_PR1_PIF15 15 Pending bit for line 15
EXTI_PR1_PIF16 16 Pending bit for line 16
EXTI_PR1_PIF21 21 Pending bit for line 21
EXTI_PR1_PIF22 22 Pending bit for line 22
RTSR2 0x20 32 EXTI rising trigger selection register [31:0]
EXTI_RTSR2_RT34 2 Rising trigger event configuration bit of line 34
EXTI_RTSR2_RT45 13 Rising trigger event configuration bit of line 45
FTSR2 0x24 32 EXTI falling trigger selection register [31:0]
EXTI_FTSR2_FT34 2 Falling trigger event configuration bit of line 34
EXTI_FTSR2_FT45 13 Falling trigger event configuration bit of line 45
SWIER2 0x28 32 EXTI software interrupt event register [31:0]
EXTI_SWIER2_SWI34 2 Software Interrupt on line 34
EXTI_SWIER2_SWI45 13 Software Interrupt on line 45
PR2 0x2C 32 EXTI pending register [31:0]
EXTI_PR2_PIF34 2 Pending bit for line 34
EXTI_PR2_PIF45 13 Pending bit for line 45
IMR1 0x80 32 EXTI wakeup with interrupt mask register for cpu1 [31:0]
EXTI_IMR1_IM0 0 CPU1 Interrupt Mask on line 0
EXTI_IMR1_IM1 1 CPU1 Interrupt Mask on line 1
EXTI_IMR1_IM2 2 CPU1 Interrupt Mask on line 2
EXTI_IMR1_IM3 3 CPU1 Interrupt Mask on line 3
EXTI_IMR1_IM4 4 CPU1 Interrupt Mask on line 4
EXTI_IMR1_IM5 5 CPU1 Interrupt Mask on line 5
EXTI_IMR1_IM6 6 CPU1 Interrupt Mask on line 6
EXTI_IMR1_IM7 7 CPU1 Interrupt Mask on line 7
EXTI_IMR1_IM8 8 CPU1 Interrupt Mask on line 8
EXTI_IMR1_IM9 9 CPU1 Interrupt Mask on line 9
EXTI_IMR1_IM10 10 CPU1 Interrupt Mask on line 10
EXTI_IMR1_IM11 11 CPU1 Interrupt Mask on line 11
EXTI_IMR1_IM12 12 CPU1 Interrupt Mask on line 12
EXTI_IMR1_IM13 13 CPU1 Interrupt Mask on line 13
EXTI_IMR1_IM14 14 CPU1 Interrupt Mask on line 14
EXTI_IMR1_IM15 15 CPU1 Interrupt Mask on line 15
EXTI_IMR1_IM16 16 CPU1 Interrupt Mask on line 16
EXTI_IMR1_IM17 17 CPU1 Interrupt Mask on line 17
EXTI_IMR1_IM18 18 CPU1 Interrupt Mask on line 18
EXTI_IMR1_IM19 19 CPU1 Interrupt Mask on line 19
EXTI_IMR1_IM20 20 CPU1 Interrupt Mask on line 20
EXTI_IMR1_IM21 21 CPU1 Interrupt Mask on line 21
EXTI_IMR1_IM22 22 CPU1 Interrupt Mask on line 22
EXTI_IMR1_IM23 23 CPU1 Interrupt Mask on line 23
EXTI_IMR1_IM24 24 CPU1 Interrupt Mask on line 24
EXTI_IMR1_IM25 25 CPU1 Interrupt Mask on line 25
EXTI_IMR1_IM26 26 CPU1 Interrupt Mask on line 26
EXTI_IMR1_IM27 27 CPU1 Interrupt Mask on line 27
EXTI_IMR1_IM28 28 CPU1 Interrupt Mask on line 28
EXTI_IMR1_IM29 29 CPU1 Interrupt Mask on line 29
EXTI_IMR1_IM30 30 CPU1 Interrupt Mask on line 30
EXTI_IMR1_IM31 31 CPU1 Interrupt Mask on line 31
EMR1 0x84 32 EXTI wakeup with event mask register for cpu1 [31:0]
EXTI_EMR1_EM0 0 CPU1 Event Mask on line 0
EXTI_EMR1_EM1 1 CPU1 Event Mask on line 1
EXTI_EMR1_EM2 2 CPU1 Event Mask on line 2
EXTI_EMR1_EM3 3 CPU1 Event Mask on line 3
EXTI_EMR1_EM4 4 CPU1 Event Mask on line 4
EXTI_EMR1_EM5 5 CPU1 Event Mask on line 5
EXTI_EMR1_EM6 6 CPU1 Event Mask on line 6
EXTI_EMR1_EM7 7 CPU1 Event Mask on line 7
EXTI_EMR1_EM8 8 CPU1 Event Mask on line 8
EXTI_EMR1_EM9 9 CPU1 Event Mask on line 9
EXTI_EMR1_EM10 10 CPU1 Event Mask on line 10
EXTI_EMR1_EM11 11 CPU1 Event Mask on line 11
EXTI_EMR1_EM12 12 CPU1 Event Mask on line 12
EXTI_EMR1_EM13 13 CPU1 Event Mask on line 13
EXTI_EMR1_EM14 14 CPU1 Event Mask on line 14
EXTI_EMR1_EM15 15 CPU1 Event Mask on line 15
EXTI_EMR1_EM17 17 CPU1 Event Mask on line 17
EXTI_EMR1_EM19 19 CPU1 Event Mask on line 19
EXTI_EMR1_EM20 20 CPU1 Event Mask on line 20
EXTI_EMR1_EM21 21 CPU1 Event Mask on line 21
EXTI_EMR1_EM22 22 CPU1 Event Mask on line 22
IMR2 0x90 32 EXTI wakeup with interrupt mask register for cpu1 [31:0]
EXTI_IMR2_IM34 2 CPU1 Interrupt Mask on line 34
EXTI_IMR2_IM38 6 CPU1 Interrupt Mask on line 38
EXTI_IMR2_IM42 10 CPU1 Interrupt Mask on line 42
EXTI_IMR2_IM43 11 CPU1 Interrupt Mask on line 43
EXTI_IMR2_IM44 12 CPU1 Interrupt Mask on line 44
EXTI_IMR2_IM45 13 CPU1 Interrupt Mask on line 45
EXTI_IMR2_IM46 14 CPU1 Interrupt Mask on line 46
EMR2 0x94 32 EXTI wakeup with event mask register for cpu1 [31:0]

DMA — Канал DMA (раздел 9)

Регистр Смещение Бит Назначение
CCR 0x00 32 DMA channel x configuration register
DMA_CCR_EN 0 Channel enable
DMA_CCR_TCIE 1 Transfer complete interrupt enable
DMA_CCR_HTIE 2 Half Transfer interrupt enable
DMA_CCR_TEIE 3 Transfer error interrupt enable
DMA_CCR_DIR 4 Data transfer direction
DMA_CCR_CIRC 5 Circular mode
DMA_CCR_PINC 6 Peripheral increment mode
DMA_CCR_MINC 7 Memory increment mode
DMA_CCR_PSIZE 8:9 PSIZE[1:0] bits (Peripheral size)
DMA_CCR_MSIZE 10:11 MSIZE[1:0] bits (Memory size)
DMA_CCR_PL 12:13 PL[1:0] bits(Channel Priority level)
DMA_CCR_MEM2MEM 14 Memory to memory mode
CNDTR 0x04 32 DMA channel x number of data register
DMA_CNDTR_NDT 0:17 Number of data to Transfer
CPAR 0x08 32 DMA channel x peripheral address register
DMA_CPAR_PA 0:31 Peripheral Address
CMAR 0x0C 32 DMA channel x memory address register
DMA_CMAR_MA 0:31 Memory Address

PWR — Питание и режимы сна (раздел 10)

Регистр Смещение Бит Назначение
CR1 0x00 32 PWR Power Control Register 1
PWR_CR1_LPMS 0:2 Low Power Mode Selection for CPU1
PWR_CR1_SUBGHZSPINSSSEL 3 Sub-GHz radio SPI NSS source select
PWR_CR1_FPDR 4 Flash power down mode during LPrun for CPU1
PWR_CR1_FPDS 5 Flash power down mode during LPsleep for CPU1
PWR_CR1_DBP 8 Disable Backup Domain write protection
PWR_CR1_VOS 9:10 Voltage scaling range selection
PWR_CR1_LPR 14 Regulator Low-Power Run mode
CR2 0x04 32 PWR Power Control Register 2
PWR_CR2_PVDE 0 Power voltage detector enable
PWR_CR2_PLS 1:3 Power voltage detector level selection
PWR_CR2_PVME3 6 Peripherical Voltage Monitor Vdda Enable
CR3 0x08 32 PWR Power Control Register 3
PWR_CR3_EWUP 0:2 Enable all external Wake-Up lines
PWR_CR3_EWUP1 0 Enable external WKUP Pin 1 [line 0]
PWR_CR3_EWUP2 1 Enable external WKUP Pin 2 [line 1]
PWR_CR3_EWUP3 2 Enable external WKUP Pin 3 [line 2]
PWR_CR3_ULPEN 7 Enable periodical sampling of supply voltage in Stop and Standby modes for detecting condition of PDR and BOR reset
PWR_CR3_EWPVD 8 Enable wakeup PVD for CPU1
PWR_CR3_RRS 9 SRAM2 retention in STANDBY mode
PWR_CR3_APC 10 Apply pull-up and pull-down configuration for CPU1
PWR_CR3_EWRFBUSY 15 Enable Radio busy IRQ and wake-up for CPU1
PWR_CR3_EWRFIRQ 17 Enable Radio IRQ[2:0] and wake-up for CPU1
PWR_CR3_EIWUL 19 Internal Wake-Up line interrupt for CPU1
CR4 0x0C 32 PWR Power Control Register 4
PWR_CR4_WP1 0 Wake-Up Pin 1 [line 0] polarity
PWR_CR4_WP2 1 Wake-Up Pin 2 [line 1] polarity
PWR_CR4_WP3 2 Wake-Up Pin 3 [line 2] polarity
PWR_CR4_VBE 8 VBAT battery charging enable
PWR_CR4_VBRS 9 VBAT battery charging resistor selection
PWR_CR4_WRFBUSYP 15 Wake-up radio busy polarity
SR1 0x10 32 PWR Power Status Register 1
PWR_SR1_WUF 0:2 Wakeup Flags of all pins
PWR_SR1_WUF1 0 Wakeup Pin 1 [Flag 0]
PWR_SR1_WUF2 1 Wakeup Pin 2 [Flag 1]
PWR_SR1_WUF3 2 Wakeup Pin 3 [Flag 2]
PWR_SR1_WPVDF 8 Wakeup PVD flag
PWR_SR1_WRFBUSYF 11 Wakeup radio busy flag
PWR_SR1_WUFI 15 Internal wakeup interrupt flag
SR2 0x14 32 PWR Power Status Register 2
PWR_SR2_RFBUSYS 1 Radio busy signal status
PWR_SR2_RFBUSYMS 2 Radio busy masked signal status
PWR_SR2_SMPSRDY 3 SMPS ready flag
PWR_SR2_LDORDY 4 LDO ready flag
PWR_SR2_RFEOLF 5 Radio end of life flag
PWR_SR2_REGMRS 6 Main regulator status
PWR_SR2_FLASHRDY 7 Flash ready
PWR_SR2_REGLPS 8 Low-power regulator ready
PWR_SR2_REGLPF 9 Low-power regulator being used
PWR_SR2_VOSF 10 Voltage scaling flag
PWR_SR2_PVDO 11 Power voltage detector output
PWR_SR2_PVMO3 14 Peripheral voltage monitor output 3: VDDA vs. 1.62V
SCR 0x18 32 PWR Power Status Reset Register
PWR_SCR_CWUF 0:2 Clear Wake-up Flags for all pins
PWR_SCR_CWUF1 0 Clear Wake-up Pin 1 [Flag 0]
PWR_SCR_CWUF2 1 Clear Wake-up Pin 2 [Flag 1]
PWR_SCR_CWUF3 2 Clear Wake-up Pin 3 [Flag 2]
PWR_SCR_CWPVDF 8 Clear wakeup PVD interrupt flag
PWR_SCR_CWRFBUSYF 11 Clear Radio busy interrupt flag
CR5 0x1C 32 PWR Power Control Register 5
PWR_CR5_RFEOLEN 14 Enable Radio End Of Life detector enabled
PWR_CR5_SMPSEN 15 Enable SMPS Step Down converter SMPS mode enable
PUCRA 0x20 32 PWR Pull-Up Control Register of port A
PWR_PUCRA_PA0 0 Pin PA0 Pull-Up set
PWR_PUCRA_PA1 1 Pin PA1 Pull-Up set
PWR_PUCRA_PA2 2 Pin PA2 Pull-Up set
PWR_PUCRA_PA3 3 Pin PA3 Pull-Up set
PWR_PUCRA_PA4 4 Pin PA4 Pull-Up set
PWR_PUCRA_PA5 5 Pin PA5 Pull-Up set
PWR_PUCRA_PA6 6 Pin PA6 Pull-Up set
PWR_PUCRA_PA7 7 Pin PA7 Pull-Up set
PWR_PUCRA_PA8 8 Pin PA8 Pull-Up set
PWR_PUCRA_PA9 9 Pin PA9 Pull-Up set
PWR_PUCRA_PA10 10 Pin PA10 Pull-Up set
PWR_PUCRA_PA11 11 Pin PA11 Pull-Up set
PWR_PUCRA_PA12 12 Pin PA12 Pull-Up set
PWR_PUCRA_PA13 13 Pin PA13 Pull-Up set
PWR_PUCRA_PA14 14 Pin PA14 Pull-Up set
PWR_PUCRA_PA15 15 Pin PA15 Pull-Up set
PDCRA 0x24 32 PWR Pull-Down Control Register of port A
PWR_PDCRA_PA0 0 Pin PA0 Pull-Down set
PWR_PDCRA_PA1 1 Pin PA1 Pull-Down set
PWR_PDCRA_PA2 2 Pin PA2 Pull-Down set
PWR_PDCRA_PA3 3 Pin PA3 Pull-Down set
PWR_PDCRA_PA4 4 Pin PA4 Pull-Down set
PWR_PDCRA_PA5 5 Pin PA5 Pull-Down set
PWR_PDCRA_PA6 6 Pin PA6 Pull-Down set
PWR_PDCRA_PA7 7 Pin PA7 Pull-Down set
PWR_PDCRA_PA8 8 Pin PA8 Pull-Down set
PWR_PDCRA_PA9 9 Pin PA9 Pull-Down set
PWR_PDCRA_PA10 10 Pin PA10 Pull-Down set
PWR_PDCRA_PA11 11 Pin PA11 Pull-Down set
PWR_PDCRA_PA12 12 Pin PA12 Pull-Down set
PWR_PDCRA_PA13 13 Pin PA13 Pull-Down set
PWR_PDCRA_PA14 14 Pin PA14 Pull-Down set
PWR_PDCRA_PA15 15 Pin PA15 Pull-Down set
PUCRB 0x28 32 PWR Pull-Up Control Register of port B
PWR_PUCRB_PB0 0 Pin PB0 Pull-Up set
PWR_PUCRB_PB1 1 Pin PB1 Pull-Up set
PWR_PUCRB_PB2 2 Pin PB2 Pull-Up set
PWR_PUCRB_PB3 3 Pin PB3 Pull-Up set
PWR_PUCRB_PB4 4 Pin PB4 Pull-Up set
PWR_PUCRB_PB5 5 Pin PB5 Pull-Up set
PWR_PUCRB_PB6 6 Pin PB6 Pull-Up set
PWR_PUCRB_PB7 7 Pin PB7 Pull-Up set
PWR_PUCRB_PB8 8 Pin PB8 Pull-Up set
PWR_PUCRB_PB9 9 Pin PB9 Pull-Up set
PWR_PUCRB_PB10 10 Pin PB10 Pull-Up set
PWR_PUCRB_PB11 11 Pin PB11 Pull-Up set
PWR_PUCRB_PB12 12 Pin PB12 Pull-Up set
PWR_PUCRB_PB13 13 Pin PB13 Pull-Up set
PWR_PUCRB_PB14 14 Pin PB14 Pull-Up set
PWR_PUCRB_PB15 15 Pin PB15 Pull-Up set
PDCRB 0x2C 32 PWR Pull-Down Control Register of port B
PWR_PDCRB_PB0 0 Pin PB0 Pull-Down set
PWR_PDCRB_PB1 1 Pin PB1 Pull-Down set
PWR_PDCRB_PB2 2 Pin PB2 Pull-Down set
PWR_PDCRB_PB3 3 Pin PB3 Pull-Down set
PWR_PDCRB_PB4 4 Pin PB4 Pull-Down set
PWR_PDCRB_PB5 5 Pin PB5 Pull-Down set
PWR_PDCRB_PB6 6 Pin PB6 Pull-Down set
PWR_PDCRB_PB7 7 Pin PB7 Pull-Down set
PWR_PDCRB_PB8 8 Pin PB8 Pull-Down set
PWR_PDCRB_PB9 9 Pin PB9 Pull-Down set
PWR_PDCRB_PB10 10 Pin PB10 Pull-Down set
PWR_PDCRB_PB11 11 Pin PB11 Pull-Down set
PWR_PDCRB_PB12 12 Pin PB12 Pull-Down set
PWR_PDCRB_PB13 13 Pin PB13 Pull-Down set
PWR_PDCRB_PB14 14 Pin PB14 Pull-Down set
PWR_PDCRB_PB15 15 Pin PB15 Pull-Down set
PUCRC 0x30 32 PWR Pull-Up Control Register of port C
PWR_PUCRC_PC0 0 Pin PC0 Pull-Up set
PWR_PUCRC_PC1 1 Pin PC1 Pull-Up set
PWR_PUCRC_PC2 2 Pin PC2 Pull-Up set
PWR_PUCRC_PC3 3 Pin PC3 Pull-Up set
PWR_PUCRC_PC4 4 Pin PC4 Pull-Up set
PWR_PUCRC_PC5 5 Pin PC5 Pull-Up set
PWR_PUCRC_PC6 6 Pin PC6 Pull-Up set
PWR_PUCRC_PC13 13 Pin PC13 Pull-Up set
PWR_PUCRC_PC14 14 Pin PC14 Pull-Up set
PWR_PUCRC_PC15 15 Pin PC15 Pull-Up set
PDCRC 0x34 32 PWR Pull-Down Control Register of port C
PWR_PDCRC_PC0 0 Pin PC0 Pull-Down set
PWR_PDCRC_PC1 1 Pin PC1 Pull-Down set
PWR_PDCRC_PC2 2 Pin PC2 Pull-Down set
PWR_PDCRC_PC3 3 Pin PC3 Pull-Down set
PWR_PDCRC_PC4 4 Pin PC4 Pull-Down set
PWR_PDCRC_PC5 5 Pin PC5 Pull-Down set
PWR_PDCRC_PC6 6 Pin PC6 Pull-Down set
PWR_PDCRC_PC13 13 Pin PC13 Pull-Down set
PWR_PDCRC_PC14 14 Pin PC14 Pull-Down set
PWR_PDCRC_PC15 15 Pin PC15 Pull-Down set
PUCRH 0x58 32 PWR Pull-Up Control Register of port H
PWR_PUCRH_PH3 2 Pin PH3 Pull-Up set
PDCRH 0x5C 32 PWR Pull-Down Control Register of port H
PWR_PDCRH_PH3 2 Pin PH3 Pull-Down set
EXTSCR 0x88 32 PWR Power Status Reset Register for CPU2
PWR_EXTSCR_C1CSSF 0 Clear standby and stop flags for CPU1
PWR_EXTSCR_C1SBF 8 System standby flag for CPU1
PWR_EXTSCR_C1STOP2F 9 System stop2 flag for CPU1
PWR_EXTSCR_C1STOPF 10 System stop0 or stop1 flag for CPU1
PWR_EXTSCR_C1DS 14 CPU1 deepsleep mode flag
SUBGHZSPICR 0x90 32 PWR SUBGHZSPI Control Register
PWR_SUBGHZSPICR_NSS 15 Sub-GHz radio SUBGHZSPI_NSS control

FLASH — Контроллер флеш-памяти (раздел 11)

Регистр Смещение Бит Назначение
ACR 0x00 32 FLASH Access control register
FLASH_ACR_LATENCY 0:2 Latency
FLASH_ACR_PRFTEN 8 Prefetch enable
FLASH_ACR_ICEN 9 Instruction cache enable
FLASH_ACR_DCEN 10 Data cache enable
FLASH_ACR_ICRST 11 Instruction cache reset
FLASH_ACR_DCRST 12 Data cache reset
FLASH_ACR_PES 15 Program/erase suspend request
FLASH_ACR_EMPTY 16 Flash use area empty
KEYR 0x08 32 FLASH Key register
OPTKEYR 0x0C 32 FLASH Option Key register
SR 0x10 32 FLASH Status register
FLASH_SR_EOP 0 End of Operation
FLASH_SR_OPERR 1 Operation error
FLASH_SR_PROGERR 3 Programming error
FLASH_SR_WRPERR 4 Write protection error
FLASH_SR_PGAERR 5 Programming alignment error
FLASH_SR_SIZERR 6 Size error
FLASH_SR_PGSERR 7 Programming sequence error
FLASH_SR_MISERR 8 Fast programming data miss error
FLASH_SR_FASTERR 9 Fast programming error
FLASH_SR_OPTNV 13 User option OPTVAL indication
FLASH_SR_RDERR 14 PCROP read error
FLASH_SR_OPTVERR 15 Option validity error
FLASH_SR_BSY 16 Flash Busy
FLASH_SR_CFGBSY 18 Programming or erase configuration busy
FLASH_SR_PESD 19 Programming/erase operation suspended
CR 0x14 32 FLASH Control register
FLASH_CR_PG 0 Flash programming
FLASH_CR_PER 1 Page erase
FLASH_CR_MER 2 Mass erase
FLASH_CR_PNB 3:9 Page number selection mask
FLASH_CR_STRT 16 Start an erase operation
FLASH_CR_OPTSTRT 17 Options modification start
FLASH_CR_FSTPG 18 Fast programming
FLASH_CR_EOPIE 24 End of operation interrupt enable
FLASH_CR_ERRIE 25 Error interrupt enable
FLASH_CR_RDERRIE 26 PCROP read error interrupt enable
FLASH_CR_OBL_LAUNCH 27 Force the option bute loading
FLASH_CR_OPTLOCK 30 Options lock
FLASH_CR_LOCK 31 Flash control register lock
ECCR 0x18 32 FLASH ECC register
FLASH_ECCR_ADDR_ECC 0:16 double-word address ECC fail
FLASH_ECCR_SYSF_ECC 20 System flash ECC fail
FLASH_ECCR_ECCCIE 24 ECC correction interrupt enable
FLASH_ECCR_CPUID 26:28 CPU identification
FLASH_ECCR_ECCC 30 ECC correction
FLASH_ECCR_ECCD 31 ECC detection
OPTR 0x20 32 FLASH Option register
FLASH_OPTR_RDP 0:7 Read protection level
FLASH_OPTR_ESE 8 Security enable
FLASH_OPTR_BOR_LEV 9:11 BOR reset level mask
FLASH_OPTR_nRST_STOP 12 Reset option in Stop mode
FLASH_OPTR_nRST_STDBY 13 Reset option in Standby mode
FLASH_OPTR_nRST_SHDW 14 Reset option in Shutdown mode
FLASH_OPTR_IWDG_SW 16 Independent watchdog selection
FLASH_OPTR_IWDG_STOP 17 Independent watchdog counter option in Stop mode
FLASH_OPTR_IWDG_STDBY 18 Independent watchdog counter option in Standby mode
FLASH_OPTR_WWDG_SW 19 Window watchdog selection
FLASH_OPTR_nBOOT1 23 Boot Configuration
FLASH_OPTR_SRAM2_PE 24 SRAM2 parity check enable
FLASH_OPTR_SRAM_RST 25 SRAM1 and SRAM2 erase option when system reset
FLASH_OPTR_nSWBOOT0 26 Software BOOT0
FLASH_OPTR_nBOOT0 27 BOOT0 option bit
FLASH_OPTR_BOOT_LOCK 30 CPU1 Boot Lock enable option bit
PCROP1ASR 0x24 32 FLASH Bank 1 PCROP area A Start address register
FLASH_PCROP1ASR_PCROP1A_STRT 0:7 PCROP area A start offset
PCROP1AER 0x28 32 FLASH Bank 1 PCROP area A End address register
FLASH_PCROP1AER_PCROP1A_END 0:7 PCROP area A end offset
FLASH_PCROP1AER_PCROP_RDP 31 PCROP area preserved when RDP level decreased
WRP1AR 0x2C 32 FLASH Bank 1 WRP area A address register
FLASH_WRP1AR_WRP1A_STRT 0:6 WRP area A start offset
FLASH_WRP1AR_WRP1A_END 16:22 WRP area A end offset
WRP1BR 0x30 32 FLASH Bank 1 WRP area B address register
FLASH_WRP1BR_WRP1B_STRT 0:6 WRP area B start offset
FLASH_WRP1BR_WRP1B_END 16:22 WRP area B end offset
PCROP1BSR 0x34 32 FLASH Bank 1 PCROP area B Start address register
FLASH_PCROP1BSR_PCROP1B_STRT 0:7 PCROP area B start offset
PCROP1BER 0x38 32 FLASH Bank 1 PCROP area B End address register
FLASH_PCROP1BER_PCROP1B_END 0:7 PCROP area B end offset

IWDG — Независимый сторож (раздел 12)

Регистр Смещение Бит Назначение
KR 0x00 32 IWDG Key register
IWDG_KR_KEY 0:15 Key value (write only, read 0000h)
PR 0x04 32 IWDG Prescaler register
IWDG_PR_PR 0:2 PR[2:0] (Prescaler divider)
RLR 0x08 32 IWDG Reload register
IWDG_RLR_RL 0:11 Watchdog counter reload value
SR 0x0C 32 IWDG Status register
IWDG_SR_PVU 0 Watchdog prescaler value update
IWDG_SR_RVU 1 Watchdog counter reload value update
IWDG_SR_WVU 2 Watchdog counter window value update
WINR 0x10 32 IWDG Window register
IWDG_WINR_WIN 0:11 Watchdog counter window value

WWDG — Оконный сторож (раздел 12)

Регистр Смещение Бит Назначение
CR 0x00 32 WWDG Control register
WWDG_CR_T 0:6 T[6:0] bits (7-Bit counter (MSB to LSB))
WWDG_CR_WDGA 7 Activation bit
CFR 0x04 32 WWDG Configuration register
WWDG_CFR_W 0:6 W[6:0] bits (7-bit window value)
WWDG_CFR_EWI 9 Early Wakeup Interrupt
WWDG_CFR_WDGTB 11:13 WDGTB[2:0] bits (Timer Base)
SR 0x08 32 WWDG Status register
WWDG_SR_EWIF 0 Early Wakeup Interrupt Flag

CRC — Контрольная сумма (раздел 12)

Регистр Смещение Бит Назначение
DR 0x00 32 CRC Data register
CRC_DR_DR 0:31 Data register bits
IDR 0x04 32 CRC Independent data register
CRC_IDR_IDR 0:7 General-purpose 8-bits data register bits
CR 0x08 32 CRC Control register
CRC_CR_RESET 0 RESET the CRC computation unit bit
CRC_CR_POLYSIZE 3:4 Polynomial size bits
CRC_CR_REV_IN 5:6 REV_IN Reverse Input Data bits
CRC_CR_REV_OUT 7 REV_OUT Reverse Output Data bits
INIT 0x10 32 Initial CRC value register
CRC_INIT_INIT 0:31 Initial CRC value bits
POL 0x14 32 CRC polynomial register
CRC_POL_POL 0:31 Coefficients of the polynomial

RTC — Часы реального времени (раздел 12)

Регистр Смещение Бит Назначение
TR 0x00 32 RTC time register
RTC_TR_SU 0:3
RTC_TR_ST 4:6
RTC_TR_MNU 8:11
RTC_TR_MNT 12:14
RTC_TR_HU 16:19
RTC_TR_HT 20:21
RTC_TR_PM 22
DR 0x04 32 RTC date register
RTC_DR_DU 0:3
RTC_DR_DT 4:5
RTC_DR_MU 8:11
RTC_DR_MT 12
RTC_DR_WDU 13:15
RTC_DR_YU 16:19
RTC_DR_YT 20:23
SSR 0x08 32 RTC sub second register
RTC_SSR_SS 0:31
ICSR 0x0C 32 RTC initialization control and status register
RTC_ICSR_WUTWF 2
RTC_ICSR_SHPF 3
RTC_ICSR_INITS 4
RTC_ICSR_RSF 5
RTC_ICSR_INITF 6
RTC_ICSR_INIT 7
RTC_ICSR_BIN 8:9
RTC_ICSR_BCDU 10:12
RTC_ICSR_RECALPF 16
PRER 0x10 32 RTC prescaler register
RTC_PRER_PREDIV_S 0:14
RTC_PRER_PREDIV_A 16:22
WUTR 0x14 32 RTC wakeup timer register
RTC_WUTR_WUTOCLR 0:15
RTC_WUTR_WUT 0:15
CR 0x18 32 RTC control register
RTC_CR_WUCKSEL 0:2
RTC_CR_TSEDGE 3
RTC_CR_REFCKON 4
RTC_CR_BYPSHAD 5
RTC_CR_FMT 6
RTC_CR_SSRUIE 7
RTC_CR_ALRAE 8
RTC_CR_ALRBE 9
RTC_CR_WUTE 10
RTC_CR_TSE 11
RTC_CR_ALRAIE 12
RTC_CR_ALRBIE 13
RTC_CR_WUTIE 14
RTC_CR_TSIE 15
RTC_CR_ADD1H 16
RTC_CR_SUB1H 17
RTC_CR_BKP 18
RTC_CR_COSEL 19
RTC_CR_POL 20
RTC_CR_OSEL 21:22
RTC_CR_COE 23
RTC_CR_ITSE 24 Timestamp on internal event enable
RTC_CR_TAMPTS 25 Activate timestamp on tamper detection event
RTC_CR_TAMPOE 26 Tamper detection output enable on TAMPALARM
RTC_CR_TAMPALRM_PU 29 TAMPALARM output pull-up config
RTC_CR_TAMPALRM_TYPE 30 TAMPALARM output type
RTC_CR_OUT2EN 31 RTC_OUT2 output enable
WPR 0x24 32 RTC write protection register
RTC_WPR_KEY 0:7
CALR 0x28 32 RTC calibration register
RTC_CALR_CALM 0:8
RTC_CALR_LPCAL 12
RTC_CALR_CALW16 13
RTC_CALR_CALW8 14
RTC_CALR_CALP 15
SHIFTR 0x2C 32 RTC shift control register
RTC_SHIFTR_SUBFS 0:14
RTC_SHIFTR_ADD1S 31
TSTR 0x30 32 RTC time stamp time register
RTC_TSTR_SU 0:3
RTC_TSTR_ST 4:6
RTC_TSTR_MNU 8:11
RTC_TSTR_MNT 12:14
RTC_TSTR_HU 16:19
RTC_TSTR_HT 20:21
RTC_TSTR_PM 22
TSDR 0x34 32 RTC time stamp date register
RTC_TSDR_DU 0:3
RTC_TSDR_DT 4:5
RTC_TSDR_MU 8:11
RTC_TSDR_MT 12
RTC_TSDR_WDU 13:15
TSSSR 0x38 32 RTC time-stamp sub second register
RTC_TSSSR_SS 0:31
ALRMAR 0x40 32 RTC alarm A register
RTC_ALRMAR_SU 0:3
RTC_ALRMAR_ST 4:6
RTC_ALRMAR_MSK1 7
RTC_ALRMAR_MNU 8:11
RTC_ALRMAR_MNT 12:14
RTC_ALRMAR_MSK2 15
RTC_ALRMAR_HU 16:19
RTC_ALRMAR_HT 20:21
RTC_ALRMAR_PM 22
RTC_ALRMAR_MSK3 23
RTC_ALRMAR_DU 24:27
RTC_ALRMAR_DT 28:29
RTC_ALRMAR_WDSEL 30
RTC_ALRMAR_MSK4 31
ALRMASSR 0x44 32 RTC alarm A sub second register
RTC_ALRMASSR_SS 0:14
RTC_ALRMASSR_MASKSS 24:27
RTC_ALRMASSR_SSCLR 31
ALRMBR 0x48 32 RTC alarm B register
RTC_ALRMBR_SU 0:3
RTC_ALRMBR_ST 4:6
RTC_ALRMBR_MSK1 7
RTC_ALRMBR_MNU 8:11
RTC_ALRMBR_MNT 12:14
RTC_ALRMBR_MSK2 15
RTC_ALRMBR_HU 16:19
RTC_ALRMBR_HT 20:21
RTC_ALRMBR_PM 22
RTC_ALRMBR_MSK3 23
RTC_ALRMBR_DU 24:27
RTC_ALRMBR_DT 28:29
RTC_ALRMBR_WDSEL 30
RTC_ALRMBR_MSK4 31
ALRMBSSR 0x4C 32 RTC alarm B sub second register
RTC_ALRMBSSR_SS 0:14
RTC_ALRMBSSR_MASKSS 24:27
RTC_ALRMBSSR_SSCLR 31
SR 0x50 32 RTC Status register
RTC_SR_ALRAF 0
RTC_SR_ALRBF 1
RTC_SR_WUTF 2
RTC_SR_TSF 3
RTC_SR_TSOVF 4
RTC_SR_ITSF 5
RTC_SR_SSRUF 6
MISR 0x54 32 RTC masked interrupt status register
RTC_MISR_ALRAMF 0
RTC_MISR_ALRBMF 1
RTC_MISR_WUTMF 2
RTC_MISR_TSMF 3
RTC_MISR_TSOVMF 4
RTC_MISR_ITSMF 5
RTC_MISR_SSRUMF 6
SCR 0x5C 32 RTC status Clear register
RTC_SCR_CALRAF 0
RTC_SCR_CALRBF 1
RTC_SCR_CWUTF 2
RTC_SCR_CTSF 3
RTC_SCR_CTSOVF 4
RTC_SCR_CITSF 5
RTC_SCR_CSSRUF 6
ALRABINR 0x70 32 RTC alarm A binary mode register
RTC_ALRABINR_SS 0:31
ALRBBINR 0x74 32 RTC alarm B binary mode register
RTC_ALRBBINR_SS 0:31

TAMP — Вскрытие корпуса и резервные регистры (раздел 12)

Регистр Смещение Бит Назначение
CR1 0x00 32 TAMP configuration register 1
TAMP_CR1_TAMP1E 0
TAMP_CR1_TAMP2E 1
TAMP_CR1_TAMP3E 2
TAMP_CR1_ITAMP6E 17
TAMP_CR1_ITAMP3E 18
TAMP_CR1_ITAMP5E 20
TAMP_CR1_ITAMP8E 23
CR2 0x04 32 TAMP configuration register 2
TAMP_CR2_TAMP1NOERASE 0
TAMP_CR2_TAMP2NOERASE 1
TAMP_CR2_TAMP3NOERASE 2
TAMP_CR2_TAMP1MSK 16
TAMP_CR2_TAMP2MSK 17
TAMP_CR2_TAMP3MSK 18
TAMP_CR2_BKERASE 23
TAMP_CR2_TAMP1TRG 24
TAMP_CR2_TAMP2TRG 25
TAMP_CR2_TAMP3TRG 25
CR3 0x08 32 TAMP configuration register 3
TAMP_CR3_ITAMP3NOER 2
TAMP_CR3_ITAMP5NOER 4
TAMP_CR3_ITAMP6NOER 5
TAMP_CR3_ITAMP8NOER 23
FLTCR 0x0C 32 TAMP filter control register
TAMP_FLTCR_TAMPFREQ 0:2
TAMP_FLTCR_TAMPFLT 3:4
TAMP_FLTCR_TAMPPRCH 5:6
TAMP_FLTCR_TAMPPUDIS 7
IER 0x2C 32 TAMP interrupt enable register
TAMP_IER_TAMP1IE 0
TAMP_IER_TAMP2IE 1
TAMP_IER_TAMP3IE 2
TAMP_IER_ITAMP6IE 17
TAMP_IER_ITAMP3IE 18
TAMP_IER_ITAMP5IE 20
TAMP_IER_ITAMP8IE 23
SR 0x30 32 TAMP status register
TAMP_SR_TAMP1F 0
TAMP_SR_TAMP2F 1
TAMP_SR_TAMP3F 2
TAMP_SR_ITAMP6F 17
TAMP_SR_ITAMP3F 18
TAMP_SR_ITAMP5F 20
TAMP_SR_ITAMP8F 23
MISR 0x34 32 TAMP masked interrupt status register
TAMP_MISR_TAMP1MF 0
TAMP_MISR_TAMP2MF 1
TAMP_MISR_TAMP3MF 2
TAMP_MISR_ITAMP6MF 17
TAMP_MISR_ITAMP3MF 18
TAMP_MISR_ITAMP5MF 20
TAMP_MISR_ITAMP8MF 23
SCR 0x3C 32 TAMP status clear register
TAMP_SCR_CTAMP1F 0
TAMP_SCR_CTAMP2F 1
TAMP_SCR_CTAMP3F 2
TAMP_SCR_CITAMP6F 17
TAMP_SCR_CITAMP3F 18
TAMP_SCR_CITAMP5F 20
TAMP_SCR_CITAMP8F 23
COUNTR 0x40 32 TAMP monotonic counter register
BKP0R 0x100 32 TAMP backup register 0
BKP1R 0x104 32 TAMP backup register 1
BKP2R 0x108 32 TAMP backup register 2
BKP3R 0x10C 32 TAMP backup register 3
BKP4R 0x110 32 TAMP backup register 4
BKP5R 0x114 32 TAMP backup register 5
BKP6R 0x118 32 TAMP backup register 6
BKP7R 0x11C 32 TAMP backup register 7
BKP8R 0x120 32 TAMP backup register 8
BKP9R 0x124 32 TAMP backup register 9
BKP10R 0x128 32 TAMP backup register 10
BKP11R 0x12C 32 TAMP backup register 11
BKP12R 0x130 32 TAMP backup register 12
BKP13R 0x134 32 TAMP backup register 13
BKP14R 0x138 32 TAMP backup register 14
BKP15R 0x13C 32 TAMP backup register 15
BKP16R 0x140 32 TAMP backup register 16
BKP17R 0x144 32 TAMP backup register 17
BKP18R 0x148 32 TAMP backup register 18
BKP19R 0x14C 32 TAMP backup register 19

TIM — Таймеры (раздел 13)

Регистр Смещение Бит Назначение
CR1 0x00 32 TIM control register 1
TIM_CR1_CEN 0 Counter enable
TIM_CR1_UDIS 1 Update disable
TIM_CR1_URS 2 Update request source
TIM_CR1_OPM 3 One pulse mode
TIM_CR1_DIR 4 Direction
TIM_CR1_CMS 5:6 CMS[1:0] bits (Center-aligned mode selection)
TIM_CR1_ARPE 7 Auto-reload preload enable
TIM_CR1_CKD 8:9 CKD[1:0] bits (clock division)
TIM_CR1_UIFREMAP 11 Update interrupt flag remap
CR2 0x04 32 TIM control register 2
TIM_CR2_CCPC 0 Capture/Compare Preloaded Control
TIM_CR2_CCUS 2 Capture/Compare Control Update Selection
TIM_CR2_CCDS 3 Capture/Compare DMA Selection
TIM_CR2_MMS 4:6 MMS[2:0] bits (Master Mode Selection)
TIM_CR2_TI1S 7 TI1 Selection
TIM_CR2_OIS1 8 Output Idle state 1 (OC1 output)
TIM_CR2_OIS1N 9 Output Idle state 1 (OC1N output)
TIM_CR2_OIS2 10 Output Idle state 2 (OC2 output)
TIM_CR2_OIS2N 11 Output Idle state 2 (OC2N output)
TIM_CR2_OIS3 12 Output Idle state 3 (OC3 output)
TIM_CR2_OIS3N 13 Output Idle state 3 (OC3N output)
TIM_CR2_OIS4 14 Output Idle state 4 (OC4 output)
TIM_CR2_OIS5 16 Output Idle state 5 (OC5 output)
TIM_CR2_OIS6 18 Output Idle state 6 (OC6 output)
TIM_CR2_MMS2 20:23 MMS[2:0] bits (Master Mode Selection)
SMCR 0x08 32 TIM slave mode control register
TIM_SMCR_SMS 0:16 SMS[2:0] bits (Slave mode selection)
TIM_SMCR_OCCS 3 OCREF clear selection
TIM_SMCR_TS 4:21 TS[2:0] bits (Trigger selection)
TIM_SMCR_MSM 7 Master/slave mode
TIM_SMCR_ETF 8:11 ETF[3:0] bits (External trigger filter)
TIM_SMCR_ETPS 12:13 ETPS[1:0] bits (External trigger prescaler)
TIM_SMCR_ECE 14 External clock enable
TIM_SMCR_ETP 15 External trigger polarity
DIER 0x0C 32 TIM DMA/interrupt enable register
TIM_DIER_UIE 0 Update interrupt enable
TIM_DIER_CC1IE 1 Capture/Compare 1 interrupt enable
TIM_DIER_CC2IE 2 Capture/Compare 2 interrupt enable
TIM_DIER_CC3IE 3 Capture/Compare 3 interrupt enable
TIM_DIER_CC4IE 4 Capture/Compare 4 interrupt enable
TIM_DIER_COMIE 5 COM interrupt enable
TIM_DIER_TIE 6 Trigger interrupt enable
TIM_DIER_BIE 7 Break interrupt enable
TIM_DIER_UDE 8 Update DMA request enable
TIM_DIER_CC1DE 9 Capture/Compare 1 DMA request enable
TIM_DIER_CC2DE 10 Capture/Compare 2 DMA request enable
TIM_DIER_CC3DE 11 Capture/Compare 3 DMA request enable
TIM_DIER_CC4DE 12 Capture/Compare 4 DMA request enable
TIM_DIER_COMDE 13 COM DMA request enable
TIM_DIER_TDE 14 Trigger DMA request enable
SR 0x10 32 TIM status register
TIM_SR_UIF 0 Update interrupt Flag
TIM_SR_CC1IF 1 Capture/Compare 1 interrupt Flag
TIM_SR_CC2IF 2 Capture/Compare 2 interrupt Flag
TIM_SR_CC3IF 3 Capture/Compare 3 interrupt Flag
TIM_SR_CC4IF 4 Capture/Compare 4 interrupt Flag
TIM_SR_COMIF 5 COM interrupt Flag
TIM_SR_TIF 6 Trigger interrupt Flag
TIM_SR_BIF 7 Break interrupt Flag
TIM_SR_B2IF 8 Break 2 interrupt Flag
TIM_SR_CC1OF 9 Capture/Compare 1 Overcapture Flag
TIM_SR_CC2OF 10 Capture/Compare 2 Overcapture Flag
TIM_SR_CC3OF 11 Capture/Compare 3 Overcapture Flag
TIM_SR_CC4OF 12 Capture/Compare 4 Overcapture Flag
TIM_SR_SBIF 13 System Break interrupt Flag
TIM_SR_CC5IF 16 Capture/Compare 5 interrupt Flag
TIM_SR_CC6IF 17 Capture/Compare 6 interrupt Flag
EGR 0x14 32 TIM event generation register
TIM_EGR_UG 0 Update Generation
TIM_EGR_CC1G 1 Capture/Compare 1 Generation
TIM_EGR_CC2G 2 Capture/Compare 2 Generation
TIM_EGR_CC3G 3 Capture/Compare 3 Generation
TIM_EGR_CC4G 4 Capture/Compare 4 Generation
TIM_EGR_COMG 5 Capture/Compare Control Update Generation
TIM_EGR_TG 6 Trigger Generation
TIM_EGR_BG 7 Break Generation
TIM_EGR_B2G 8 Break 2 Generation
CCMR1 0x18 32 TIM capture/compare mode register 1
TIM_CCMR1_CC1S 0:1 CC1S[1:0] bits (Capture/Compare 1 Selection)
TIM_CCMR1_OC1FE 2 Output Compare 1 Fast enable
TIM_CCMR1_IC1PSC 2:3 IC1PSC[1:0] bits (Input Capture 1 Prescaler)
TIM_CCMR1_OC1PE 3 Output Compare 1 Preload enable
TIM_CCMR1_OC1M 4:16 OC1M[2:0] bits (Output Compare 1 Mode)
TIM_CCMR1_IC1F 4:7 IC1F[3:0] bits (Input Capture 1 Filter)
TIM_CCMR1_OC1CE 7 Output Compare 1 Clear Enable
TIM_CCMR1_CC2S 8:9 CC2S[1:0] bits (Capture/Compare 2 Selection)
TIM_CCMR1_OC2FE 10 Output Compare 2 Fast enable
TIM_CCMR1_IC2PSC 10:11 IC2PSC[1:0] bits (Input Capture 2 Prescaler)
TIM_CCMR1_OC2PE 11 Output Compare 2 Preload enable
TIM_CCMR1_OC2M 12:24 OC2M[2:0] bits (Output Compare 2 Mode)
TIM_CCMR1_IC2F 12:15 IC2F[3:0] bits (Input Capture 2 Filter)
TIM_CCMR1_OC2CE 15 Output Compare 2 Clear Enable
CCMR2 0x1C 32 TIM capture/compare mode register 2
TIM_CCMR2_CC3S 0:1 CC3S[1:0] bits (Capture/Compare 3 Selection)
TIM_CCMR2_OC3FE 2 Output Compare 3 Fast enable
TIM_CCMR2_IC3PSC 2:3 IC3PSC[1:0] bits (Input Capture 3 Prescaler)
TIM_CCMR2_OC3PE 3 Output Compare 3 Preload enable
TIM_CCMR2_OC3M 4:16 OC3M[2:0] bits (Output Compare 3 Mode)
TIM_CCMR2_IC3F 4:7 IC3F[3:0] bits (Input Capture 3 Filter)
TIM_CCMR2_OC3CE 7 Output Compare 3 Clear Enable
TIM_CCMR2_CC4S 8:9 CC4S[1:0] bits (Capture/Compare 4 Selection)
TIM_CCMR2_OC4FE 10 Output Compare 4 Fast enable
TIM_CCMR2_IC4PSC 10:11 IC4PSC[1:0] bits (Input Capture 4 Prescaler)
TIM_CCMR2_OC4PE 11 Output Compare 4 Preload enable
TIM_CCMR2_OC4M 12:24 OC4M[2:0] bits (Output Compare 4 Mode)
TIM_CCMR2_IC4F 12:15 IC4F[3:0] bits (Input Capture 4 Filter)
TIM_CCMR2_OC4CE 15 Output Compare 4 Clear Enable
CCER 0x20 32 TIM capture/compare enable register
TIM_CCER_CC1E 0 Capture/Compare 1 output enable
TIM_CCER_CC1P 1 Capture/Compare 1 output Polarity
TIM_CCER_CC1NE 2 Capture/Compare 1 Complementary output enable
TIM_CCER_CC1NP 3 Capture/Compare 1 Complementary output Polarity
TIM_CCER_CC2E 4 Capture/Compare 2 output enable
TIM_CCER_CC2P 5 Capture/Compare 2 output Polarity
TIM_CCER_CC2NE 6 Capture/Compare 2 Complementary output enable
TIM_CCER_CC2NP 7 Capture/Compare 2 Complementary output Polarity
TIM_CCER_CC3E 8 Capture/Compare 3 output enable
TIM_CCER_CC3P 9 Capture/Compare 3 output Polarity
TIM_CCER_CC3NE 10 Capture/Compare 3 Complementary output enable
TIM_CCER_CC3NP 11 Capture/Compare 3 Complementary output Polarity
TIM_CCER_CC4E 12 Capture/Compare 4 output enable
TIM_CCER_CC4P 13 Capture/Compare 4 output Polarity
TIM_CCER_CC4NP 15 Capture/Compare 4 Complementary output Polarity
TIM_CCER_CC5E 16 Capture/Compare 5 output enable
TIM_CCER_CC5P 17 Capture/Compare 5 output Polarity
TIM_CCER_CC6E 20 Capture/Compare 6 output enable
TIM_CCER_CC6P 21 Capture/Compare 6 output Polarity
CNT 0x24 32 TIM counter register
TIM_CNT_CNT 0:31 Counter Value
TIM_CNT_UIFCPY 31 Update interrupt flag copy (if UIFREMAP=1)
PSC 0x28 32 TIM prescaler register
TIM_PSC_PSC 0:15 Prescaler Value
ARR 0x2C 32 TIM auto-reload register
TIM_ARR_ARR 0:31 Actual auto-reload Value
RCR 0x30 32 TIM repetition counter register
TIM_RCR_REP 0:15 Repetition Counter Value
CCR1 0x34 32 TIM capture/compare register 1
TIM_CCR1_CCR1 0:31 Capture/Compare 1 Value
CCR2 0x38 32 TIM capture/compare register 2
TIM_CCR2_CCR2 0:31 Capture/Compare 2 Value
CCR3 0x3C 32 TIM capture/compare register 3
TIM_CCR3_CCR3 0:31 Capture/Compare 3 Value
CCR4 0x40 32 TIM capture/compare register 4
TIM_CCR4_CCR4 0:31 Capture/Compare 4 Value
BDTR 0x44 32 TIM break and dead-time register
TIM_BDTR_DTG 0:7 DTG[0:7] bits (Dead-Time Generator set-up)
TIM_BDTR_LOCK 8:9 LOCK[1:0] bits (Lock Configuration)
TIM_BDTR_OSSI 10 Off-State Selection for Idle mode
TIM_BDTR_OSSR 11 Off-State Selection for Run mode
TIM_BDTR_BKE 12 Break enable for Break 1
TIM_BDTR_BKP 13 Break Polarity for Break 1
TIM_BDTR_AOE 14 Automatic Output enable
TIM_BDTR_MOE 15 Main Output enable
TIM_BDTR_BKF 16:19 Break Filter for Break 1
TIM_BDTR_BK2F 20:23 Break Filter for Break 2
TIM_BDTR_BK2E 24 Break enable for Break 2
TIM_BDTR_BK2P 25 Break Polarity for Break 2
TIM_BDTR_BKDSRM 26 Break disarming/re-arming
TIM_BDTR_BK2DSRM 27 Break2 disarming/re-arming
TIM_BDTR_BKBID 28 Break BIDirectional
TIM_BDTR_BK2BID 29 Break2 BIDirectional
DCR 0x48 32 TIM DMA control register
TIM_DCR_DBA 0:4 DBA[4:0] bits (DMA Base Address)
TIM_DCR_DBL 8:12 DBL[4:0] bits (DMA Burst Length)
DMAR 0x4C 32 TIM DMA address for full transfer
TIM_DMAR_DMAB 0:15 DMA register for burst accesses
OR1 0x50 32 TIM option register
CCMR3 0x54 32 TIM capture/compare mode register 3
TIM_CCMR3_OC5FE 2 Output Compare 5 Fast enable
TIM_CCMR3_OC5PE 3 Output Compare 5 Preload enable
TIM_CCMR3_OC5M 4:16 OC5M[3:0] bits (Output Compare 5 Mode)
TIM_CCMR3_OC5CE 7 Output Compare 5 Clear Enable
TIM_CCMR3_OC6FE 10 Output Compare 6 Fast enable
TIM_CCMR3_OC6PE 11 Output Compare 6 Preload enable
TIM_CCMR3_OC6M 12:24 OC6M[3:0] bits (Output Compare 6 Mode)
TIM_CCMR3_OC6CE 15 Output Compare 6 Clear Enable
CCR5 0x58 32 TIM capture/compare register5
TIM_CCR5_CCR5 0:15 Capture/Compare 5 Value
TIM_CCR5_GC5C1 29 Group Channel 5 and Channel 1
TIM_CCR5_GC5C2 30 Group Channel 5 and Channel 2
TIM_CCR5_GC5C3 31 Group Channel 5 and Channel 3
CCR6 0x5C 32 TIM capture/compare register6
TIM_CCR6_CCR6 0:15 Capture/Compare 6 Value
AF1 0x60 32 TIM Alternate function option register 1
AF2 0x64 32 TIM Alternate function option register 2

LPTIM — Таймер с малым потреблением (раздел 46)

Регистр Смещение Бит Назначение
ISR 0x00 32 LPTIM Interrupt and Status register
LPTIM_ISR_CMPM 0 Compare match
LPTIM_ISR_ARRM 1 Autoreload match
LPTIM_ISR_EXTTRIG 2 External trigger edge event
LPTIM_ISR_CMPOK 3 Compare register update OK
LPTIM_ISR_ARROK 4 Autoreload register update OK
LPTIM_ISR_UP 5 Counter direction change down to up
LPTIM_ISR_DOWN 6 Counter direction change up to down
LPTIM_ISR_UE 7 Update event occurrence
LPTIM_ISR_REPOK 8 Repetition register update OK
ICR 0x04 32 LPTIM Interrupt Clear register
LPTIM_ICR_CMPMCF 0 Compare match Clear Flag
LPTIM_ICR_ARRMCF 1 Autoreload match Clear Flag
LPTIM_ICR_EXTTRIGCF 2 External trigger edge event Clear Flag
LPTIM_ICR_CMPOKCF 3 Compare register update OK Clear Flag
LPTIM_ICR_ARROKCF 4 Autoreload register update OK Clear Flag
LPTIM_ICR_UPCF 5 Counter direction change down to up Clear Flag
LPTIM_ICR_DOWNCF 6 Counter direction change up to down Clear Flag
LPTIM_ICR_UECF 7 Update event Clear Flag
LPTIM_ICR_REPOKCF 8 Repetition register update OK Clear Flag
IER 0x08 32 LPTIM Interrupt Enable register
LPTIM_IER_CMPMIE 0 Compare match Interrupt Enable
LPTIM_IER_ARRMIE 1 Autoreload match Interrupt Enable
LPTIM_IER_EXTTRIGIE 2 External trigger edge event Interrupt Enable
LPTIM_IER_CMPOKIE 3 Compare register update OK Interrupt Enable
LPTIM_IER_ARROKIE 4 Autoreload register update OK Interrupt Enable
LPTIM_IER_UPIE 5 Counter direction change down to up Interrupt Enable
LPTIM_IER_DOWNIE 6 Counter direction change up to down Interrupt Enable
LPTIM_IER_UEIE 7 Update event Interrupt Enable
LPTIM_IER_REPOKIE 8 Repetition register update OK Interrupt Enable
CFGR 0x0C 32 LPTIM Configuration register
LPTIM_CFGR_CKSEL 0 Clock selector
LPTIM_CFGR_CKPOL 1:2 CKPOL[1:0] bits (Clock polarity)
LPTIM_CFGR_CKFLT 3:4 CKFLT[1:0] bits (Configurable digital filter for external clock)
LPTIM_CFGR_TRGFLT 6:7 TRGFLT[1:0] bits (Configurable digital filter for trigger)
LPTIM_CFGR_PRESC 9:11 PRESC[2:0] bits (Clock prescaler)
LPTIM_CFGR_TRIGSEL 13:15 TRIGSEL[2:0]] bits (Trigger selector)
LPTIM_CFGR_TRIGEN 17:18 TRIGEN[1:0] bits (Trigger enable and polarity)
LPTIM_CFGR_TIMOUT 19 Timout enable
LPTIM_CFGR_WAVE 20 Waveform shape
LPTIM_CFGR_WAVPOL 21 Waveform shape polarity
LPTIM_CFGR_PRELOAD 22 Reg update mode
LPTIM_CFGR_COUNTMODE 23 Counter mode enable
LPTIM_CFGR_ENC 24 Encoder mode enable
CR 0x10 32 LPTIM Control register
LPTIM_CR_ENABLE 0 LPTIMer enable
LPTIM_CR_SNGSTRT 1 Timer start in single mode
LPTIM_CR_CNTSTRT 2 Timer start in continuous mode
LPTIM_CR_COUNTRST 3 Counter reset
LPTIM_CR_RSTARE 4 Reset after read enable
CMP 0x14 32 LPTIM Compare register
LPTIM_CMP_CMP 0:15 Compare register
ARR 0x18 32 LPTIM Autoreload register
LPTIM_ARR_ARR 0:15 Auto reload register
CNT 0x1C 32 LPTIM Counter register
LPTIM_CNT_CNT 0:15 Counter register
OR 0x20 32 LPTIM Option register
LPTIM_OR_OR 0:1 OR[1:0] bits (Remap selection)
RCR 0x28 32 LPTIM repetition register
LPTIM_RCR_REP 0:7 Repetition Counter Value

ADC — АЦП (раздел 14)

Регистр Смещение Бит Назначение
ISR 0x00 32 ADC interrupt and status register
ADC_ISR_ADRDY 0 ADC ready flag
ADC_ISR_EOSMP 1 ADC group regular end of sampling flag
ADC_ISR_EOC 2 ADC group regular end of unitary conversion flag
ADC_ISR_EOS 3 ADC group regular end of sequence conversions flag
ADC_ISR_OVR 4 ADC group regular overrun flag
ADC_ISR_AWD1 7 ADC analog watchdog 1 flag
ADC_ISR_AWD2 8 ADC analog watchdog 2 flag
ADC_ISR_AWD3 9 ADC analog watchdog 3 flag
ADC_ISR_EOCAL 11 ADC end of calibration flag
ADC_ISR_CCRDY 13 ADC channel configuration ready flag
IER 0x04 32 ADC interrupt enable register
ADC_IER_ADRDYIE 0 ADC ready interrupt
ADC_IER_EOSMPIE 1 ADC group regular end of sampling interrupt
ADC_IER_EOCIE 2 ADC group regular end of unitary conversion interrupt
ADC_IER_EOSIE 3 ADC group regular end of sequence conversions interrupt
ADC_IER_OVRIE 4 ADC group regular overrun interrupt
ADC_IER_AWD1IE 7 ADC analog watchdog 1 interrupt
ADC_IER_AWD2IE 8 ADC analog watchdog 2 interrupt
ADC_IER_AWD3IE 9 ADC analog watchdog 3 interrupt
ADC_IER_EOCALIE 11 ADC end of calibration interrupt
ADC_IER_CCRDYIE 13 ADC channel configuration ready interrupt
CR 0x08 32 ADC control register
ADC_CR_ADEN 0 ADC enable
ADC_CR_ADDIS 1 ADC disable
ADC_CR_ADSTART 2 ADC group regular conversion start
ADC_CR_ADSTP 4 ADC group regular conversion stop
ADC_CR_ADVREGEN 28 ADC voltage regulator enable
ADC_CR_ADCAL 31 ADC calibration
CFGR1 0x0C 32 ADC configuration register 1
ADC_CFGR1_DMAEN 0 ADC DMA transfer enable
ADC_CFGR1_DMACFG 1 ADC DMA transfer configuration
ADC_CFGR1_SCANDIR 2 ADC group regular sequencer scan direction
ADC_CFGR1_RES 3:4 ADC data resolution
ADC_CFGR1_ALIGN 5 ADC data alignment
ADC_CFGR1_EXTSEL 6:8 ADC group regular external trigger source
ADC_CFGR1_EXTEN 10:11 ADC group regular external trigger polarity
ADC_CFGR1_OVRMOD 12 ADC group regular overrun configuration
ADC_CFGR1_CONT 13 ADC group regular continuous conversion mode
ADC_CFGR1_WAIT 14 ADC low power auto wait
ADC_CFGR1_AUTOFF 15 ADC low power auto power off
ADC_CFGR1_DISCEN 16 ADC group regular sequencer discontinuous mode
ADC_CFGR1_CHSELRMOD 21 ADC group regular sequencer mode
ADC_CFGR1_AWD1SGL 22 ADC analog watchdog 1 monitoring a single channel or all channels
ADC_CFGR1_AWD1EN 23 ADC analog watchdog 1 enable on scope ADC group regular
ADC_CFGR1_AWD1CH 26:30 ADC analog watchdog 1 monitored channel selection
CFGR2 0x10 32 ADC configuration register 2
ADC_CFGR2_OVSE 0 ADC oversampler enable on scope ADC group regular
ADC_CFGR2_OVSR 2:4 ADC oversampling ratio
ADC_CFGR2_OVSS 5:8 ADC oversampling shift
ADC_CFGR2_TOVS 9 ADC oversampling discontinuous mode (triggered mode) for ADC group regular
ADC_CFGR2_LFTRIG 29 ADC low frequency trigger mode
ADC_CFGR2_CKMODE 30:31 ADC clock source and prescaler (prescaler only for clock source synchronous)
SMPR 0x14 32 ADC sampling time register
ADC_SMPR_SMP1 0:2 ADC group of channels sampling time 1
ADC_SMPR_SMP2 4:6 ADC group of channels sampling time 2
ADC_SMPR_SMPSEL 8:25 ADC all channels sampling time selection
ADC_SMPR_SMPSEL0 8 ADC channel 0 sampling time selection
ADC_SMPR_SMPSEL1 9 ADC channel 1 sampling time selection
ADC_SMPR_SMPSEL2 10 ADC channel 2 sampling time selection
ADC_SMPR_SMPSEL3 11 ADC channel 3 sampling time selection
ADC_SMPR_SMPSEL4 12 ADC channel 4 sampling time selection
ADC_SMPR_SMPSEL5 13 ADC channel 5 sampling time selection
ADC_SMPR_SMPSEL6 14 ADC channel 6 sampling time selection
ADC_SMPR_SMPSEL7 15 ADC channel 7 sampling time selection
ADC_SMPR_SMPSEL8 16 ADC channel 8 sampling time selection
ADC_SMPR_SMPSEL9 17 ADC channel 9 sampling time selection
ADC_SMPR_SMPSEL10 18 ADC channel 10 sampling time selection
ADC_SMPR_SMPSEL11 19 ADC channel 11 sampling time selection
ADC_SMPR_SMPSEL12 20 ADC channel 12 sampling time selection
ADC_SMPR_SMPSEL13 21 ADC channel 13 sampling time selection
ADC_SMPR_SMPSEL14 22 ADC channel 14 sampling time selection
ADC_SMPR_SMPSEL15 23 ADC channel 15 sampling time selection
ADC_SMPR_SMPSEL16 24 ADC channel 16 sampling time selection
ADC_SMPR_SMPSEL17 25 ADC channel 17 sampling time selection
AWD1TR 0x20 32 ADC analog watchdog 1 threshold register
ADC_AWD1TR_LT1 0:11 ADC analog watchdog 1 threshold low
ADC_AWD1TR_HT1 16:27 ADC Analog watchdog 1 threshold high
AWD2TR 0x24 32 ADC analog watchdog 2 threshold register
ADC_AWD2TR_LT2 0:11 ADC analog watchdog 2 threshold low
ADC_AWD2TR_HT2 16:27 ADC analog watchdog 2 threshold high
CHSELR 0x28 32 ADC group regular sequencer register
ADC_CHSELR_CHSEL 0:17 ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL0 0 ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_SQ_ALL 0:31 ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set
ADC_CHSELR_SQ1 0:3 ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set
ADC_CHSELR_CHSEL1 1 ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL2 2 ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL3 3 ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL4 4 ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_SQ2 4:7 ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set
ADC_CHSELR_CHSEL5 5 ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL6 6 ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL7 7 ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL8 8 ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_SQ3 8:11 ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set
ADC_CHSELR_CHSEL9 9 ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL10 10 ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL11 11 ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL12 12 ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_SQ4 12:15 ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set
ADC_CHSELR_CHSEL13 13 ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL14 14 ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL15 15 ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_CHSEL16 16 ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_SQ5 16:19 ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set
ADC_CHSELR_CHSEL17 17 ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset
ADC_CHSELR_SQ6 20:23 ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set
ADC_CHSELR_SQ7 24:27 ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set
ADC_CHSELR_SQ8 28:31 ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set
AWD3TR 0x2C 32 ADC analog watchdog 3 threshold register
ADC_AWD3TR_LT3 0:11 ADC analog watchdog 3 threshold low
ADC_AWD3TR_HT3 16:27 ADC analog watchdog 3 threshold high
DR 0x40 32 ADC group regular data register
ADC_DR_DATA 0:15 ADC group regular conversion data
AWD2CR 0xA0 32 ADC analog watchdog 2 configuration register
ADC_AWD2CR_AWD2CH 0:17 ADC analog watchdog 2 monitored channel selection
AWD3CR 0xA4 32 ADC analog watchdog 3 configuration register
ADC_AWD3CR_AWD3CH 0:17 ADC analog watchdog 3 monitored channel selection
CALFACT 0xB4 32 ADC Calibration factor register
ADC_CALFACT_CALFACT 0:6 ADC calibration factor in single-ended mode

ADC_Common — АЦП: общие регистры (раздел 14)

Регистр Смещение Бит Назначение
CCR 0x00 32 ADC common configuration register
ADC_CCR_PRESC 18:21 ADC common clock prescaler, only for clock source asynchronous
ADC_CCR_VREFEN 22 ADC internal path to VrefInt enable
ADC_CCR_TSEN 23 ADC internal path to temperature sensor enable
ADC_CCR_VBATEN 24 ADC internal path to battery voltage enable

DAC — ЦАП (раздел 15)

Регистр Смещение Бит Назначение
CR 0x00 32 DAC control register
DAC_CR_EN1 0 DAC channel1 enable
DAC_CR_TEN1 1 DAC channel1 Trigger enable
DAC_CR_TSEL1 2:5 TSEL1[3:0] (DAC channel1 Trigger selection)
DAC_CR_WAVE1 6:7 WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
DAC_CR_MAMP1 8:11 MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
DAC_CR_DMAEN1 12 DAC channel1 DMA enable
DAC_CR_DMAUDRIE1 13 DAC channel 1 DMA underrun interrupt enable >
DAC_CR_CEN1 14 DAC channel 1 calibration enable >
SWTRIGR 0x04 32 DAC software trigger register
DAC_SWTRIGR_SWTRIG1 0 DAC channel1 software trigger
DHR12R1 0x08 32 DAC channel1 12-bit right-aligned data holding register
DAC_DHR12R1_DACC1DHR 0:11 DAC channel1 12-bit Right aligned data
DHR12L1 0x0C 32 DAC channel1 12-bit left aligned data holding register
DAC_DHR12L1_DACC1DHR 4:15 DAC channel1 12-bit Left aligned data
DHR8R1 0x10 32 DAC channel1 8-bit right aligned data holding register
DAC_DHR8R1_DACC1DHR 0:7 DAC channel1 8-bit Right aligned data
DHR12RD 0x20 32 Dual DAC 12-bit right-aligned data holding register
DAC_DHR12RD_DACC1DHR 0:11 DAC channel1 12-bit Right aligned data
DHR12LD 0x24 32 DUAL DAC 12-bit left aligned data holding register
DAC_DHR12LD_DACC1DHR 4:15 DAC channel1 12-bit Left aligned data
DHR8RD 0x28 32 DUAL DAC 8-bit right aligned data holding register
DAC_DHR8RD_DACC1DHR 0:7 DAC channel1 8-bit Right aligned data
DOR1 0x2C 32 DAC channel1 data output register
DAC_DOR1_DACC1DOR 0:11 DAC channel1 data output
SR 0x34 32 DAC status register
DAC_SR_DMAUDR1 13 DAC channel1 DMA underrun flag
DAC_SR_CAL_FLAG1 14 DAC channel1 calibration offset status
DAC_SR_BWST1 15 DAC channel1 busy writing sample time flag
CCR 0x38 32 DAC calibration control register
DAC_CCR_OTRIM1 0:4 DAC channel1 offset trimming value
MCR 0x3C 32 DAC mode control register
DAC_MCR_MODE1 0:2 MODE1[2:0] (DAC channel1 mode)
SHSR1 0x40 32 DAC Sample and Hold sample time register 1
DAC_SHSR1_TSAMPLE1 0:9 DAC channel1 sample time
SHHR 0x48 32 DAC Sample and Hold hold time register
DAC_SHHR_THOLD1 0:9 DAC channel1 hold time
SHRR 0x4C 32 DAC Sample and Hold refresh time register
DAC_SHRR_TREFRESH1 0:7 DAC channel1 refresh time

COMP — Компаратор (раздел 44)

Регистр Смещение Бит Назначение
CSR 0x00 32 COMP control and status register
COMP_CSR_EN 0 Comparator enable
COMP_CSR_PWRMODE 2:3 Comparator power mode
COMP_CSR_INMSEL 4:6 Comparator input minus selection
COMP_CSR_INPSEL 7:8 Comparator input plus selection
COMP_CSR_WINMODE 9 Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)
COMP_CSR_POLARITY 15 Comparator output polarity
COMP_CSR_HYST 16:17 Comparator hysteresis
COMP_CSR_BLANKING 18:20 Comparator blanking source
COMP_CSR_BRGEN 22 Comparator voltage scaler enable
COMP_CSR_SCALEN 23 Comparator scaler bridge enable
COMP_CSR_INMESEL 25:26 Comparator input minus extended selection
COMP_CSR_VALUE 30 Comparator output level
COMP_CSR_LOCK 31 Comparator lock

USART — UART / USART / LPUART (раздел 16)

Регистр Смещение Бит Назначение
CR1 0x00 32 USART Control register 1
USART_CR1_UE 0 USART Enable
USART_CR1_UESM 1 USART Enable in STOP Mode
USART_CR1_RE 2 Receiver Enable
USART_CR1_TE 3 Transmitter Enable
USART_CR1_IDLEIE 4 IDLE Interrupt Enable
USART_CR1_RXNEIE_RXFNEIE 5 RXNE/RXFIFO not empty Interrupt Enable
USART_CR1_TCIE 6 Transmission Complete Interrupt Enable
USART_CR1_TXEIE_TXFNFIE 7 TXE/TXFIFO not full Interrupt Enable
USART_CR1_PEIE 8 PE Interrupt Enable
USART_CR1_PS 9 Parity Selection
USART_CR1_PCE 10 Parity Control Enable
USART_CR1_WAKE 11 Receiver Wakeup method
USART_CR1_M 12:28 Word length
USART_CR1_M0 12 Word length - Bit 0
USART_CR1_MME 13 Mute Mode Enable
USART_CR1_CMIE 14 Character match interrupt enable
USART_CR1_OVER8 15 Oversampling by 8-bit or 16-bit mode
USART_CR1_DEDT 16:20 DEDT[4:0] bits (Driver Enable Deassertion Time)
USART_CR1_DEAT 21:25 DEAT[4:0] bits (Driver Enable Assertion Time)
USART_CR1_RTOIE 26 Receive Time Out interrupt enable
USART_CR1_EOBIE 27 End of Block interrupt enable
USART_CR1_M1 28 Word length - Bit 1
USART_CR1_FIFOEN 29 FIFO mode enable
USART_CR1_TXFEIE 30 TXFIFO empty interrupt enable
USART_CR1_RXFFIE 31 RXFIFO Full interrupt enable
CR2 0x04 32 USART Control register 2
USART_CR2_SLVEN 0 Synchronous Slave mode enable
USART_CR2_DIS_NSS 3 NSS input pin disable for SPI slave selection
USART_CR2_ADDM7 4 7-bit or 4-bit Address Detection
USART_CR2_LBDL 5 LIN Break Detection Length
USART_CR2_LBDIE 6 LIN Break Detection Interrupt Enable
USART_CR2_LBCL 8 Last Bit Clock pulse
USART_CR2_CPHA 9 Clock Phase
USART_CR2_CPOL 10 Clock Polarity
USART_CR2_CLKEN 11 Clock Enable
USART_CR2_STOP 12:13 STOP[1:0] bits (STOP bits)
USART_CR2_LINEN 14 LIN mode enable
USART_CR2_SWAP 15 SWAP TX/RX pins
USART_CR2_RXINV 16 RX pin active level inversion
USART_CR2_TXINV 17 TX pin active level inversion
USART_CR2_DATAINV 18 Binary data inversion
USART_CR2_MSBFIRST 19 Most Significant Bit First
USART_CR2_ABREN 20 Auto Baud-Rate Enable
USART_CR2_ABRMODE 21:22 ABRMOD[1:0] bits (Auto Baud-Rate Mode)
USART_CR2_RTOEN 23 Receiver Time-Out enable
USART_CR2_ADD 24:31 Address of the USART node
CR3 0x08 32 USART Control register 3
USART_CR3_EIE 0 Error Interrupt Enable
USART_CR3_IREN 1 IrDA mode Enable
USART_CR3_IRLP 2 IrDA Low-Power
USART_CR3_HDSEL 3 Half-Duplex Selection
USART_CR3_NACK 4 SmartCard NACK enable
USART_CR3_SCEN 5 SmartCard mode enable
USART_CR3_DMAR 6 DMA Enable Receiver
USART_CR3_DMAT 7 DMA Enable Transmitter
USART_CR3_RTSE 8 RTS Enable
USART_CR3_CTSE 9 CTS Enable
USART_CR3_CTSIE 10 CTS Interrupt Enable
USART_CR3_ONEBIT 11 One sample bit method enable
USART_CR3_OVRDIS 12 Overrun Disable
USART_CR3_DDRE 13 DMA Disable on Reception Error
USART_CR3_DEM 14 Driver Enable Mode
USART_CR3_DEP 15 Driver Enable Polarity Selection
USART_CR3_SCARCNT 17:19 SCARCNT[2:0] bits (SmartCard Auto-Retry Count)
USART_CR3_WUS 20:21 WUS[1:0] bits (Wake UP Interrupt Flag Selection)
USART_CR3_WUFIE 22 Wake Up Interrupt Enable
USART_CR3_TXFTIE 23 TXFIFO threshold interrupt enable
USART_CR3_TCBGTIE 24 Transmission Complete Before Guard Time Interrupt Enable
USART_CR3_RXFTCFG 25:27 RXFIFO FIFO threshold configuration
USART_CR3_RXFTIE 28 RXFIFO threshold interrupt enable
USART_CR3_TXFTCFG 29:31 TXFIFO threshold configuration
BRR 0x0C 32 USART Baud rate register
GTPR 0x10 32 USART Guard time and prescaler register
USART_GTPR_PSC 0:7 PSC[7:0] bits (Prescaler value)
USART_GTPR_GT 8:15 GT[7:0] bits (Guard time value)
RTOR 0x14 32 USART Receiver Time Out register
USART_RTOR_RTO 0:23 Receiver Time Out Value
USART_RTOR_BLEN 24:31 Block Length
RQR 0x18 32 USART Request register
ISR 0x1C 32 USART Interrupt and status register
USART_ISR_PE 0 Parity Error
USART_ISR_FE 1 Framing Error
USART_ISR_NE 2 Noise detected Flag
USART_ISR_ORE 3 OverRun Error
USART_ISR_IDLE 4 IDLE line detected
USART_ISR_RXNE_RXFNE 5 Read Data Register Not Empty/RXFIFO Not Empty
USART_ISR_TC 6 Transmission Complete
USART_ISR_TXE_TXFNF 7 Transmit Data Register Empty/TXFIFO Not Full
USART_ISR_LBDF 8 LIN Break Detection Flag
USART_ISR_CTSIF 9 CTS interrupt flag
USART_ISR_CTS 10 CTS flag
USART_ISR_RTOF 11 Receiver Time Out
USART_ISR_EOBF 12 End Of Block Flag
USART_ISR_UDR 13 SPI Slave Underrun Error Flag
USART_ISR_ABRE 14 Auto-Baud Rate Error
USART_ISR_ABRF 15 Auto-Baud Rate Flag
USART_ISR_BUSY 16 Busy Flag
USART_ISR_CMF 17 Character Match Flag
USART_ISR_SBKF 18 Send Break Flag
USART_ISR_RWU 19 Receive Wake Up from mute mode Flag
USART_ISR_WUF 20 Wake Up from stop mode Flag
USART_ISR_TEACK 21 Transmit Enable Acknowledge Flag
USART_ISR_REACK 22 Receive Enable Acknowledge Flag
USART_ISR_TXFE 23 TXFIFO Empty Flag
USART_ISR_RXFF 24 RXFIFO Full Flag
USART_ISR_TCBGT 25 Transmission Complete Before Guard Time Completion Flag
USART_ISR_RXFT 26 RXFIFO Threshold Flag
USART_ISR_TXFT 27 TXFIFO Threshold Flag
ICR 0x20 32 USART Interrupt flag Clear register
USART_ICR_PECF 0 Parity Error Clear Flag
USART_ICR_FECF 1 Framing Error Clear Flag
USART_ICR_NECF 2 Noise Error detected Clear Flag
USART_ICR_ORECF 3 OverRun Error Clear Flag
USART_ICR_IDLECF 4 IDLE line detected Clear Flag
USART_ICR_TXFECF 5 TXFIFO Empty Clear Flag
USART_ICR_TCCF 6 Transmission Complete Clear Flag
USART_ICR_TCBGTCF 7 Transmission Complete Before Guard Time Clear Flag
USART_ICR_LBDCF 8 LIN Break Detection Clear Flag
USART_ICR_CTSCF 9 CTS Interrupt Clear Flag
USART_ICR_RTOCF 11 Receiver Time Out Clear Flag
USART_ICR_EOBCF 12 End Of Block Clear Flag
USART_ICR_UDRCF 13 SPI Slave Underrun Clear Flag
USART_ICR_CMCF 17 Character Match Clear Flag
USART_ICR_WUCF 20 Wake Up from stop mode Clear Flag
RDR 0x24 32 USART Receive Data register
USART_RDR_RDR 0:8 RDR[8:0] bits (Receive Data value)
TDR 0x28 32 USART Transmit Data register
USART_TDR_TDR 0:8 TDR[8:0] bits (Transmit Data value)
PRESC 0x2C 32 USART Prescaler register
USART_PRESC_PRESCALER 0:3 PRESCALER[3:0] bits (Clock prescaler)

I2C — I²C (раздел 17)

Регистр Смещение Бит Назначение
CR1 0x00 32 I2C Control register 1
I2C_CR1_PE 0 Peripheral enable
I2C_CR1_TXIE 1 TX interrupt enable
I2C_CR1_RXIE 2 RX interrupt enable
I2C_CR1_ADDRIE 3 Address match interrupt enable
I2C_CR1_NACKIE 4 NACK received interrupt enable
I2C_CR1_STOPIE 5 STOP detection interrupt enable
I2C_CR1_TCIE 6 Transfer complete interrupt enable
I2C_CR1_ERRIE 7 Errors interrupt enable
I2C_CR1_DNF 8:11 Digital noise filter
I2C_CR1_ANFOFF 12 Analog noise filter OFF
I2C_CR1_TXDMAEN 14 DMA transmission requests enable
I2C_CR1_RXDMAEN 15 DMA reception requests enable
I2C_CR1_SBC 16 Slave byte control
I2C_CR1_NOSTRETCH 17 Clock stretching disable
I2C_CR1_WUPEN 18 Wakeup from STOP enable
I2C_CR1_GCEN 19 General call enable
I2C_CR1_SMBHEN 20 SMBus host address enable
I2C_CR1_SMBDEN 21 SMBus device default address enable
I2C_CR1_ALERTEN 22 SMBus alert enable
I2C_CR1_PECEN 23 PEC enable
CR2 0x04 32 I2C Control register 2
I2C_CR2_SADD 0:9 Slave address (master mode)
I2C_CR2_RD_WRN 10 Transfer direction (master mode)
I2C_CR2_ADD10 11 10-bit addressing mode (master mode)
I2C_CR2_HEAD10R 12 10-bit address header only read direction (master mode)
I2C_CR2_START 13 START generation
I2C_CR2_STOP 14 STOP generation (master mode)
I2C_CR2_NACK 15 NACK generation (slave mode)
I2C_CR2_NBYTES 16:23 Number of bytes
I2C_CR2_RELOAD 24 NBYTES reload mode
I2C_CR2_AUTOEND 25 Automatic end mode (master mode)
I2C_CR2_PECBYTE 26 Packet error checking byte
OAR1 0x08 32 I2C Own address 1 register
I2C_OAR1_OA1 0:9 Interface own address 1
I2C_OAR1_OA1MODE 10 Own address 1 10-bit mode
I2C_OAR1_OA1EN 15 Own address 1 enable
OAR2 0x0C 32 I2C Own address 2 register
I2C_OAR2_OA2 1:7 Interface own address 2
I2C_OAR2_OA2MSK 8:10 Own address 2 masks
I2C_OAR2_OA2MASK01 8 OA2[1] is masked, Only OA2[7:2] are compared
I2C_OAR2_OA2MASK03 8:9 OA2[3:1] is masked, Only OA2[7:4] are compared
I2C_OAR2_OA2MASK05 8:10 OA2[5:1] is masked, Only OA2[7:6] are compared
I2C_OAR2_OA2MASK07 8:10 OA2[7:1] is masked, No comparison is done
I2C_OAR2_OA2MASK02 9 OA2[2:1] is masked, Only OA2[7:3] are compared
I2C_OAR2_OA2MASK06 9:10 OA2[6:1] is masked, Only OA2[7] are compared
I2C_OAR2_OA2MASK04 10 OA2[4:1] is masked, Only OA2[7:5] are compared
I2C_OAR2_OA2EN 15 Own address 2 enable
TIMINGR 0x10 32 I2C Timing register
I2C_TIMINGR_SCLL 0:7 SCL low period (master mode)
I2C_TIMINGR_SCLH 8:15 SCL high period (master mode)
I2C_TIMINGR_SDADEL 16:19 Data hold time
I2C_TIMINGR_SCLDEL 20:23 Data setup time
I2C_TIMINGR_PRESC 28:31 Timings prescaler
TIMEOUTR 0x14 32 I2C Timeout register
I2C_TIMEOUTR_TIMEOUTA 0:11 Bus timeout A
I2C_TIMEOUTR_TIDLE 12 Idle clock timeout detection
I2C_TIMEOUTR_TIMOUTEN 15 Clock timeout enable
I2C_TIMEOUTR_TIMEOUTB 16:27 Bus timeout B
I2C_TIMEOUTR_TEXTEN 31 Extended clock timeout enable
ISR 0x18 32 I2C Interrupt and status register
I2C_ISR_TXE 0 Transmit data register empty
I2C_ISR_TXIS 1 Transmit interrupt status
I2C_ISR_RXNE 2 Receive data register not empty
I2C_ISR_ADDR 3 Address matched (slave mode)
I2C_ISR_NACKF 4 NACK received flag
I2C_ISR_STOPF 5 STOP detection flag
I2C_ISR_TC 6 Transfer complete (master mode)
I2C_ISR_TCR 7 Transfer complete reload
I2C_ISR_BERR 8 Bus error
I2C_ISR_ARLO 9 Arbitration lost
I2C_ISR_OVR 10 Overrun/Underrun
I2C_ISR_PECERR 11 PEC error in reception
I2C_ISR_TIMEOUT 12 Timeout or Tlow detection flag
I2C_ISR_ALERT 13 SMBus alert
I2C_ISR_BUSY 15 Bus busy
I2C_ISR_DIR 16 Transfer direction (slave mode)
I2C_ISR_ADDCODE 17:23 Address match code (slave mode)
ICR 0x1C 32 I2C Interrupt clear register
I2C_ICR_ADDRCF 3 Address matched clear flag
I2C_ICR_NACKCF 4 NACK clear flag
I2C_ICR_STOPCF 5 STOP detection clear flag
I2C_ICR_BERRCF 8 Bus error clear flag
I2C_ICR_ARLOCF 9 Arbitration lost clear flag
I2C_ICR_OVRCF 10 Overrun/Underrun clear flag
I2C_ICR_PECCF 11 PAC error clear flag
I2C_ICR_TIMOUTCF 12 Timeout clear flag
I2C_ICR_ALERTCF 13 Alert clear flag
PECR 0x20 32 I2C PEC register
I2C_PECR_PEC 0:7 PEC register
RXDR 0x24 32 I2C Receive data register
I2C_RXDR_RXDATA 0:7 8-bit receive data
TXDR 0x28 32 I2C Transmit data register
I2C_TXDR_TXDATA 0:7 8-bit transmit data

SPI — SPI / I²S (раздел 18)

Регистр Смещение Бит Назначение
CR1 0x00 32 SPI Control register 1 (not used in I2S mode)
SPI_CR1_CPHA 0 Clock Phase
SPI_CR1_CPOL 1 Clock Polarity
SPI_CR1_MSTR 2 Master Selection
SPI_CR1_BR 3:5 BR[2:0] bits (Baud Rate Control)
SPI_CR1_SPE 6 SPI Enable
SPI_CR1_LSBFIRST 7 Frame Format
SPI_CR1_SSI 8 Internal slave select
SPI_CR1_SSM 9 Software slave management
SPI_CR1_RXONLY 10 Receive only
SPI_CR1_CRCL 11 CRC Length
SPI_CR1_CRCNEXT 12 Transmit CRC next
SPI_CR1_CRCEN 13 Hardware CRC calculation enable
SPI_CR1_BIDIOE 14 Output enable in bidirectional mode
SPI_CR1_BIDIMODE 15 Bidirectional data mode enable
CR2 0x04 32 SPI Control register 2
SPI_CR2_RXDMAEN 0 Rx Buffer DMA Enable
SPI_CR2_TXDMAEN 1 Tx Buffer DMA Enable
SPI_CR2_SSOE 2 SS Output Enable
SPI_CR2_NSSP 3 NSS pulse management Enable
SPI_CR2_FRF 4 Frame Format Enable
SPI_CR2_ERRIE 5 Error Interrupt Enable
SPI_CR2_RXNEIE 6 RX buffer Not Empty Interrupt Enable
SPI_CR2_TXEIE 7 Tx buffer Empty Interrupt Enable
SPI_CR2_DS 8:11 DS[3:0] Data Size
SPI_CR2_FRXTH 12 FIFO reception Threshold
SPI_CR2_LDMARX 13 Last DMA transfer for reception
SPI_CR2_LDMATX 14 Last DMA transfer for transmission
SR 0x08 32 SPI Status register
SPI_SR_RXNE 0 Receive buffer Not Empty
SPI_SR_TXE 1 Transmit buffer Empty
SPI_SR_CHSIDE 2 Channel side
SPI_SR_UDR 3 Underrun flag
SPI_SR_CRCERR 4 CRC Error flag
SPI_SR_MODF 5 Mode fault
SPI_SR_OVR 6 Overrun flag
SPI_SR_BSY 7 Busy flag
SPI_SR_FRE 8 TI frame format error
SPI_SR_FRLVL 9:10 FIFO Reception Level
SPI_SR_FTLVL 11:12 FIFO Transmission Level
DR 0x0C 32 SPI data register
SPI_DR_DR 0:15 Data Register
CRCPR 0x10 32 SPI CRC polynomial register (not used in I2S mode)
SPI_CRCPR_CRCPOLY 0:15 CRC polynomial register
RXCRCR 0x14 32 SPI Rx CRC register (not used in I2S mode)
SPI_RXCRCR_RXCRC 0:15 Rx CRC Register
TXCRCR 0x18 32 SPI Tx CRC register (not used in I2S mode)
SPI_TXCRCR_TXCRC 0:15 Tx CRC Register
I2SCFGR 0x1C 32 SPI_I2S configuration register
SPI_I2SCFGR_CHLEN 0 Channel length (number of bits per audio channel)
SPI_I2SCFGR_DATLEN 1:2 DATLEN[1:0] bits (Data length to be transferred)
SPI_I2SCFGR_CKPOL 3 steady state clock polarity
SPI_I2SCFGR_I2SSTD 4:5 I2SSTD[1:0] bits (I2S standard selection)
SPI_I2SCFGR_PCMSYNC 7 PCM frame synchronization
SPI_I2SCFGR_I2SCFG 8:9 I2SCFG[1:0] bits (I2S configuration mode)
SPI_I2SCFGR_I2SE 10 I2S Enable
SPI_I2SCFGR_I2SMOD 11 I2S mode selection
SPI_I2SCFGR_ASTRTEN 12 Asynchronous start enable
I2SPR 0x20 32 SPI_I2S prescaler register
SPI_I2SPR_I2SDIV 0:7 I2S Linear prescaler
SPI_I2SPR_ODD 8 Odd factor for the prescaler
SPI_I2SPR_MCKOE 9 Master Clock Output Enable
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