STM32L053 · уровень справочник · 58 мин чтения

Приложение A12. Карты регистров STM32L0

Серия STM32L0: Cortex-M0+ до 32 МГц, малое потребление: LPUART, LPTIM, сон с часами. Регистры и биты основных блоков — из заголовка STM32L053, тем же генератором, что карты F1 и F4: смещения — по структурам *_TypeDef, назначение регистра и описание бита — из комментариев заголовка. Блоки, которых в серии нет, опущены. Для малого потребления смотрите PWR (режимы сна), RCC (генераторы LSE/LSI/MSI), LPTIM и LPUART — они работают во сне. Разделы справочника написаны для F103 и F407; имена регистров и битов у серий в основном те же — карта помогает перенести код и увидеть, что устроено иначе.

Как читать: смещение — от базового адреса блока; 31:16 — поле битов с 16 по 31; одно число — отдельный бит. Цифра в скобках у заголовка блока — раздел, где блок разобран.

Периферия STM32L053 по шинам: базы шин и смещения блоков приложения, как в окне отладчика

RCC — Тактирование (раздел 6)

Регистр	Смещение	Бит	Назначение
`CR`	`0x00`	32	RCC clock control register
`RCC_CR_HSION`		0	Internal High Speed clock enable
`RCC_CR_HSIKERON`		1	Internal High Speed clock enable for some IPs Kernel
`RCC_CR_HSIRDY`		2	Internal High Speed clock ready flag
`RCC_CR_HSIDIVEN`		3	Internal High Speed clock divider enable
`RCC_CR_HSIDIVF`		4	Internal High Speed clock divider flag
`RCC_CR_MSION`		8	Internal Multi Speed clock enable
`RCC_CR_MSIRDY`		9	Internal Multi Speed clock ready flag
`RCC_CR_HSEON`		16	External High Speed clock enable
`RCC_CR_HSERDY`		17	External High Speed clock ready flag
`RCC_CR_HSEBYP`		18	External High Speed clock Bypass
`RCC_CR_CSSHSEON`		19	HSE Clock Security System enable
`RCC_CR_RTCPRE`		20:21	RTC/LCD prescaler [1:0] bits
`RCC_CR_PLLON`		24	PLL enable
`RCC_CR_PLLRDY`		25	PLL clock ready flag
`ICSCR`	`0x04`	32	RCC Internal clock sources calibration register
`RCC_ICSCR_HSICAL`		0:7	Internal High Speed clock Calibration
`RCC_ICSCR_HSITRIM`		8:12	Internal High Speed clock trimming
`RCC_ICSCR_MSIRANGE`		13:15	Internal Multi Speed clock Range
`RCC_ICSCR_MSICAL`		16:23	Internal Multi Speed clock Calibration
`RCC_ICSCR_MSITRIM`		24:31	Internal Multi Speed clock trimming
`CRRCR`	`0x08`	32	RCC Clock recovery RC register
`RCC_CRRCR_HSI48ON`		0	HSI 48MHz clock enable
`RCC_CRRCR_HSI48RDY`		1	HSI 48MHz clock ready flag
`RCC_CRRCR_HSI48CAL`		8:15	HSI 48MHz clock Calibration
`CFGR`	`0x0C`	32	RCC Clock configuration register
`RCC_CFGR_SW`		0:1	SW[1:0] bits (System clock Switch)
`RCC_CFGR_SWS`		2:3	SWS[1:0] bits (System Clock Switch Status)
`RCC_CFGR_HPRE`		4:7	HPRE[3:0] bits (AHB prescaler)
`RCC_CFGR_PPRE1`		8:10	PRE1[2:0] bits (APB1 prescaler)
`RCC_CFGR_PPRE2`		11:13	PRE2[2:0] bits (APB2 prescaler)
`RCC_CFGR_STOPWUCK`		15	Wake Up from Stop Clock selection
`RCC_CFGR_PLLSRC`		16	PLL entry clock source
`RCC_CFGR_PLLMUL`		18:21	PLLMUL[3:0] bits (PLL multiplication factor)
`RCC_CFGR_PLLDIV`		22:23	PLLDIV[1:0] bits (PLL Output Division)
`RCC_CFGR_PLLDIV2`		22	PLL clock output = CKVCO / 2
`RCC_CFGR_PLLDIV4`		22:23	PLL clock output = CKVCO / 4
`RCC_CFGR_PLLDIV3`		23	PLL clock output = CKVCO / 3
`RCC_CFGR_MCOSEL`		24:27	MCO[3:0] bits (Microcontroller Clock Output)
`RCC_CFGR_MCOSEL_SYSCLK`		24	System clock selected as MCO source
`RCC_CFGR_MCOSEL_MSI`		24:25	Internal Medium Speed RC oscillator clock selected
`RCC_CFGR_MCOSEL_PLL`		24:26	PLL clock divided
`RCC_CFGR_MCOSEL_LSE`		24:26	LSE selected
`RCC_CFGR_MCOSEL_HSI`		25	Internal 16 MHz RC oscillator clock selected
`RCC_CFGR_MCOSEL_LSI`		25:26	LSI selected
`RCC_CFGR_MCOSEL_HSE`		26	External 1-25 MHz oscillator clock selected
`RCC_CFGR_MCOSEL_HSI48`		27	HSI48 clock selected as MCO source
`RCC_CFGR_MCOPRE`		28:30	MCO prescaler
`CIER`	`0x10`	32	RCC Clock interrupt enable register
`RCC_CIER_LSIRDYIE`		0	LSI Ready Interrupt Enable
`RCC_CIER_LSERDYIE`		1	LSE Ready Interrupt Enable
`RCC_CIER_HSIRDYIE`		2	HSI Ready Interrupt Enable
`RCC_CIER_HSERDYIE`		3	HSE Ready Interrupt Enable
`RCC_CIER_PLLRDYIE`		4	PLL Ready Interrupt Enable
`RCC_CIER_MSIRDYIE`		5	MSI Ready Interrupt Enable
`RCC_CIER_HSI48RDYIE`		6	HSI48 Ready Interrupt Enable
`RCC_CIER_CSSLSE`		7	LSE CSS Interrupt Enable
`CIFR`	`0x14`	32	RCC Clock interrupt flag register
`RCC_CIFR_LSIRDYF`		0	LSI Ready Interrupt flag
`RCC_CIFR_LSERDYF`		1	LSE Ready Interrupt flag
`RCC_CIFR_HSIRDYF`		2	HSI Ready Interrupt flag
`RCC_CIFR_HSERDYF`		3	HSE Ready Interrupt flag
`RCC_CIFR_PLLRDYF`		4	PLL Ready Interrupt flag
`RCC_CIFR_MSIRDYF`		5	MSI Ready Interrupt flag
`RCC_CIFR_HSI48RDYF`		6	HSI48 Ready Interrupt flag
`RCC_CIFR_CSSLSEF`		7	LSE Clock Security System Interrupt flag
`RCC_CIFR_CSSHSEF`		8	HSE Clock Security System Interrupt flag
`CICR`	`0x18`	32	RCC Clock interrupt clear register
`RCC_CICR_LSIRDYC`		0	LSI Ready Interrupt Clear
`RCC_CICR_LSERDYC`		1	LSE Ready Interrupt Clear
`RCC_CICR_HSIRDYC`		2	HSI Ready Interrupt Clear
`RCC_CICR_HSERDYC`		3	HSE Ready Interrupt Clear
`RCC_CICR_PLLRDYC`		4	PLL Ready Interrupt Clear
`RCC_CICR_MSIRDYC`		5	MSI Ready Interrupt Clear
`RCC_CICR_HSI48RDYC`		6	HSI48 Ready Interrupt Clear
`RCC_CICR_CSSLSEC`		7	LSE Clock Security System Interrupt Clear
`RCC_CICR_CSSHSEC`		8	HSE Clock Security System Interrupt Clear
`IOPRSTR`	`0x1C`	32	RCC IO port reset register
`RCC_IOPRSTR_IOPARST`		0	GPIO port A reset
`RCC_IOPRSTR_IOPBRST`		1	GPIO port B reset
`RCC_IOPRSTR_IOPCRST`		2	GPIO port C reset
`RCC_IOPRSTR_IOPDRST`		3	GPIO port D reset
`RCC_IOPRSTR_IOPHRST`		7	GPIO port H reset
`AHBRSTR`	`0x20`	32	RCC AHB peripheral reset register
`RCC_AHBRSTR_DMARST`		0	DMA1 reset
`RCC_AHBRSTR_MIFRST`		8	Memory interface reset
`RCC_AHBRSTR_CRCRST`		12	CRC reset
`RCC_AHBRSTR_TSCRST`		16	TSC reset
`RCC_AHBRSTR_RNGRST`		20	RNG reset
`APB2RSTR`	`0x24`	32	RCC APB2 peripheral reset register
`RCC_APB2RSTR_SYSCFGRST`		0	SYSCFG reset
`RCC_APB2RSTR_TIM21RST`		2	TIM21 reset
`RCC_APB2RSTR_TIM22RST`		5	TIM22 reset
`RCC_APB2RSTR_ADCRST`		9	ADC1 reset
`RCC_APB2RSTR_SPI1RST`		12	SPI1 reset
`RCC_APB2RSTR_USART1RST`		14	USART1 reset
`RCC_APB2RSTR_DBGRST`		22	DBGMCU reset
`APB1RSTR`	`0x28`	32	RCC APB1 peripheral reset register
`RCC_APB1RSTR_TIM2RST`		0	Timer 2 reset
`RCC_APB1RSTR_TIM6RST`		4	Timer 6 reset
`RCC_APB1RSTR_LCDRST`		9	LCD reset
`RCC_APB1RSTR_WWDGRST`		11	Window Watchdog reset
`RCC_APB1RSTR_SPI2RST`		14	SPI2 reset
`RCC_APB1RSTR_USART2RST`		17	USART 2 reset
`RCC_APB1RSTR_LPUART1RST`		18	LPUART1 reset
`RCC_APB1RSTR_I2C1RST`		21	I2C 1 reset
`RCC_APB1RSTR_I2C2RST`		22	I2C 2 reset
`RCC_APB1RSTR_USBRST`		23	USB reset
`RCC_APB1RSTR_CRSRST`		27	CRS reset
`RCC_APB1RSTR_PWRRST`		28	PWR reset
`RCC_APB1RSTR_DACRST`		29	DAC reset
`RCC_APB1RSTR_LPTIM1RST`		31	LPTIM1 reset
`IOPENR`	`0x2C`	32	RCC Clock IO port enable register
`RCC_IOPENR_IOPAEN`		0	GPIO port A clock enable
`RCC_IOPENR_IOPBEN`		1	GPIO port B clock enable
`RCC_IOPENR_IOPCEN`		2	GPIO port C clock enable
`RCC_IOPENR_IOPDEN`		3	GPIO port D clock enable
`RCC_IOPENR_IOPHEN`		7	GPIO port H clock enable
`AHBENR`	`0x30`	32	RCC AHB peripheral clock enable register
`RCC_AHBENR_DMAEN`		0	DMA1 clock enable
`RCC_AHBENR_MIFEN`		8	NVM interface clock enable bit
`RCC_AHBENR_CRCEN`		12	CRC clock enable
`RCC_AHBENR_TSCEN`		16	TSC clock enable
`RCC_AHBENR_RNGEN`		20	RNG clock enable
`APB2ENR`	`0x34`	32	RCC APB2 peripheral enable register
`RCC_APB2ENR_SYSCFGEN`		0	SYSCFG clock enable
`RCC_APB2ENR_TIM21EN`		2	TIM21 clock enable
`RCC_APB2ENR_TIM22EN`		5	TIM22 clock enable
`RCC_APB2ENR_FWEN`		7	MiFare Firewall clock enable
`RCC_APB2ENR_ADCEN`		9	ADC1 clock enable
`RCC_APB2ENR_SPI1EN`		12	SPI1 clock enable
`RCC_APB2ENR_USART1EN`		14	USART1 clock enable
`RCC_APB2ENR_DBGEN`		22	DBGMCU clock enable
`APB1ENR`	`0x38`	32	RCC APB1 peripheral enable register
`RCC_APB1ENR_TIM2EN`		0	Timer 2 clock enable
`RCC_APB1ENR_TIM6EN`		4	Timer 6 clock enable
`RCC_APB1ENR_LCDEN`		9	LCD clock enable
`RCC_APB1ENR_WWDGEN`		11	Window Watchdog clock enable
`RCC_APB1ENR_SPI2EN`		14	SPI2 clock enable
`RCC_APB1ENR_USART2EN`		17	USART2 clock enable
`RCC_APB1ENR_LPUART1EN`		18	LPUART1 clock enable
`RCC_APB1ENR_I2C1EN`		21	I2C1 clock enable
`RCC_APB1ENR_I2C2EN`		22	I2C2 clock enable
`RCC_APB1ENR_USBEN`		23	USB clock enable
`RCC_APB1ENR_CRSEN`		27	CRS clock enable
`RCC_APB1ENR_PWREN`		28	PWR clock enable
`RCC_APB1ENR_DACEN`		29	DAC clock enable
`RCC_APB1ENR_LPTIM1EN`		31	LPTIM1 clock enable
`IOPSMENR`	`0x3C`	32	RCC IO port clock enable in sleep mode register
`RCC_IOPSMENR_IOPASMEN`		0	GPIO port A clock enabled in sleep mode
`RCC_IOPSMENR_IOPBSMEN`		1	GPIO port B clock enabled in sleep mode
`RCC_IOPSMENR_IOPCSMEN`		2	GPIO port C clock enabled in sleep mode
`RCC_IOPSMENR_IOPDSMEN`		3	GPIO port D clock enabled in sleep mode
`RCC_IOPSMENR_IOPHSMEN`		7	GPIO port H clock enabled in sleep mode
`AHBSMENR`	`0x40`	32	RCC AHB peripheral clock enable in sleep mode register
`RCC_AHBSMENR_DMASMEN`		0	DMA1 clock enabled in sleep mode
`RCC_AHBSMENR_MIFSMEN`		8	NVM interface clock enable during sleep mode
`RCC_AHBSMENR_SRAMSMEN`		9	SRAM clock enabled in sleep mode
`RCC_AHBSMENR_CRCSMEN`		12	CRC clock enabled in sleep mode
`RCC_AHBSMENR_TSCSMEN`		16	TSC clock enabled in sleep mode
`RCC_AHBSMENR_RNGSMEN`		20	RNG clock enabled in sleep mode
`APB2SMENR`	`0x44`	32	RCC APB2 peripheral clock enable in sleep mode register
`RCC_APB2SMENR_SYSCFGSMEN`		0	SYSCFG clock enabled in sleep mode
`RCC_APB2SMENR_TIM21SMEN`		2	TIM21 clock enabled in sleep mode
`RCC_APB2SMENR_TIM22SMEN`		5	TIM22 clock enabled in sleep mode
`RCC_APB2SMENR_ADCSMEN`		9	ADC1 clock enabled in sleep mode
`RCC_APB2SMENR_SPI1SMEN`		12	SPI1 clock enabled in sleep mode
`RCC_APB2SMENR_USART1SMEN`		14	USART1 clock enabled in sleep mode
`RCC_APB2SMENR_DBGSMEN`		22	DBGMCU clock enabled in sleep mode
`APB1SMENR`	`0x48`	32	RCC APB1 peripheral clock enable in sleep mode register
`RCC_APB1SMENR_TIM2SMEN`		0	Timer 2 clock enabled in sleep mode
`RCC_APB1SMENR_TIM6SMEN`		4	Timer 6 clock enabled in sleep mode
`RCC_APB1SMENR_LCDSMEN`		9	LCD clock enabled in sleep mode
`RCC_APB1SMENR_WWDGSMEN`		11	Window Watchdog clock enabled in sleep mode
`RCC_APB1SMENR_SPI2SMEN`		14	SPI2 clock enabled in sleep mode
`RCC_APB1SMENR_USART2SMEN`		17	USART2 clock enabled in sleep mode
`RCC_APB1SMENR_LPUART1SMEN`		18	LPUART1 clock enabled in sleep mode
`RCC_APB1SMENR_I2C1SMEN`		21	I2C1 clock enabled in sleep mode
`RCC_APB1SMENR_I2C2SMEN`		22	I2C2 clock enabled in sleep mode
`RCC_APB1SMENR_USBSMEN`		23	USB clock enabled in sleep mode
`RCC_APB1SMENR_CRSSMEN`		27	CRS clock enabled in sleep mode
`RCC_APB1SMENR_PWRSMEN`		28	PWR clock enabled in sleep mode
`RCC_APB1SMENR_DACSMEN`		29	DAC clock enabled in sleep mode
`RCC_APB1SMENR_LPTIM1SMEN`		31	LPTIM1 clock enabled in sleep mode
`CCIPR`	`0x4C`	32	RCC clock configuration register
`RCC_CCIPR_USART1SEL`		0:1	USART1SEL[1:0] bits
`RCC_CCIPR_USART2SEL`		2:3	USART2SEL[1:0] bits
`RCC_CCIPR_LPUART1SEL`		10:11	LPUART1SEL[1:0] bits
`RCC_CCIPR_I2C1SEL`		12:13	I2C1SEL [1:0] bits
`RCC_CCIPR_LPTIM1SEL`		18:19	LPTIM1SEL [1:0] bits
`RCC_CCIPR_HSI48SEL`		26	HSI48 RC clock source selection bit for USB and RNG
`CSR`	`0x50`	32	RCC Control/status register
`RCC_CSR_LSION`		0	Internal Low Speed oscillator enable
`RCC_CSR_LSIRDY`		1	Internal Low Speed oscillator Ready
`RCC_CSR_LSEON`		8	External Low Speed oscillator enable
`RCC_CSR_LSERDY`		9	External Low Speed oscillator Ready
`RCC_CSR_LSEBYP`		10	External Low Speed oscillator Bypass
`RCC_CSR_LSEDRV`		11:12	LSEDRV[1:0] bits (LSE Osc. drive capability)
`RCC_CSR_LSECSSON`		13	External Low Speed oscillator CSS Enable
`RCC_CSR_LSECSSD`		14	External Low Speed oscillator CSS Detected
`RCC_CSR_RTCSEL`		16:17	RTCSEL[1:0] bits (RTC clock source selection)
`RCC_CSR_RTCSEL_LSE`		16	LSE oscillator clock used as RTC clock
`RCC_CSR_RTCSEL_HSE`		16:17	HSE oscillator clock used as RTC clock
`RCC_CSR_RTCSEL_LSI`		17	LSI oscillator clock used as RTC clock
`RCC_CSR_RTCEN`		18	RTC clock enable
`RCC_CSR_RTCRST`		19	RTC software reset
`RCC_CSR_RMVF`		23	Remove reset flag
`RCC_CSR_FWRSTF`		24	Mifare Firewall reset flag
`RCC_CSR_OBLRSTF`		25	OBL reset flag
`RCC_CSR_PINRSTF`		26	PIN reset flag
`RCC_CSR_PORRSTF`		27	POR/PDR reset flag
`RCC_CSR_SFTRSTF`		28	Software Reset flag
`RCC_CSR_IWDGRSTF`		29	Independent Watchdog reset flag
`RCC_CSR_WWDGRSTF`		30	Window watchdog reset flag
`RCC_CSR_LPWRRSTF`		31	Low-Power reset flag

GPIO — Порты ввода-вывода (раздел 8)

Регистр	Смещение	Бит	Назначение
`MODER`	`0x00`	32	GPIO port mode register
`GPIO_MODER_MODE0`		0:1
`GPIO_MODER_MODE1`		2:3
`GPIO_MODER_MODE2`		4:5
`GPIO_MODER_MODE3`		6:7
`GPIO_MODER_MODE4`		8:9
`GPIO_MODER_MODE5`		10:11
`GPIO_MODER_MODE6`		12:13
`GPIO_MODER_MODE7`		14:15
`GPIO_MODER_MODE8`		16:17
`GPIO_MODER_MODE9`		18:19
`GPIO_MODER_MODE10`		20:21
`GPIO_MODER_MODE11`		22:23
`GPIO_MODER_MODE12`		24:25
`GPIO_MODER_MODE13`		26:27
`GPIO_MODER_MODE14`		28:29
`GPIO_MODER_MODE15`		30:31
`OTYPER`	`0x04`	32	GPIO port output type register
`OSPEEDR`	`0x08`	32	GPIO port output speed register
`PUPDR`	`0x0C`	32	GPIO port pull-up/pull-down register
`GPIO_PUPDR_PUPD0`		0:1
`GPIO_PUPDR_PUPD1`		2:3
`GPIO_PUPDR_PUPD2`		4:5
`GPIO_PUPDR_PUPD3`		6:7
`GPIO_PUPDR_PUPD4`		8:9
`GPIO_PUPDR_PUPD5`		10:11
`GPIO_PUPDR_PUPD6`		12:13
`GPIO_PUPDR_PUPD7`		14:15
`GPIO_PUPDR_PUPD8`		16:17
`GPIO_PUPDR_PUPD9`		18:19
`GPIO_PUPDR_PUPD10`		20:21
`GPIO_PUPDR_PUPD11`		22:23
`GPIO_PUPDR_PUPD12`		24:25
`GPIO_PUPDR_PUPD13`		26:27
`GPIO_PUPDR_PUPD14`		28:29
`GPIO_PUPDR_PUPD15`		30:31
`IDR`	`0x10`	32	GPIO port input data register
`GPIO_IDR_ID0`		0
`GPIO_IDR_ID1`		1
`GPIO_IDR_ID2`		2
`GPIO_IDR_ID3`		3
`GPIO_IDR_ID4`		4
`GPIO_IDR_ID5`		5
`GPIO_IDR_ID6`		6
`GPIO_IDR_ID7`		7
`GPIO_IDR_ID8`		8
`GPIO_IDR_ID9`		9
`GPIO_IDR_ID10`		10
`GPIO_IDR_ID11`		11
`GPIO_IDR_ID12`		12
`GPIO_IDR_ID13`		13
`GPIO_IDR_ID14`		14
`GPIO_IDR_ID15`		15
`ODR`	`0x14`	32	GPIO port output data register
`GPIO_ODR_OD0`		0
`GPIO_ODR_OD1`		1
`GPIO_ODR_OD2`		2
`GPIO_ODR_OD3`		3
`GPIO_ODR_OD4`		4
`GPIO_ODR_OD5`		5
`GPIO_ODR_OD6`		6
`GPIO_ODR_OD7`		7
`GPIO_ODR_OD8`		8
`GPIO_ODR_OD9`		9
`GPIO_ODR_OD10`		10
`GPIO_ODR_OD11`		11
`GPIO_ODR_OD12`		12
`GPIO_ODR_OD13`		13
`GPIO_ODR_OD14`		14
`GPIO_ODR_OD15`		15
`BSRR`	`0x18`	32	GPIO port bit set/reset registerBSRR
`LCKR`	`0x1C`	32	GPIO port configuration lock register
`GPIO_LCKR_LCK0`		0
`GPIO_LCKR_LCK1`		1
`GPIO_LCKR_LCK2`		2
`GPIO_LCKR_LCK3`		3
`GPIO_LCKR_LCK4`		4
`GPIO_LCKR_LCK5`		5
`GPIO_LCKR_LCK6`		6
`GPIO_LCKR_LCK7`		7
`GPIO_LCKR_LCK8`		8
`GPIO_LCKR_LCK9`		9
`GPIO_LCKR_LCK10`		10
`GPIO_LCKR_LCK11`		11
`GPIO_LCKR_LCK12`		12
`GPIO_LCKR_LCK13`		13
`GPIO_LCKR_LCK14`		14
`GPIO_LCKR_LCK15`		15
`GPIO_LCKR_LCKK`		16
`AFR`+2×4	`0x20`	32	GPIO alternate function register
`BRR`	`0x28`	32	GPIO bit reset register

SYSCFG — Системная конфигурация (раздел 8)

Регистр	Смещение	Бит	Назначение
`CFGR1`	`0x00`	32	SYSCFG configuration register 1
`SYSCFG_CFGR1_MEM_MODE`		0:1	SYSCFG_Memory Remap Config
`SYSCFG_CFGR1_BOOT_MODE`		8:9	SYSCFG_Boot mode Config
`CFGR2`	`0x04`	32	SYSCFG configuration register 2
`SYSCFG_CFGR2_FWDISEN`		0	Firewall disable bit
`SYSCFG_CFGR2_CAPA`		1:3	Connection of internal Vlcd rail to external capacitors
`SYSCFG_CFGR2_I2C_PB6_FMP`		8	I2C PB6 Fast mode plus
`SYSCFG_CFGR2_I2C_PB7_FMP`		9	I2C PB7 Fast mode plus
`SYSCFG_CFGR2_I2C_PB8_FMP`		10	I2C PB8 Fast mode plus
`SYSCFG_CFGR2_I2C_PB9_FMP`		11	I2C PB9 Fast mode plus
`SYSCFG_CFGR2_I2C1_FMP`		12	I2C1 Fast mode plus
`SYSCFG_CFGR2_I2C2_FMP`		13	I2C2 Fast mode plus
`EXTICR`+4×4	`0x08`	32	SYSCFG external interrupt configuration register
`CFGR3`	`0x20`	32	SYSCFG configuration register 3
`SYSCFG_CFGR3_VREF_OUT`		4:5	Verf_ADC connection bit
`SYSCFG_CFGR3_EN_VREFINT`		8	Vref Enable bit
`SYSCFG_CFGR3_ENBUF_VREFINT_ADC`		8	VREFINT reference for ADC enable bit
`SYSCFG_CFGR3_ENBUF_SENSOR_ADC`		9	Sensor reference for ADC enable bit
`SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP`		12	VREFINT reference for comparator 2 enable bit
`SYSCFG_CFGR3_ENREF_HSI48`		13	VREFINT reference or 48 MHz RC oscillator enable bit
`SYSCFG_CFGR3_VREFINT_RDYF`		30	VREFINT ready flag
`SYSCFG_CFGR3_REF_LOCK`		31	CFGR3 lock bit

EXTI — Внешние прерывания (раздел 7)

Регистр	Смещение	Бит	Назначение
`IMR`	`0x00`	32	EXTI Interrupt mask register
`EXTI_IMR_IM0`		0	Interrupt Mask on line 0
`EXTI_IMR_IM`		0:29	Interrupt Mask All
`EXTI_IMR_IM1`		1	Interrupt Mask on line 1
`EXTI_IMR_IM2`		2	Interrupt Mask on line 2
`EXTI_IMR_IM3`		3	Interrupt Mask on line 3
`EXTI_IMR_IM4`		4	Interrupt Mask on line 4
`EXTI_IMR_IM5`		5	Interrupt Mask on line 5
`EXTI_IMR_IM6`		6	Interrupt Mask on line 6
`EXTI_IMR_IM7`		7	Interrupt Mask on line 7
`EXTI_IMR_IM8`		8	Interrupt Mask on line 8
`EXTI_IMR_IM9`		9	Interrupt Mask on line 9
`EXTI_IMR_IM10`		10	Interrupt Mask on line 10
`EXTI_IMR_IM11`		11	Interrupt Mask on line 11
`EXTI_IMR_IM12`		12	Interrupt Mask on line 12
`EXTI_IMR_IM13`		13	Interrupt Mask on line 13
`EXTI_IMR_IM14`		14	Interrupt Mask on line 14
`EXTI_IMR_IM15`		15	Interrupt Mask on line 15
`EXTI_IMR_IM16`		16	Interrupt Mask on line 16
`EXTI_IMR_IM17`		17	Interrupt Mask on line 17
`EXTI_IMR_IM18`		18	Interrupt Mask on line 18
`EXTI_IMR_IM19`		19	Interrupt Mask on line 19
`EXTI_IMR_IM20`		20	Interrupt Mask on line 20
`EXTI_IMR_IM21`		21	Interrupt Mask on line 21
`EXTI_IMR_IM22`		22	Interrupt Mask on line 22
`EXTI_IMR_IM23`		23	Interrupt Mask on line 23
`EXTI_IMR_IM25`		25	Interrupt Mask on line 25
`EXTI_IMR_IM26`		26	Interrupt Mask on line 26
`EXTI_IMR_IM28`		28	Interrupt Mask on line 28
`EXTI_IMR_IM29`		29	Interrupt Mask on line 29
`EMR`	`0x04`	32	EXTI Event mask register
`EXTI_EMR_EM0`		0	Event Mask on line 0
`EXTI_EMR_EM1`		1	Event Mask on line 1
`EXTI_EMR_EM2`		2	Event Mask on line 2
`EXTI_EMR_EM3`		3	Event Mask on line 3
`EXTI_EMR_EM4`		4	Event Mask on line 4
`EXTI_EMR_EM5`		5	Event Mask on line 5
`EXTI_EMR_EM6`		6	Event Mask on line 6
`EXTI_EMR_EM7`		7	Event Mask on line 7
`EXTI_EMR_EM8`		8	Event Mask on line 8
`EXTI_EMR_EM9`		9	Event Mask on line 9
`EXTI_EMR_EM10`		10	Event Mask on line 10
`EXTI_EMR_EM11`		11	Event Mask on line 11
`EXTI_EMR_EM12`		12	Event Mask on line 12
`EXTI_EMR_EM13`		13	Event Mask on line 13
`EXTI_EMR_EM14`		14	Event Mask on line 14
`EXTI_EMR_EM15`		15	Event Mask on line 15
`EXTI_EMR_EM16`		16	Event Mask on line 16
`EXTI_EMR_EM17`		17	Event Mask on line 17
`EXTI_EMR_EM18`		18	Event Mask on line 18
`EXTI_EMR_EM19`		19	Event Mask on line 19
`EXTI_EMR_EM20`		20	Event Mask on line 20
`EXTI_EMR_EM21`		21	Event Mask on line 21
`EXTI_EMR_EM22`		22	Event Mask on line 22
`EXTI_EMR_EM23`		23	Event Mask on line 23
`EXTI_EMR_EM25`		25	Event Mask on line 25
`EXTI_EMR_EM26`		26	Event Mask on line 26
`EXTI_EMR_EM28`		28	Event Mask on line 28
`EXTI_EMR_EM29`		29	Event Mask on line 29
`RTSR`	`0x08`	32	EXTI Rising trigger selection register
`EXTI_RTSR_RT0`		0	Rising trigger event configuration bit of line 0
`EXTI_RTSR_RT1`		1	Rising trigger event configuration bit of line 1
`EXTI_RTSR_RT2`		2	Rising trigger event configuration bit of line 2
`EXTI_RTSR_RT3`		3	Rising trigger event configuration bit of line 3
`EXTI_RTSR_RT4`		4	Rising trigger event configuration bit of line 4
`EXTI_RTSR_RT5`		5	Rising trigger event configuration bit of line 5
`EXTI_RTSR_RT6`		6	Rising trigger event configuration bit of line 6
`EXTI_RTSR_RT7`		7	Rising trigger event configuration bit of line 7
`EXTI_RTSR_RT8`		8	Rising trigger event configuration bit of line 8
`EXTI_RTSR_RT9`		9	Rising trigger event configuration bit of line 9
`EXTI_RTSR_RT10`		10	Rising trigger event configuration bit of line 10
`EXTI_RTSR_RT11`		11	Rising trigger event configuration bit of line 11
`EXTI_RTSR_RT12`		12	Rising trigger event configuration bit of line 12
`EXTI_RTSR_RT13`		13	Rising trigger event configuration bit of line 13
`EXTI_RTSR_RT14`		14	Rising trigger event configuration bit of line 14
`EXTI_RTSR_RT15`		15	Rising trigger event configuration bit of line 15
`EXTI_RTSR_RT16`		16	Rising trigger event configuration bit of line 16
`EXTI_RTSR_RT17`		17	Rising trigger event configuration bit of line 17
`EXTI_RTSR_RT19`		19	Rising trigger event configuration bit of line 19
`EXTI_RTSR_RT20`		20	Rising trigger event configuration bit of line 20
`EXTI_RTSR_RT21`		21	Rising trigger event configuration bit of line 21
`EXTI_RTSR_RT22`		22	Rising trigger event configuration bit of line 22
`FTSR`	`0x0C`	32	EXTI Falling trigger selection register
`EXTI_FTSR_FT0`		0	Falling trigger event configuration bit of line 0
`EXTI_FTSR_FT1`		1	Falling trigger event configuration bit of line 1
`EXTI_FTSR_FT2`		2	Falling trigger event configuration bit of line 2
`EXTI_FTSR_FT3`		3	Falling trigger event configuration bit of line 3
`EXTI_FTSR_FT4`		4	Falling trigger event configuration bit of line 4
`EXTI_FTSR_FT5`		5	Falling trigger event configuration bit of line 5
`EXTI_FTSR_FT6`		6	Falling trigger event configuration bit of line 6
`EXTI_FTSR_FT7`		7	Falling trigger event configuration bit of line 7
`EXTI_FTSR_FT8`		8	Falling trigger event configuration bit of line 8
`EXTI_FTSR_FT9`		9	Falling trigger event configuration bit of line 9
`EXTI_FTSR_FT10`		10	Falling trigger event configuration bit of line 10
`EXTI_FTSR_FT11`		11	Falling trigger event configuration bit of line 11
`EXTI_FTSR_FT12`		12	Falling trigger event configuration bit of line 12
`EXTI_FTSR_FT13`		13	Falling trigger event configuration bit of line 13
`EXTI_FTSR_FT14`		14	Falling trigger event configuration bit of line 14
`EXTI_FTSR_FT15`		15	Falling trigger event configuration bit of line 15
`EXTI_FTSR_FT16`		16	Falling trigger event configuration bit of line 16
`EXTI_FTSR_FT17`		17	Falling trigger event configuration bit of line 17
`EXTI_FTSR_FT19`		19	Falling trigger event configuration bit of line 19
`EXTI_FTSR_FT20`		20	Falling trigger event configuration bit of line 20
`EXTI_FTSR_FT21`		21	Falling trigger event configuration bit of line 21
`EXTI_FTSR_FT22`		22	Falling trigger event configuration bit of line 22
`SWIER`	`0x10`	32	EXTI Software interrupt event register
`EXTI_SWIER_SWI0`		0	Software Interrupt on line 0
`EXTI_SWIER_SWI1`		1	Software Interrupt on line 1
`EXTI_SWIER_SWI2`		2	Software Interrupt on line 2
`EXTI_SWIER_SWI3`		3	Software Interrupt on line 3
`EXTI_SWIER_SWI4`		4	Software Interrupt on line 4
`EXTI_SWIER_SWI5`		5	Software Interrupt on line 5
`EXTI_SWIER_SWI6`		6	Software Interrupt on line 6
`EXTI_SWIER_SWI7`		7	Software Interrupt on line 7
`EXTI_SWIER_SWI8`		8	Software Interrupt on line 8
`EXTI_SWIER_SWI9`		9	Software Interrupt on line 9
`EXTI_SWIER_SWI10`		10	Software Interrupt on line 10
`EXTI_SWIER_SWI11`		11	Software Interrupt on line 11
`EXTI_SWIER_SWI12`		12	Software Interrupt on line 12
`EXTI_SWIER_SWI13`		13	Software Interrupt on line 13
`EXTI_SWIER_SWI14`		14	Software Interrupt on line 14
`EXTI_SWIER_SWI15`		15	Software Interrupt on line 15
`EXTI_SWIER_SWI16`		16	Software Interrupt on line 16
`EXTI_SWIER_SWI17`		17	Software Interrupt on line 17
`EXTI_SWIER_SWI19`		19	Software Interrupt on line 19
`EXTI_SWIER_SWI20`		20	Software Interrupt on line 20
`EXTI_SWIER_SWI21`		21	Software Interrupt on line 21
`EXTI_SWIER_SWI22`		22	Software Interrupt on line 22
`PR`	`0x14`	32	EXTI Pending register
`EXTI_PR_PIF0`		0	Pending bit 0
`EXTI_PR_PIF1`		1	Pending bit 1
`EXTI_PR_PIF2`		2	Pending bit 2
`EXTI_PR_PIF3`		3	Pending bit 3
`EXTI_PR_PIF4`		4	Pending bit 4
`EXTI_PR_PIF5`		5	Pending bit 5
`EXTI_PR_PIF6`		6	Pending bit 6
`EXTI_PR_PIF7`		7	Pending bit 7
`EXTI_PR_PIF8`		8	Pending bit 8
`EXTI_PR_PIF9`		9	Pending bit 9
`EXTI_PR_PIF10`		10	Pending bit 10
`EXTI_PR_PIF11`		11	Pending bit 11
`EXTI_PR_PIF12`		12	Pending bit 12
`EXTI_PR_PIF13`		13	Pending bit 13
`EXTI_PR_PIF14`		14	Pending bit 14
`EXTI_PR_PIF15`		15	Pending bit 15
`EXTI_PR_PIF16`		16	Pending bit 16
`EXTI_PR_PIF17`		17	Pending bit 17
`EXTI_PR_PIF19`		19	Pending bit 19
`EXTI_PR_PIF20`		20	Pending bit 20
`EXTI_PR_PIF21`		21	Pending bit 21
`EXTI_PR_PIF22`		22	Pending bit 22

DMA — Канал DMA (раздел 9)

Регистр	Смещение	Бит	Назначение
`CCR`	`0x00`	32	DMA channel x configuration register
`DMA_CCR_EN`		0	Channel enable
`DMA_CCR_TCIE`		1	Transfer complete interrupt enable
`DMA_CCR_HTIE`		2	Half Transfer interrupt enable
`DMA_CCR_TEIE`		3	Transfer error interrupt enable
`DMA_CCR_DIR`		4	Data transfer direction
`DMA_CCR_CIRC`		5	Circular mode
`DMA_CCR_PINC`		6	Peripheral increment mode
`DMA_CCR_MINC`		7	Memory increment mode
`DMA_CCR_PSIZE`		8:9	PSIZE[1:0] bits (Peripheral size)
`DMA_CCR_MSIZE`		10:11	MSIZE[1:0] bits (Memory size)
`DMA_CCR_PL`		12:13	PL[1:0] bits(Channel Priority level)
`DMA_CCR_MEM2MEM`		14	Memory to memory mode
`CNDTR`	`0x04`	32	DMA channel x number of data register
`DMA_CNDTR_NDT`		0:15	Number of data to Transfer
`CPAR`	`0x08`	32	DMA channel x peripheral address register
`DMA_CPAR_PA`		0:31	Peripheral Address
`CMAR`	`0x0C`	32	DMA channel x memory address register
`DMA_CMAR_MA`		0:31	Memory Address

PWR — Питание и режимы сна (раздел 10)

Регистр	Смещение	Бит	Назначение
`CR`	`0x00`	32	PWR power control register
`PWR_CR_LPSDSR`		0	Low-power deepsleep/sleep/low power run
`PWR_CR_PDDS`		1	Power Down Deepsleep
`PWR_CR_CWUF`		2	Clear Wakeup Flag
`PWR_CR_CSBF`		3	Clear Standby Flag
`PWR_CR_PVDE`		4	Power Voltage Detector Enable
`PWR_CR_PLS`		5:7	PLS[2:0] bits (PVD Level Selection)
`PWR_CR_DBP`		8	Disable Backup Domain write protection
`PWR_CR_ULP`		9	Ultra Low Power mode
`PWR_CR_FWU`		10	Fast wakeup
`PWR_CR_VOS`		11:12	VOS[1:0] bits (Voltage scaling range selection)
`PWR_CR_DSEEKOFF`		13	Deep Sleep mode with EEPROM kept Off
`PWR_CR_LPRUN`		14	Low power run mode
`CSR`	`0x04`	32	PWR power control/status register
`PWR_CSR_WUF`		0	Wakeup Flag
`PWR_CSR_SBF`		1	Standby Flag
`PWR_CSR_PVDO`		2	PVD Output
`PWR_CSR_VREFINTRDYF`		3	Internal voltage reference (VREFINT) ready flag
`PWR_CSR_VOSF`		4	Voltage Scaling select flag
`PWR_CSR_REGLPF`		5	Regulator LP flag
`PWR_CSR_EWUP1`		8	Enable WKUP pin 1
`PWR_CSR_EWUP2`		9	Enable WKUP pin 2

FLASH — Контроллер флеш-памяти (раздел 11)

Регистр	Смещение	Бит	Назначение
`ACR`	`0x00`	32	Access control register
`FLASH_ACR_LATENCY`		0	LATENCY bit (Latency)
`FLASH_ACR_PRFTEN`		1	Prefetch Buffer Enable
`FLASH_ACR_SLEEP_PD`		3	Flash mode during sleep mode
`FLASH_ACR_RUN_PD`		4	Flash mode during RUN mode
`FLASH_ACR_DISAB_BUF`		5	Disable Buffer
`FLASH_ACR_PRE_READ`		6	Pre-read data address
`PECR`	`0x04`	32	Program/erase control register
`FLASH_PECR_PELOCK`		0	FLASH_PECR and Flash data Lock
`FLASH_PECR_PRGLOCK`		1	Program matrix Lock
`FLASH_PECR_OPTLOCK`		2	Option byte matrix Lock
`FLASH_PECR_PROG`		3	Program matrix selection
`FLASH_PECR_DATA`		4	Data matrix selection
`FLASH_PECR_FIX`		8	Fixed Time Data write for Word/Half Word/Byte programming
`FLASH_PECR_ERASE`		9	Page erasing mode
`FLASH_PECR_FPRG`		10	Fast Page/Half Page programming mode
`FLASH_PECR_EOPIE`		16	End of programming interrupt
`FLASH_PECR_ERRIE`		17	Error interrupt
`FLASH_PECR_OBL_LAUNCH`		18	Launch the option byte loading
`FLASH_PECR_HALF_ARRAY`		19	Half array mode
`PDKEYR`	`0x08`	32	Power down key register
`FLASH_PDKEYR_PDKEYR`		0:31	FLASH_PEC and data matrix Key
`PEKEYR`	`0x0C`	32	Program/erase key register
`FLASH_PEKEYR_PEKEYR`		0:31	FLASH_PEC and data matrix Key
`PRGKEYR`	`0x10`	32	Program memory key register
`FLASH_PRGKEYR_PRGKEYR`		0:31	Program matrix Key
`OPTKEYR`	`0x14`	32	Option byte key register
`FLASH_OPTKEYR_OPTKEYR`		0:31	Option bytes matrix Key
`SR`	`0x18`	32	Status register
`FLASH_SR_BSY`		0	Busy
`FLASH_SR_EOP`		1	End Of Programming
`FLASH_SR_HVOFF`		2	End of high voltage
`FLASH_SR_READY`		3	Flash ready after low power mode
`FLASH_SR_WRPERR`		8	Write protection error
`FLASH_SR_PGAERR`		9	Programming Alignment Error
`FLASH_SR_SIZERR`		10	Size error
`FLASH_SR_OPTVERR`		11	Option Valid error
`FLASH_SR_RDERR`		13	Read protected error
`FLASH_SR_NOTZEROERR`		16	Not Zero error
`FLASH_SR_FWWERR`		17	Write/Errase operation aborted
`OPTR`	`0x1C`	32	Option byte register
`FLASH_OPTR_RDPROT`		0:7	Read Protection
`FLASH_OPTR_WPRMOD`		8	Selection of protection mode of WPR bits
`FLASH_OPTR_BOR_LEV`		16:19	BOR_LEV[3:0] Brown Out Reset Threshold Level
`FLASH_OPTR_IWDG_SW`		20	IWDG_SW
`FLASH_OPTR_USER`		20:22	User Option Bytes
`FLASH_OPTR_nRST_STOP`		21	nRST_STOP
`FLASH_OPTR_nRST_STDBY`		22	nRST_STDBY
`FLASH_OPTR_BOOT1`		31	BOOT1
`WRPR`	`0x20`	32	Write protection register
`FLASH_WRPR_WRP`		0:15	Write Protection bits

IWDG — Независимый сторож (раздел 12)

Регистр	Смещение	Бит	Назначение
`KR`	`0x00`	32	IWDG Key register
`IWDG_KR_KEY`		0:15	Key value (write only, read 0000h)
`PR`	`0x04`	32	IWDG Prescaler register
`IWDG_PR_PR`		0:2	PR[2:0] (Prescaler divider)
`RLR`	`0x08`	32	IWDG Reload register
`IWDG_RLR_RL`		0:11	Watchdog counter reload value
`SR`	`0x0C`	32	IWDG Status register
`IWDG_SR_PVU`		0	Watchdog prescaler value update
`IWDG_SR_RVU`		1	Watchdog counter reload value update
`IWDG_SR_WVU`		2	Watchdog counter window value update
`WINR`	`0x10`	32	IWDG Window register
`IWDG_WINR_WIN`		0:11	Watchdog counter window value

WWDG — Оконный сторож (раздел 12)

Регистр	Смещение	Бит	Назначение
`CR`	`0x00`	32	WWDG Control register
`WWDG_CR_T`		0:6	T[6:0] bits (7-Bit counter (MSB to LSB))
`WWDG_CR_WDGA`		7	Activation bit
`CFR`	`0x04`	32	WWDG Configuration register
`WWDG_CFR_W`		0:6	W[6:0] bits (7-bit window value)
`WWDG_CFR_WDGTB`		7:8	WDGTB[1:0] bits (Timer Base)
`WWDG_CFR_EWI`		9	Early Wakeup Interrupt
`SR`	`0x08`	32	WWDG Status register
`WWDG_SR_EWIF`		0	Early Wakeup Interrupt Flag

CRC — Контрольная сумма (раздел 12)

Регистр	Смещение	Бит	Назначение
`DR`	`0x00`	32	CRC Data register
`CRC_DR_DR`		0:31	Data register bits
`IDR`	`0x04`	8	CRC Independent data register
`CR`	`0x08`	32	CRC Control register
`CRC_CR_RESET`		0	RESET the CRC computation unit bit
`CRC_CR_POLYSIZE`		3:4	Polynomial size bits
`CRC_CR_REV_IN`		5:6	REV_IN Reverse Input Data bits
`CRC_CR_REV_OUT`		7	REV_OUT Reverse Output Data bits
`INIT`	`0x10`	32	Initial CRC value register
`CRC_INIT_INIT`		0:31	Initial CRC value bits
`POL`	`0x14`	32	CRC polynomial register
`CRC_POL_POL`		0:31	Coefficients of the polynomial

RTC — Часы реального времени (раздел 12)

Регистр	Смещение	Бит	Назначение
`TR`	`0x00`	32	RTC time register
`RTC_TR_SU`		0:3
`RTC_TR_ST`		4:6
`RTC_TR_MNU`		8:11
`RTC_TR_MNT`		12:14
`RTC_TR_HU`		16:19
`RTC_TR_HT`		20:21
`RTC_TR_PM`		22
`DR`	`0x04`	32	RTC date register
`RTC_DR_DU`		0:3
`RTC_DR_DT`		4:5
`RTC_DR_MU`		8:11
`RTC_DR_MT`		12
`RTC_DR_WDU`		13:15
`RTC_DR_YU`		16:19
`RTC_DR_YT`		20:23
`CR`	`0x08`	32	RTC control register
`RTC_CR_WUCKSEL`		0:2
`RTC_CR_TSEDGE`		3
`RTC_CR_REFCKON`		4
`RTC_CR_BYPSHAD`		5
`RTC_CR_FMT`		6
`RTC_CR_ALRAE`		8
`RTC_CR_ALRBE`		9
`RTC_CR_WUTE`		10
`RTC_CR_TSE`		11
`RTC_CR_ALRAIE`		12
`RTC_CR_ALRBIE`		13
`RTC_CR_WUTIE`		14
`RTC_CR_TSIE`		15
`RTC_CR_ADD1H`		16
`RTC_CR_SUB1H`		17
`RTC_CR_BKP`		18
`RTC_CR_COSEL`		19
`RTC_CR_POL`		20
`RTC_CR_OSEL`		21:22
`RTC_CR_COE`		23
`ISR`	`0x0C`	32	RTC initialization and status register
`RTC_ISR_ALRAWF`		0
`RTC_ISR_ALRBWF`		1
`RTC_ISR_WUTWF`		2
`RTC_ISR_SHPF`		3
`RTC_ISR_INITS`		4
`RTC_ISR_RSF`		5
`RTC_ISR_INITF`		6
`RTC_ISR_INIT`		7
`RTC_ISR_ALRAF`		8
`RTC_ISR_ALRBF`		9
`RTC_ISR_WUTF`		10
`RTC_ISR_TSF`		11
`RTC_ISR_TSOVF`		12
`RTC_ISR_TAMP1F`		13
`RTC_ISR_TAMP2F`		14
`RTC_ISR_RECALPF`		16
`PRER`	`0x10`	32	RTC prescaler register
`RTC_PRER_PREDIV_S`		0:14
`RTC_PRER_PREDIV_A`		16:22
`WUTR`	`0x14`	32	RTC wakeup timer register
`RTC_WUTR_WUT`		0:15
`ALRMAR`	`0x1C`	32	RTC alarm A register
`RTC_ALRMAR_SU`		0:3
`RTC_ALRMAR_ST`		4:6
`RTC_ALRMAR_MSK1`		7
`RTC_ALRMAR_MNU`		8:11
`RTC_ALRMAR_MNT`		12:14
`RTC_ALRMAR_MSK2`		15
`RTC_ALRMAR_HU`		16:19
`RTC_ALRMAR_HT`		20:21
`RTC_ALRMAR_PM`		22
`RTC_ALRMAR_MSK3`		23
`RTC_ALRMAR_DU`		24:27
`RTC_ALRMAR_DT`		28:29
`RTC_ALRMAR_WDSEL`		30
`RTC_ALRMAR_MSK4`		31
`ALRMBR`	`0x20`	32	RTC alarm B register
`RTC_ALRMBR_SU`		0:3
`RTC_ALRMBR_ST`		4:6
`RTC_ALRMBR_MSK1`		7
`RTC_ALRMBR_MNU`		8:11
`RTC_ALRMBR_MNT`		12:14
`RTC_ALRMBR_MSK2`		15
`RTC_ALRMBR_HU`		16:19
`RTC_ALRMBR_HT`		20:21
`RTC_ALRMBR_PM`		22
`RTC_ALRMBR_MSK3`		23
`RTC_ALRMBR_DU`		24:27
`RTC_ALRMBR_DT`		28:29
`RTC_ALRMBR_WDSEL`		30
`RTC_ALRMBR_MSK4`		31
`WPR`	`0x24`	32	RTC write protection register
`RTC_WPR_KEY`		0:7
`SSR`	`0x28`	32	RTC sub second register
`RTC_SSR_SS`		0:15
`SHIFTR`	`0x2C`	32	RTC shift control register
`RTC_SHIFTR_SUBFS`		0:14
`RTC_SHIFTR_ADD1S`		31
`TSTR`	`0x30`	32	RTC time stamp time register
`RTC_TSTR_SU`		0:3
`RTC_TSTR_ST`		4:6
`RTC_TSTR_MNU`		8:11
`RTC_TSTR_MNT`		12:14
`RTC_TSTR_HU`		16:19
`RTC_TSTR_HT`		20:21
`RTC_TSTR_PM`		22
`TSDR`	`0x34`	32	RTC time stamp date register
`RTC_TSDR_DU`		0:3
`RTC_TSDR_DT`		4:5
`RTC_TSDR_MU`		8:11
`RTC_TSDR_MT`		12
`RTC_TSDR_WDU`		13:15
`TSSSR`	`0x38`	32	RTC time-stamp sub second register
`RTC_TSSSR_SS`		0:15
`CALR`	`0x3C`	32	RTC calibration register
`RTC_CALR_CALM`		0:8
`RTC_CALR_CALW16`		13
`RTC_CALR_CALW8`		14
`RTC_CALR_CALP`		15
`TAMPCR`	`0x40`	32	RTC tamper configuration register
`RTC_TAMPCR_TAMP1E`		0
`RTC_TAMPCR_TAMP1TRG`		1
`RTC_TAMPCR_TAMPIE`		2
`RTC_TAMPCR_TAMP2E`		3
`RTC_TAMPCR_TAMP2TRG`		4
`RTC_TAMPCR_TAMPTS`		7
`RTC_TAMPCR_TAMPFREQ`		8:10
`RTC_TAMPCR_TAMPFLT`		11:12
`RTC_TAMPCR_TAMPPRCH`		13:14
`RTC_TAMPCR_TAMPPUDIS`		15
`RTC_TAMPCR_TAMP1IE`		16
`RTC_TAMPCR_TAMP1NOERASE`		17
`RTC_TAMPCR_TAMP1MF`		18
`RTC_TAMPCR_TAMP2IE`		19
`RTC_TAMPCR_TAMP2NOERASE`		20
`RTC_TAMPCR_TAMP2MF`		21
`ALRMASSR`	`0x44`	32	RTC alarm A sub second register
`RTC_ALRMASSR_SS`		0:14
`RTC_ALRMASSR_MASKSS`		24:27
`ALRMBSSR`	`0x48`	32	RTC alarm B sub second register
`RTC_ALRMBSSR_SS`		0:14
`RTC_ALRMBSSR_MASKSS`		24:27
`OR`	`0x4C`	32	RTC option register, Address offset 0x4C
`RTC_OR_ALARMOUTTYPE`		0
`RTC_OR_OUT_RMP`		1
`BKP0R`	`0x50`	32	RTC backup register 0
`BKP1R`	`0x54`	32	RTC backup register 1
`BKP2R`	`0x58`	32	RTC backup register 2
`BKP3R`	`0x5C`	32	RTC backup register 3
`BKP4R`	`0x60`	32	RTC backup register 4

TIM — Таймеры (раздел 13)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	TIM control register 1
`TIM_CR1_CEN`		0	Counter enable
`TIM_CR1_UDIS`		1	Update disable
`TIM_CR1_URS`		2	Update request source
`TIM_CR1_OPM`		3	One pulse mode
`TIM_CR1_DIR`		4	Direction
`TIM_CR1_CMS`		5:6	CMS[1:0] bits (Center-aligned mode selection)
`TIM_CR1_ARPE`		7	Auto-reload preload enable
`TIM_CR1_CKD`		8:9	CKD[1:0] bits (clock division)
`CR2`	`0x04`	32	TIM control register 2
`TIM_CR2_CCDS`		3	Capture/Compare DMA Selection
`TIM_CR2_MMS`		4:6	MMS[2:0] bits (Master Mode Selection)
`TIM_CR2_TI1S`		7	TI1 Selection
`SMCR`	`0x08`	32	TIM slave Mode Control register
`TIM_SMCR_SMS`		0:2	SMS[2:0] bits (Slave mode selection)
`TIM_SMCR_TS`		4:6	TS[2:0] bits (Trigger selection)
`TIM_SMCR_MSM`		7	Master/slave mode
`TIM_SMCR_ETF`		8:11	ETF[3:0] bits (External trigger filter)
`TIM_SMCR_ETPS`		12:13	ETPS[1:0] bits (External trigger prescaler)
`TIM_SMCR_ECE`		14	External clock enable
`TIM_SMCR_ETP`		15	External trigger polarity
`DIER`	`0x0C`	32	TIM DMA/interrupt enable register
`TIM_DIER_UIE`		0	Update interrupt enable
`TIM_DIER_CC1IE`		1	Capture/Compare 1 interrupt enable
`TIM_DIER_CC2IE`		2	Capture/Compare 2 interrupt enable
`TIM_DIER_CC3IE`		3	Capture/Compare 3 interrupt enable
`TIM_DIER_CC4IE`		4	Capture/Compare 4 interrupt enable
`TIM_DIER_TIE`		6	Trigger interrupt enable
`TIM_DIER_UDE`		8	Update DMA request enable
`TIM_DIER_CC1DE`		9	Capture/Compare 1 DMA request enable
`TIM_DIER_CC2DE`		10	Capture/Compare 2 DMA request enable
`TIM_DIER_CC3DE`		11	Capture/Compare 3 DMA request enable
`TIM_DIER_CC4DE`		12	Capture/Compare 4 DMA request enable
`TIM_DIER_TDE`		14	Trigger DMA request enable
`SR`	`0x10`	32	TIM status register
`TIM_SR_UIF`		0	Update interrupt Flag
`TIM_SR_CC1IF`		1	Capture/Compare 1 interrupt Flag
`TIM_SR_CC2IF`		2	Capture/Compare 2 interrupt Flag
`TIM_SR_CC3IF`		3	Capture/Compare 3 interrupt Flag
`TIM_SR_CC4IF`		4	Capture/Compare 4 interrupt Flag
`TIM_SR_TIF`		6	Trigger interrupt Flag
`TIM_SR_CC1OF`		9	Capture/Compare 1 Overcapture Flag
`TIM_SR_CC2OF`		10	Capture/Compare 2 Overcapture Flag
`TIM_SR_CC3OF`		11	Capture/Compare 3 Overcapture Flag
`TIM_SR_CC4OF`		12	Capture/Compare 4 Overcapture Flag
`EGR`	`0x14`	32	TIM event generation register
`TIM_EGR_UG`		0	Update Generation
`TIM_EGR_CC1G`		1	Capture/Compare 1 Generation
`TIM_EGR_CC2G`		2	Capture/Compare 2 Generation
`TIM_EGR_CC3G`		3	Capture/Compare 3 Generation
`TIM_EGR_CC4G`		4	Capture/Compare 4 Generation
`TIM_EGR_TG`		6	Trigger Generation
`CCMR1`	`0x18`	32	TIM capture/compare mode register 1
`TIM_CCMR1_CC1S`		0:1	CC1S[1:0] bits (Capture/Compare 1 Selection)
`TIM_CCMR1_OC1FE`		2	Output Compare 1 Fast enable
`TIM_CCMR1_IC1PSC`		2:3	IC1PSC[1:0] bits (Input Capture 1 Prescaler)
`TIM_CCMR1_OC1PE`		3	Output Compare 1 Preload enable
`TIM_CCMR1_OC1M`		4:6	OC1M[2:0] bits (Output Compare 1 Mode)
`TIM_CCMR1_IC1F`		4:7	IC1F[3:0] bits (Input Capture 1 Filter)
`TIM_CCMR1_OC1CE`		7	Output Compare 1Clear Enable
`TIM_CCMR1_CC2S`		8:9	CC2S[1:0] bits (Capture/Compare 2 Selection)
`TIM_CCMR1_OC2FE`		10	Output Compare 2 Fast enable
`TIM_CCMR1_IC2PSC`		10:11	IC2PSC[1:0] bits (Input Capture 2 Prescaler)
`TIM_CCMR1_OC2PE`		11	Output Compare 2 Preload enable
`TIM_CCMR1_OC2M`		12:14	OC2M[2:0] bits (Output Compare 2 Mode)
`TIM_CCMR1_IC2F`		12:15	IC2F[3:0] bits (Input Capture 2 Filter)
`TIM_CCMR1_OC2CE`		15	Output Compare 2 Clear Enable
`CCMR2`	`0x1C`	32	TIM capture/compare mode register 2
`TIM_CCMR2_CC3S`		0:1	CC3S[1:0] bits (Capture/Compare 3 Selection)
`TIM_CCMR2_OC3FE`		2	Output Compare 3 Fast enable
`TIM_CCMR2_IC3PSC`		2:3	IC3PSC[1:0] bits (Input Capture 3 Prescaler)
`TIM_CCMR2_OC3PE`		3	Output Compare 3 Preload enable
`TIM_CCMR2_OC3M`		4:6	OC3M[2:0] bits (Output Compare 3 Mode)
`TIM_CCMR2_IC3F`		4:7	IC3F[3:0] bits (Input Capture 3 Filter)
`TIM_CCMR2_OC3CE`		7	Output Compare 3 Clear Enable
`TIM_CCMR2_CC4S`		8:9	CC4S[1:0] bits (Capture/Compare 4 Selection)
`TIM_CCMR2_OC4FE`		10	Output Compare 4 Fast enable
`TIM_CCMR2_IC4PSC`		10:11	IC4PSC[1:0] bits (Input Capture 4 Prescaler)
`TIM_CCMR2_OC4PE`		11	Output Compare 4 Preload enable
`TIM_CCMR2_OC4M`		12:14	OC4M[2:0] bits (Output Compare 4 Mode)
`TIM_CCMR2_IC4F`		12:15	IC4F[3:0] bits (Input Capture 4 Filter)
`TIM_CCMR2_OC4CE`		15	Output Compare 4 Clear Enable
`CCER`	`0x20`	32	TIM capture/compare enable register
`TIM_CCER_CC1E`		0	Capture/Compare 1 output enable
`TIM_CCER_CC1P`		1	Capture/Compare 1 output Polarity
`TIM_CCER_CC1NP`		3	Capture/Compare 1 Complementary output Polarity
`TIM_CCER_CC2E`		4	Capture/Compare 2 output enable
`TIM_CCER_CC2P`		5	Capture/Compare 2 output Polarity
`TIM_CCER_CC2NP`		7	Capture/Compare 2 Complementary output Polarity
`TIM_CCER_CC3E`		8	Capture/Compare 3 output enable
`TIM_CCER_CC3P`		9	Capture/Compare 3 output Polarity
`TIM_CCER_CC3NP`		11	Capture/Compare 3 Complementary output Polarity
`TIM_CCER_CC4E`		12	Capture/Compare 4 output enable
`TIM_CCER_CC4P`		13	Capture/Compare 4 output Polarity
`TIM_CCER_CC4NP`		15	Capture/Compare 4 Complementary output Polarity
`CNT`	`0x24`	32	TIM counter register
`TIM_CNT_CNT`		0:15	Counter Value
`PSC`	`0x28`	32	TIM prescaler register
`TIM_PSC_PSC`		0:15	Prescaler Value
`ARR`	`0x2C`	32	TIM auto-reload register
`TIM_ARR_ARR`		0:15	actual auto-reload Value
`CCR1`	`0x34`	32	TIM capture/compare register 1
`TIM_CCR1_CCR1`		0:15	Capture/Compare 1 Value
`CCR2`	`0x38`	32	TIM capture/compare register 2
`TIM_CCR2_CCR2`		0:15	Capture/Compare 2 Value
`CCR3`	`0x3C`	32	TIM capture/compare register 3
`TIM_CCR3_CCR3`		0:15	Capture/Compare 3 Value
`CCR4`	`0x40`	32	TIM capture/compare register 4
`TIM_CCR4_CCR4`		0:15	Capture/Compare 4 Value
`DCR`	`0x48`	32	TIM DMA control register
`TIM_DCR_DBA`		0:4	DBA[4:0] bits (DMA Base Address)
`TIM_DCR_DBL`		8:12	DBL[4:0] bits (DMA Burst Length)
`DMAR`	`0x4C`	32	TIM DMA address for full transfer register
`TIM_DMAR_DMAB`		0:15	DMA register for burst accesses
`OR`	`0x50`	32	TIM option register

LPTIM — Таймер с малым потреблением (раздел 46)

Регистр	Смещение	Бит	Назначение
`ISR`	`0x00`	32	LPTIM Interrupt and Status register
`LPTIM_ISR_CMPM`		0	Compare match
`LPTIM_ISR_ARRM`		1	Autoreload match
`LPTIM_ISR_EXTTRIG`		2	External trigger edge event
`LPTIM_ISR_CMPOK`		3	Compare register update OK
`LPTIM_ISR_ARROK`		4	Autoreload register update OK
`LPTIM_ISR_UP`		5	Counter direction change down to up
`LPTIM_ISR_DOWN`		6	Counter direction change up to down
`ICR`	`0x04`	32	LPTIM Interrupt Clear register
`LPTIM_ICR_CMPMCF`		0	Compare match Clear Flag
`LPTIM_ICR_ARRMCF`		1	Autoreload match Clear Flag
`LPTIM_ICR_EXTTRIGCF`		2	External trigger edge event Clear Flag
`LPTIM_ICR_CMPOKCF`		3	Compare register update OK Clear Flag
`LPTIM_ICR_ARROKCF`		4	Autoreload register update OK Clear Flag
`LPTIM_ICR_UPCF`		5	Counter direction change down to up Clear Flag
`LPTIM_ICR_DOWNCF`		6	Counter direction change up to down Clear Flag
`IER`	`0x08`	32	LPTIM Interrupt Enable register
`LPTIM_IER_CMPMIE`		0	Compare match Interrupt Enable
`LPTIM_IER_ARRMIE`		1	Autoreload match Interrupt Enable
`LPTIM_IER_EXTTRIGIE`		2	External trigger edge event Interrupt Enable
`LPTIM_IER_CMPOKIE`		3	Compare register update OK Interrupt Enable
`LPTIM_IER_ARROKIE`		4	Autoreload register update OK Interrupt Enable
`LPTIM_IER_UPIE`		5	Counter direction change down to up Interrupt Enable
`LPTIM_IER_DOWNIE`		6	Counter direction change up to down Interrupt Enable
`CFGR`	`0x0C`	32	LPTIM Configuration register
`LPTIM_CFGR_CKSEL`		0	Clock selector
`LPTIM_CFGR_CKPOL`		1:2	CKPOL[1:0] bits (Clock polarity)
`LPTIM_CFGR_CKFLT`		3:4	CKFLT[1:0] bits (Configurable digital filter for external clock)
`LPTIM_CFGR_TRGFLT`		6:7	TRGFLT[1:0] bits (Configurable digital filter for trigger)
`LPTIM_CFGR_PRESC`		9:11	PRESC[2:0] bits (Clock prescaler)
`LPTIM_CFGR_TRIGSEL`		13:15	TRIGSEL[2:0]] bits (Trigger selector)
`LPTIM_CFGR_TRIGEN`		17:18	TRIGEN[1:0] bits (Trigger enable and polarity)
`LPTIM_CFGR_TIMOUT`		19	Timout enable
`LPTIM_CFGR_WAVE`		20	Waveform shape
`LPTIM_CFGR_WAVPOL`		21	Waveform shape polarity
`LPTIM_CFGR_PRELOAD`		22	Reg update mode
`LPTIM_CFGR_COUNTMODE`		23	Counter mode enable
`LPTIM_CFGR_ENC`		24	Encoder mode enable
`CR`	`0x10`	32	LPTIM Control register
`LPTIM_CR_ENABLE`		0	LPTIMer enable
`LPTIM_CR_SNGSTRT`		1	Timer start in single mode
`LPTIM_CR_CNTSTRT`		2	Timer start in continuous mode
`CMP`	`0x14`	32	LPTIM Compare register
`LPTIM_CMP_CMP`		0:15	Compare register
`ARR`	`0x18`	32	LPTIM Autoreload register
`LPTIM_ARR_ARR`		0:15	Auto reload register
`CNT`	`0x1C`	32	LPTIM Counter register
`LPTIM_CNT_CNT`		0:15	Counter register

ADC — АЦП (раздел 14)

Регистр	Смещение	Бит	Назначение
`ISR`	`0x00`	32	ADC Interrupt and Status register
`ADC_ISR_ADRDY`		0	ADC Ready
`ADC_ISR_EOSMP`		1	End of sampling flag
`ADC_ISR_EOC`		2	End of Conversion
`ADC_ISR_EOSEQ`		3	End of Sequence flag
`ADC_ISR_OVR`		4	Overrun flag
`ADC_ISR_AWD`		7	Analog watchdog flag
`ADC_ISR_EOCAL`		11	End of calibration flag
`IER`	`0x04`	32	ADC Interrupt Enable register
`ADC_IER_ADRDYIE`		0	ADC Ready interrupt enable
`ADC_IER_EOSMPIE`		1	End of sampling interrupt enable
`ADC_IER_EOCIE`		2	End of Conversion interrupt enable
`ADC_IER_EOSEQIE`		3	End of Sequence of conversion interrupt enable
`ADC_IER_OVRIE`		4	Overrun interrupt enable
`ADC_IER_AWDIE`		7	Analog Watchdog interrupt enable
`ADC_IER_EOCALIE`		11	Enf Of Calibration interrupt enable
`CR`	`0x08`	32	ADC Control register
`ADC_CR_ADEN`		0	ADC enable control
`ADC_CR_ADDIS`		1	ADC disable command
`ADC_CR_ADSTART`		2	ADC start of conversion
`ADC_CR_ADSTP`		4	ADC stop of conversion command
`ADC_CR_ADVREGEN`		28	ADC Voltage Regulator Enable
`ADC_CR_ADCAL`		31	ADC calibration
`CFGR1`	`0x0C`	32	ADC Configuration register 1
`ADC_CFGR1_DMAEN`		0	Direct memory access enable
`ADC_CFGR1_DMACFG`		1	Direct memory access configuration
`ADC_CFGR1_SCANDIR`		2	Sequence scan direction
`ADC_CFGR1_RES`		3:4	RES[1:0] bits (Resolution)
`ADC_CFGR1_ALIGN`		5	Data Alignment
`ADC_CFGR1_EXTSEL`		6:8	EXTSEL[2:0] bits (External Event Select for regular group)
`ADC_CFGR1_EXTEN`		10:11	EXTEN[1:0] bits (External Trigger Conversion mode for regular channels)
`ADC_CFGR1_OVRMOD`		12	Overrun mode
`ADC_CFGR1_CONT`		13	Continuous Conversion
`ADC_CFGR1_WAIT`		14	ADC wait conversion mode
`ADC_CFGR1_AUTOFF`		15	ADC auto power off
`ADC_CFGR1_DISCEN`		16	Discontinuous mode on regular channels
`ADC_CFGR1_AWDSGL`		22	Enable the watchdog on a single channel or on all channels
`ADC_CFGR1_AWDEN`		23	Analog watchdog enable on regular channels
`ADC_CFGR1_AWDCH`		26:30	AWDCH[4:0] bits (Analog watchdog channel select bits)
`CFGR2`	`0x10`	32	ADC Configuration register 2
`ADC_CFGR2_OVSE`		0	Oversampler Enable
`ADC_CFGR2_OVSR`		2:4	OVSR [2:0] bits (Oversampling ratio)
`ADC_CFGR2_OVSS`		5:8	OVSS [3:0] bits (Oversampling shift)
`ADC_CFGR2_TOVS`		9:31	Triggered Oversampling
`ADC_CFGR2_CKMODE`		30:31	CKMODE [1:0] bits (ADC clock mode)
`SMPR`	`0x14`	32	ADC Sampling time register
`ADC_SMPR_SMP`		0:2	SMPR[2:0] bits (Sampling time selection)
`TR`	`0x20`	32	ADC watchdog threshold register
`ADC_TR_LT`		0:11	Analog watchdog low threshold
`ADC_TR_HT`		16:27	Analog watchdog high threshold
`CHSELR`	`0x28`	32	ADC channel selection register
`ADC_CHSELR_CHSEL`		0:18	ADC group regular sequencer channels
`ADC_CHSELR_CHSEL0`		0	Channel 0 selection
`ADC_CHSELR_CHSEL1`		1	Channel 1 selection
`ADC_CHSELR_CHSEL2`		2	Channel 2 selection
`ADC_CHSELR_CHSEL3`		3	Channel 3 selection
`ADC_CHSELR_CHSEL4`		4	Channel 4 selection
`ADC_CHSELR_CHSEL5`		5	Channel 5 selection
`ADC_CHSELR_CHSEL6`		6	Channel 6 selection
`ADC_CHSELR_CHSEL7`		7	Channel 7 selection
`ADC_CHSELR_CHSEL8`		8	Channel 8 selection
`ADC_CHSELR_CHSEL9`		9	Channel 9 selection
`ADC_CHSELR_CHSEL10`		10	Channel 10 selection
`ADC_CHSELR_CHSEL11`		11	Channel 11 selection
`ADC_CHSELR_CHSEL12`		12	Channel 12 selection
`ADC_CHSELR_CHSEL13`		13	Channel 13 selection
`ADC_CHSELR_CHSEL14`		14	Channel 14 selection
`ADC_CHSELR_CHSEL15`		15	Channel 15 selection
`ADC_CHSELR_CHSEL16`		16	Channel 16 selection
`ADC_CHSELR_CHSEL17`		17	Channel 17 selection
`ADC_CHSELR_CHSEL18`		18	Channel 18 selection
`DR`	`0x40`	32	ADC data register
`ADC_DR_DATA`		0:15	Regular data
`CALFACT`	`0xB4`	32	ADC data register
`ADC_CALFACT_CALFACT`		0:6	Calibration factor

ADC_Common — АЦП: общие регистры (раздел 14)

Регистр	Смещение	Бит	Назначение
`CCR`	`0x00`	32
`ADC_CCR_PRESC`		18:21	PRESC [3:0] bits (ADC prescaler)
`ADC_CCR_VREFEN`		22	Vrefint enable
`ADC_CCR_TSEN`		23	Temperature sensore enable
`ADC_CCR_VLCDEN`		24	Voltage LCD enable
`ADC_CCR_LFMEN`		25	Low Frequency Mode enable

DAC — ЦАП (раздел 15)

Регистр	Смещение	Бит	Назначение
`CR`	`0x00`	32	DAC control register
`DAC_CR_EN1`		0	DAC channel1 enable
`DAC_CR_BOFF1`		1	DAC channel1 output buffer disable
`DAC_CR_TEN1`		2	DAC channel1 Trigger enable
`DAC_CR_TSEL1`		3:5	TSEL1[2:0] (DAC channel1 Trigger selection)
`DAC_CR_WAVE1`		6:7	WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
`DAC_CR_MAMP1`		8:11	MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
`DAC_CR_DMAEN1`		12	DAC channel1 DMA enable
`DAC_CR_DMAUDRIE1`		13	DAC channel1 DMA Underrun interrupt enable
`SWTRIGR`	`0x04`	32	DAC software trigger register
`DAC_SWTRIGR_SWTRIG1`		0	DAC channel1 software trigger
`DHR12R1`	`0x08`	32	DAC channel1 12-bit right-aligned data holding register
`DAC_DHR12R1_DACC1DHR`		0:11	DAC channel1 12-bit Right aligned data
`DHR12L1`	`0x0C`	32	DAC channel1 12-bit left aligned data holding register
`DAC_DHR12L1_DACC1DHR`		4:15	DAC channel1 12-bit Left aligned data
`DHR8R1`	`0x10`	32	DAC channel1 8-bit right aligned data holding register
`DAC_DHR8R1_DACC1DHR`		0:7	DAC channel1 8-bit Right aligned data
`DOR1`	`0x2C`	32	DAC channel1 data output register
`DAC_DOR1_DACC1DOR`		0:11	DAC channel1 data output
`SR`	`0x34`	32	DAC status register
`DAC_SR_DMAUDR1`		13	DAC channel1 DMA underrun flag

COMP — Компаратор (раздел 44)

Регистр	Смещение	Бит	Назначение
`CSR`	`0x00`	32	COMP comparator control and status register
`COMP_CSR_COMP1EN`		0	COMP1 enable
`COMP_CSR_COMP2EN`		0	COMP2 enable
`COMP_CSR_COMPxEN`		0	COMPx enable
`COMP_CSR_COMP2SPEED`		3	COMP2 power mode
`COMP_CSR_COMP1INNSEL`		4:5	COMP1 inverting input select
`COMP_CSR_COMP2INNSEL`		4:6	COMP2 inverting input select
`COMP_CSR_COMP1WM`		8	Comparators window mode enable
`COMP_CSR_COMP2INPSEL`		8:10	COMPx non inverting input select
`COMP_CSR_COMP1LPTIM1IN1`		12	COMP1 LPTIM1 IN1 connection
`COMP_CSR_COMP2LPTIM1IN2`		12	COMP2 LPTIM1 IN2 connection
`COMP_CSR_COMP2LPTIM1IN1`		13	COMP2 LPTIM1 IN1 connection
`COMP_CSR_COMP1POLARITY`		15	COMP1 output polarity
`COMP_CSR_COMP2POLARITY`		15	COMP2 output polarity
`COMP_CSR_COMPxPOLARITY`		15	COMPx output polarity
`COMP_CSR_COMP1VALUE`		30	COMP1 output level
`COMP_CSR_COMP2VALUE`		30	COMP2 output level
`COMP_CSR_COMPxOUTVALUE`		30	COMPx output level
`COMP_CSR_COMP1LOCK`		31	COMP1 lock
`COMP_CSR_COMP2LOCK`		31	COMP2 lock
`COMP_CSR_COMPxLOCK`		31	COMPx lock

USART — UART / USART / LPUART (раздел 16)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	USART Control register 1
`USART_CR1_UE`		0	USART Enable
`USART_CR1_UESM`		1	USART Enable in STOP Mode
`USART_CR1_RE`		2	Receiver Enable
`USART_CR1_TE`		3	Transmitter Enable
`USART_CR1_IDLEIE`		4	IDLE Interrupt Enable
`USART_CR1_RXNEIE`		5	RXNE Interrupt Enable
`USART_CR1_TCIE`		6	Transmission Complete Interrupt Enable
`USART_CR1_TXEIE`		7	TXE Interrupt Enable
`USART_CR1_PEIE`		8	PE Interrupt Enable
`USART_CR1_PS`		9	Parity Selection
`USART_CR1_PCE`		10	Parity Control Enable
`USART_CR1_WAKE`		11	Receiver Wakeup method
`USART_CR1_M`		12:28	Word length
`USART_CR1_M0`		12	Word length - Bit 0
`USART_CR1_MME`		13	Mute Mode Enable
`USART_CR1_CMIE`		14	Character match interrupt enable
`USART_CR1_OVER8`		15	Oversampling by 8-bit or 16-bit mode
`USART_CR1_DEDT`		16:20	DEDT[4:0] bits (Driver Enable Deassertion Time)
`USART_CR1_DEAT`		21:25	DEAT[4:0] bits (Driver Enable Assertion Time)
`USART_CR1_RTOIE`		26	Receive Time Out interrupt enable
`USART_CR1_EOBIE`		27	End of Block interrupt enable
`USART_CR1_M1`		28	Word length - Bit 1
`CR2`	`0x04`	32	USART Control register 2
`USART_CR2_ADDM7`		4	7-bit or 4-bit Address Detection
`USART_CR2_LBDL`		5	LIN Break Detection Length
`USART_CR2_LBDIE`		6	LIN Break Detection Interrupt Enable
`USART_CR2_LBCL`		8	Last Bit Clock pulse
`USART_CR2_CPHA`		9	Clock Phase
`USART_CR2_CPOL`		10	Clock Polarity
`USART_CR2_CLKEN`		11	Clock Enable
`USART_CR2_STOP`		12:13	STOP[1:0] bits (STOP bits)
`USART_CR2_LINEN`		14	LIN mode enable
`USART_CR2_SWAP`		15	SWAP TX/RX pins
`USART_CR2_RXINV`		16	RX pin active level inversion
`USART_CR2_TXINV`		17	TX pin active level inversion
`USART_CR2_DATAINV`		18	Binary data inversion
`USART_CR2_MSBFIRST`		19	Most Significant Bit First
`USART_CR2_ABREN`		20	Auto Baud-Rate Enable
`USART_CR2_ABRMODE`		21:22	ABRMOD[1:0] bits (Auto Baud-Rate Mode)
`USART_CR2_RTOEN`		23	Receiver Time-Out enable
`USART_CR2_ADD`		24:31	Address of the USART node
`CR3`	`0x08`	32	USART Control register 3
`USART_CR3_EIE`		0	Error Interrupt Enable
`USART_CR3_IREN`		1	IrDA mode Enable
`USART_CR3_IRLP`		2	IrDA Low-Power
`USART_CR3_HDSEL`		3	Half-Duplex Selection
`USART_CR3_NACK`		4	SmartCard NACK enable
`USART_CR3_SCEN`		5	SmartCard mode enable
`USART_CR3_DMAR`		6	DMA Enable Receiver
`USART_CR3_DMAT`		7	DMA Enable Transmitter
`USART_CR3_RTSE`		8	RTS Enable
`USART_CR3_CTSE`		9	CTS Enable
`USART_CR3_CTSIE`		10	CTS Interrupt Enable
`USART_CR3_ONEBIT`		11	One sample bit method enable
`USART_CR3_OVRDIS`		12	Overrun Disable
`USART_CR3_DDRE`		13	DMA Disable on Reception Error
`USART_CR3_DEM`		14	Driver Enable Mode
`USART_CR3_DEP`		15	Driver Enable Polarity Selection
`USART_CR3_SCARCNT`		17:19	SCARCNT[2:0] bits (SmartCard Auto-Retry Count)
`USART_CR3_WUS`		20:21	WUS[1:0] bits (Wake UP Interrupt Flag Selection)
`USART_CR3_WUFIE`		22	Wake Up Interrupt Enable
`USART_CR3_UCESM`		23	Clock Enable in Stop mode
`BRR`	`0x0C`	32	USART Baud rate register
`USART_BRR_DIV_FRACTION`		0:3	Fraction of USARTDIV
`USART_BRR_DIV_MANTISSA`		4:15	Mantissa of USARTDIV
`GTPR`	`0x10`	32	USART Guard time and prescaler register
`USART_GTPR_PSC`		0:7	PSC[7:0] bits (Prescaler value)
`USART_GTPR_GT`		8:15	GT[7:0] bits (Guard time value)
`RTOR`	`0x14`	32	USART Receiver Time Out register
`USART_RTOR_RTO`		0:23	Receiver Time Out Value
`USART_RTOR_BLEN`		24:31	Block Length
`RQR`	`0x18`	32	USART Request register
`USART_RQR_ABRRQ`		0	Auto-Baud Rate Request
`USART_RQR_SBKRQ`		1	Send Break Request
`USART_RQR_MMRQ`		2	Mute Mode Request
`USART_RQR_RXFRQ`		3	Receive Data flush Request
`USART_RQR_TXFRQ`		4	Transmit data flush Request
`ISR`	`0x1C`	32	USART Interrupt and status register
`USART_ISR_PE`		0	Parity Error
`USART_ISR_FE`		1	Framing Error
`USART_ISR_NE`		2	Noise detected Flag
`USART_ISR_ORE`		3	OverRun Error
`USART_ISR_IDLE`		4	IDLE line detected
`USART_ISR_RXNE`		5	Read Data Register Not Empty
`USART_ISR_TC`		6	Transmission Complete
`USART_ISR_TXE`		7	Transmit Data Register Empty
`USART_ISR_LBDF`		8	LIN Break Detection Flag
`USART_ISR_CTSIF`		9	CTS interrupt flag
`USART_ISR_CTS`		10	CTS flag
`USART_ISR_RTOF`		11	Receiver Time Out
`USART_ISR_EOBF`		12	End Of Block Flag
`USART_ISR_ABRE`		14	Auto-Baud Rate Error
`USART_ISR_ABRF`		15	Auto-Baud Rate Flag
`USART_ISR_BUSY`		16	Busy Flag
`USART_ISR_CMF`		17	Character Match Flag
`USART_ISR_SBKF`		18	Send Break Flag
`USART_ISR_RWU`		19	Receive Wake Up from mute mode Flag
`USART_ISR_WUF`		20	Wake Up from stop mode Flag
`USART_ISR_TEACK`		21	Transmit Enable Acknowledge Flag
`USART_ISR_REACK`		22	Receive Enable Acknowledge Flag
`ICR`	`0x20`	32	USART Interrupt flag Clear register
`USART_ICR_PECF`		0	Parity Error Clear Flag
`USART_ICR_FECF`		1	Framing Error Clear Flag
`USART_ICR_NCF`		2	Noise detected Clear Flag
`USART_ICR_ORECF`		3	OverRun Error Clear Flag
`USART_ICR_IDLECF`		4	IDLE line detected Clear Flag
`USART_ICR_TCCF`		6	Transmission Complete Clear Flag
`USART_ICR_LBDCF`		8	LIN Break Detection Clear Flag
`USART_ICR_CTSCF`		9	CTS Interrupt Clear Flag
`USART_ICR_RTOCF`		11	Receiver Time Out Clear Flag
`USART_ICR_EOBCF`		12	End Of Block Clear Flag
`USART_ICR_CMCF`		17	Character Match Clear Flag
`USART_ICR_WUCF`		20	Wake Up from stop mode Clear Flag
`RDR`	`0x24`	32	USART Receive Data register
`USART_RDR_RDR`		0:8	RDR[8:0] bits (Receive Data value)
`TDR`	`0x28`	32	USART Transmit Data register
`USART_TDR_TDR`		0:8	TDR[8:0] bits (Transmit Data value)

I2C — I²C (раздел 17)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	I2C Control register 1
`I2C_CR1_PE`		0	Peripheral enable
`I2C_CR1_TXIE`		1	TX interrupt enable
`I2C_CR1_RXIE`		2	RX interrupt enable
`I2C_CR1_ADDRIE`		3	Address match interrupt enable
`I2C_CR1_NACKIE`		4	NACK received interrupt enable
`I2C_CR1_STOPIE`		5	STOP detection interrupt enable
`I2C_CR1_TCIE`		6	Transfer complete interrupt enable
`I2C_CR1_ERRIE`		7	Errors interrupt enable
`I2C_CR1_DNF`		8:11	Digital noise filter
`I2C_CR1_ANFOFF`		12	Analog noise filter OFF
`I2C_CR1_TXDMAEN`		14	DMA transmission requests enable
`I2C_CR1_RXDMAEN`		15	DMA reception requests enable
`I2C_CR1_SBC`		16	Slave byte control
`I2C_CR1_NOSTRETCH`		17	Clock stretching disable
`I2C_CR1_WUPEN`		18	Wakeup from STOP enable
`I2C_CR1_GCEN`		19	General call enable
`I2C_CR1_SMBHEN`		20	SMBus host address enable
`I2C_CR1_SMBDEN`		21	SMBus device default address enable
`I2C_CR1_ALERTEN`		22	SMBus alert enable
`I2C_CR1_PECEN`		23	PEC enable
`CR2`	`0x04`	32	I2C Control register 2
`I2C_CR2_SADD`		0:9	Slave address (master mode)
`I2C_CR2_RD_WRN`		10	Transfer direction (master mode)
`I2C_CR2_ADD10`		11	10-bit addressing mode (master mode)
`I2C_CR2_HEAD10R`		12	10-bit address header only read direction (master mode)
`I2C_CR2_START`		13	START generation
`I2C_CR2_STOP`		14	STOP generation (master mode)
`I2C_CR2_NACK`		15	NACK generation (slave mode)
`I2C_CR2_NBYTES`		16:23	Number of bytes
`I2C_CR2_RELOAD`		24	NBYTES reload mode
`I2C_CR2_AUTOEND`		25	Automatic end mode (master mode)
`I2C_CR2_PECBYTE`		26	Packet error checking byte
`OAR1`	`0x08`	32	I2C Own address 1 register
`I2C_OAR1_OA1`		0:9	Interface own address 1
`I2C_OAR1_OA1MODE`		10	Own address 1 10-bit mode
`I2C_OAR1_OA1EN`		15	Own address 1 enable
`OAR2`	`0x0C`	32	I2C Own address 2 register
`I2C_OAR2_OA2`		1:7	Interface own address 2
`I2C_OAR2_OA2MSK`		8:10	Own address 2 masks
`I2C_OAR2_OA2MASK01`		8	OA2[1] is masked, Only OA2[7:2] are compared
`I2C_OAR2_OA2MASK03`		8:9	OA2[3:1] is masked, Only OA2[7:4] are compared
`I2C_OAR2_OA2MASK05`		8:10	OA2[5:1] is masked, Only OA2[7:6] are compared
`I2C_OAR2_OA2MASK07`		8:10	OA2[7:1] is masked, No comparison is done
`I2C_OAR2_OA2MASK02`		9	OA2[2:1] is masked, Only OA2[7:3] are compared
`I2C_OAR2_OA2MASK06`		9:10	OA2[6:1] is masked, Only OA2[7] are compared
`I2C_OAR2_OA2MASK04`		10	OA2[4:1] is masked, Only OA2[7:5] are compared
`I2C_OAR2_OA2EN`		15	Own address 2 enable
`TIMINGR`	`0x10`	32	I2C Timing register
`I2C_TIMINGR_SCLL`		0:7	SCL low period (master mode)
`I2C_TIMINGR_SCLH`		8:15	SCL high period (master mode)
`I2C_TIMINGR_SDADEL`		16:19	Data hold time
`I2C_TIMINGR_SCLDEL`		20:23	Data setup time
`I2C_TIMINGR_PRESC`		28:31	Timings prescaler
`TIMEOUTR`	`0x14`	32	I2C Timeout register
`I2C_TIMEOUTR_TIMEOUTA`		0:11	Bus timeout A
`I2C_TIMEOUTR_TIDLE`		12	Idle clock timeout detection
`I2C_TIMEOUTR_TIMOUTEN`		15	Clock timeout enable
`I2C_TIMEOUTR_TIMEOUTB`		16:27	Bus timeout B
`I2C_TIMEOUTR_TEXTEN`		31	Extended clock timeout enable
`ISR`	`0x18`	32	I2C Interrupt and status register
`I2C_ISR_TXE`		0	Transmit data register empty
`I2C_ISR_TXIS`		1	Transmit interrupt status
`I2C_ISR_RXNE`		2	Receive data register not empty
`I2C_ISR_ADDR`		3	Address matched (slave mode)
`I2C_ISR_NACKF`		4	NACK received flag
`I2C_ISR_STOPF`		5	STOP detection flag
`I2C_ISR_TC`		6	Transfer complete (master mode)
`I2C_ISR_TCR`		7	Transfer complete reload
`I2C_ISR_BERR`		8	Bus error
`I2C_ISR_ARLO`		9	Arbitration lost
`I2C_ISR_OVR`		10	Overrun/Underrun
`I2C_ISR_PECERR`		11	PEC error in reception
`I2C_ISR_TIMEOUT`		12	Timeout or Tlow detection flag
`I2C_ISR_ALERT`		13	SMBus alert
`I2C_ISR_BUSY`		15	Bus busy
`I2C_ISR_DIR`		16	Transfer direction (slave mode)
`I2C_ISR_ADDCODE`		17:23	Address match code (slave mode)
`ICR`	`0x1C`	32	I2C Interrupt clear register
`I2C_ICR_ADDRCF`		3	Address matched clear flag
`I2C_ICR_NACKCF`		4	NACK clear flag
`I2C_ICR_STOPCF`		5	STOP detection clear flag
`I2C_ICR_BERRCF`		8	Bus error clear flag
`I2C_ICR_ARLOCF`		9	Arbitration lost clear flag
`I2C_ICR_OVRCF`		10	Overrun/Underrun clear flag
`I2C_ICR_PECCF`		11	PAC error clear flag
`I2C_ICR_TIMOUTCF`		12	Timeout clear flag
`I2C_ICR_ALERTCF`		13	Alert clear flag
`PECR`	`0x20`	32	I2C PEC register
`I2C_PECR_PEC`		0:7	PEC register
`RXDR`	`0x24`	32	I2C Receive data register
`I2C_RXDR_RXDATA`		0:7	8-bit receive data
`TXDR`	`0x28`	32	I2C Transmit data register
`I2C_TXDR_TXDATA`		0:7	8-bit transmit data

SPI — SPI / I²S (раздел 18)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	SPI Control register 1 (not used in I2S mode)
`SPI_CR1_CPHA`		0	Clock Phase
`SPI_CR1_CPOL`		1	Clock Polarity
`SPI_CR1_MSTR`		2	Master Selection
`SPI_CR1_BR`		3:5	BR[2:0] bits (Baud Rate Control)
`SPI_CR1_SPE`		6	SPI Enable
`SPI_CR1_LSBFIRST`		7	Frame Format
`SPI_CR1_SSI`		8	Internal slave select
`SPI_CR1_SSM`		9	Software slave management
`SPI_CR1_RXONLY`		10	Receive only
`SPI_CR1_DFF`		11	Data Frame Format
`SPI_CR1_CRCNEXT`		12	Transmit CRC next
`SPI_CR1_CRCEN`		13	Hardware CRC calculation enable
`SPI_CR1_BIDIOE`		14	Output enable in bidirectional mode
`SPI_CR1_BIDIMODE`		15	Bidirectional data mode enable
`CR2`	`0x04`	32	SPI Control register 2
`SPI_CR2_RXDMAEN`		0	Rx Buffer DMA Enable
`SPI_CR2_TXDMAEN`		1	Tx Buffer DMA Enable
`SPI_CR2_SSOE`		2	SS Output Enable
`SPI_CR2_FRF`		4	Frame Format Enable
`SPI_CR2_ERRIE`		5	Error Interrupt Enable
`SPI_CR2_RXNEIE`		6	RX buffer Not Empty Interrupt Enable
`SPI_CR2_TXEIE`		7	Tx buffer Empty Interrupt Enable
`SR`	`0x08`	32	SPI Status register
`SPI_SR_RXNE`		0	Receive buffer Not Empty
`SPI_SR_TXE`		1	Transmit buffer Empty
`SPI_SR_CHSIDE`		2	Channel side
`SPI_SR_UDR`		3	Underrun flag
`SPI_SR_CRCERR`		4	CRC Error flag
`SPI_SR_MODF`		5	Mode fault
`SPI_SR_OVR`		6	Overrun flag
`SPI_SR_BSY`		7	Busy flag
`SPI_SR_FRE`		8	TI frame format error
`DR`	`0x0C`	32	SPI data register
`SPI_DR_DR`		0:15	Data Register
`CRCPR`	`0x10`	32	SPI CRC polynomial register (not used in I2S mode)
`SPI_CRCPR_CRCPOLY`		0:15	CRC polynomial register
`RXCRCR`	`0x14`	32	SPI Rx CRC register (not used in I2S mode)
`SPI_RXCRCR_RXCRC`		0:15	Rx CRC Register
`TXCRCR`	`0x18`	32	SPI Tx CRC register (not used in I2S mode)
`SPI_TXCRCR_TXCRC`		0:15	Tx CRC Register
`I2SCFGR`	`0x1C`	32	SPI_I2S configuration register
`SPI_I2SCFGR_CHLEN`		0	Channel length (number of bits per audio channel)
`SPI_I2SCFGR_DATLEN`		1:2	DATLEN[1:0] bits (Data length to be transferred)
`SPI_I2SCFGR_CKPOL`		3	steady state clock polarity
`SPI_I2SCFGR_I2SSTD`		4:5	I2SSTD[1:0] bits (I2S standard selection)
`SPI_I2SCFGR_PCMSYNC`		7	PCM frame synchronization
`SPI_I2SCFGR_I2SCFG`		8:9	I2SCFG[1:0] bits (I2S configuration mode)
`SPI_I2SCFGR_I2SE`		10	I2S Enable
`SPI_I2SCFGR_I2SMOD`		11	I2S mode selection
`I2SPR`	`0x20`	32	SPI_I2S prescaler register
`SPI_I2SPR_I2SDIV`		0:7	I2S Linear prescaler
`SPI_I2SPR_ODD`		8	Odd factor for the prescaler
`SPI_I2SPR_MCKOE`		9	Master Clock Output Enable

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