STM32F103, STM32F407 · level reference · 6 min read

Appendix F. Abbreviations

The abbreviations that datasheets, reference manuals and headers are written in. The full English-Russian dictionary of terms is section 40; here you find only abbreviations: what each one stands for, what it means in plain words and where it appears in the handbook. The order is alphabetical.

F.1 Core and architecture

Abbreviation	Expansion	In plain words	§
AHB	Advanced High-performance Bus	fast bus of the core and memory	1, 6
APB	Advanced Peripheral Bus	peripheral bus; STM32 has two, APB1 slow, APB2 fast	6
BASEPRI	Base Priority mask	threshold for masking interrupts by priority	28
CCM	Core Coupled Memory	memory connected directly to the core; DMA cannot access it	9, 11
CMSIS	Cortex Microcontroller Software Interface Standard	standard layer for accessing the core and registers	5, B
CPU	Central Processing Unit	processor core	1
DWT	Data Watchpoint and Trace	unit with watchpoints and a cycle counter	35
FPU	Floating-Point Unit	floating-point unit; present on M4F, absent on M3	1, 24
ISR	Interrupt Service Routine	interrupt handler	7
ITM	Instrumentation Trace Macrocell	trace module, output on SWO	21
MPU	Memory Protection Unit	memory protection unit	11
MSP / PSP	Main / Process Stack Pointer	stack pointers: main and process	23
NMI	Non-Maskable Interrupt	interrupt that cannot be masked	7
NVIC	Nested Vectored Interrupt Controller	controller of nested interrupts	7
PRIMASK	Priority Mask	mask of all interrupts except NMI and faults	B
SCB	System Control Block	system control block: reset, faults, exception priorities	7, 35
SWD	Serial Wire Debug	two-wire debugging	4
SWO	Serial Wire Output	single-wire trace output	21
TPIU	Trace Port Interface Unit	unit that forms the trace stream	21
VTOR	Vector Table Offset Register	offset of the vector table	11
WFI / WFE	Wait For Interrupt / Event	wait for an interrupt / event, entry into sleep	10, 33

F.2 Clocks and power

Abbreviation	Expansion	In plain words	§
CSS	Clock Security System	protection against loss of the external clock	6
HSE / HSI	High-Speed External / Internal	external crystal / internal RC oscillator, MHz	6
LSE / LSI	Low-Speed External / Internal	32768 Hz watch crystal / internal ~40 kHz	6, 12
MCO	Microcontroller Clock Output	internal clock brought out to a pin	6
PLL	Phase-Locked Loop	frequency multiplier	6
PVD	Programmable Voltage Detector	supply brown-out detector	10
PWR	Power control	power control block	10
RCC	Reset and Clock Control	reset and clocking	6
VBAT	Battery voltage	backup supply for the clock and backup registers	12
VDDA	Analog supply	supply of the analog part and ADC reference	14

F.3 Peripherals

Abbreviation	Expansion	In plain words	§
ADC	Analog-to-Digital Converter	turns a voltage into a number	14
AFIO	Alternate Function I/O	remapping of alternate functions (F1 only)	8
bxCAN	Basic Extended CAN	the CAN controller of STM32	19
CAN	Controller Area Network	CAN bus	19
CRC	Cyclic Redundancy Check	checksum, hardware unit	12
DAC	Digital-to-Analog Converter	turns a number into a voltage	15
DMA	Direct Memory Access	direct memory access	9
EXTI	External Interrupt	external interrupts on pins	7
FSMC / FMC	Flexible Static/Memory Controller	external memory controller	41
GPIO	General-Purpose Input/Output	input/output ports	8
I²C	Inter-Integrated Circuit	two-wire bus	17
I²S	Inter-IC Sound	audio bus, an SPI mode	18, E
IWDG / WWDG	Independent / Window Watchdog	independent / window watchdog timer	12
OTG	On-The-Go	USB with host and device roles (F4)	20
PWM	Pulse-Width Modulation	pulse-width modulation	13
QSPI	Quad SPI	four-wire SPI for flash memory	41
RTC	Real-Time Clock	real-time clock	12
SDIO	Secure Digital I/O	SD card interface	41
SPI	Serial Peripheral Interface	serial interface, full duplex	18
TIM	Timer	timer	13
UART / USART	(Universal Synchronous) Asynchronous Receiver-Transmitter	serial port	16
USB	Universal Serial Bus	USB	20

F.4 Registers and bits: typical suffixes

Suffix	Meaning	Example
EN	enable	`RCC_APB2ENR_IOPAEN`
RST	reset the block	`RCC_APB2RSTR_USART1RST`
IE	interrupt enable	`USART_CR1_RXNEIE`
IF / F	interrupt flag / flag	`TIM_SR_UIF`, `USART_SR_TXE`
CR	control register	`SPI_CR1`
SR	status register	`ADC_SR`
DR	data register	`USART_DR`
BRR	baud rate / bit reset: baud rate divider / bit clear	`USART_BRR`, `GPIO_BRR`
BSRR	bit set/reset register	`GPIO_BSRR`
ODR / IDR	output / input data register	`GPIO_ODR`
ARR / PSC / CCR	auto-reload / prescaler / capture-compare	timers
CNT	counter	`TIM_CNT`
NDTR	number of data to transfer: the DMA counter	`DMA_CNDTR`
PR	pending register: pending flags	`EXTI_PR`
SWS / SW	system clock switch status / switch	`RCC_CFGR`
RDY	ready	`RCC_CR_HSERDY`
ON	turn the oscillator on	`RCC_CR_HSEON`

F.5 Memory, build, debugging

Abbreviation	Expansion	In plain words	§
BOM	Bill of Materials	list of components	2
BSS	Block Started by Symbol	region of uninitialized data	11
DFP	Device Family Pack	family support pack in Keil	4
ELF / AXF	Executable and Linkable Format	format of the built firmware	4, 11
HAL	Hardware Abstraction Layer	ST abstraction library	5, C
LL	Low-Layer	thin ST library on top of registers	5
MSb / LSb	Most / Least Significant bit	highest / lowest bit	3
OCR	Optical Character Recognition	text recognition	—
RO / RW / ZI	Read-Only / Read-Write / Zero-Initialised	regions of the linker memory map	11
RTOS	Real-Time Operating System	real-time operating system	23
SCVD	System/Component Viewer Description	description of kernel objects for the Keil debugger	35
TCB	Task Control Block	task control block	23, 26

F.6 Network and files

Abbreviation	Expansion	In plain words	§
AT	Attention	prefix of commands to modems and modules	37
FAT / exFAT	File Allocation Table	card file system	42
LFN	Long File Name	long file names	42
MAC / PHY	Media Access Control / Physical layer	Ethernet data link / physical layer	37
MQTT	Message Queuing Telemetry Transport	publish-subscribe protocol	37
QoS	Quality of Service	level of delivery guarantee	37
RMII	Reduced Media-Independent Interface	9-wire MAC–PHY interface	37
TCP / IP	Transmission Control Protocol / Internet Protocol	the Internet stack	37
TLS	Transport Layer Security	encryption on top of TCP	37

_{Expansions follow the reference manuals of the F1 and F4 families
and the Cortex‑M core documentation; the section references are checked by
_tools/check_refs.py.}

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