STM32H743 · уровень справочник · 127 мин чтения

Приложение A7. Карты регистров STM32H7

Серия STM32H7: Cortex-M7 до 480 МГц — самая быстрая серия: кэши, три домена питания. Регистры и биты основных блоков — из заголовка STM32H743, тем же генератором, что карты F1 и F4: смещения — по структурам *_TypeDef, назначение регистра и описание бита — из комментариев заголовка. Блоки, которых в серии нет, опущены. Разделы справочника написаны для F103 и F407; имена регистров и битов у серий в основном те же — карта помогает перенести код и увидеть, что устроено иначе.

Как читать: смещение — от базового адреса блока; 31:16 — поле битов с 16 по 31; одно число — отдельный бит. Цифра в скобках у заголовка блока — раздел, где блок разобран.

Периферия STM32H743 по шинам: базы шин и смещения блоков приложения, как в окне отладчика

RCC — Тактирование (раздел 6)

Регистр	Смещение	Бит	Назначение
`CR`	`0x00`	32	RCC clock control register
`RCC_CR_HSION`		0	Internal High Speed clock enable
`RCC_CR_HSIKERON`		1	Internal High Speed clock enable for some IPs Kernel
`RCC_CR_HSIRDY`		2	Internal High Speed clock ready flag
`RCC_CR_HSIDIV`		3:4	Internal High Speed clock divider selection
`RCC_CR_HSIDIVF`		5	HSI Divider flag
`RCC_CR_CSION`		7	The Internal RC 4MHz oscillator clock enable
`RCC_CR_CSIRDY`		8	The Internal RC 4MHz oscillator clock ready
`RCC_CR_CSIKERON`		9	Internal RC 4MHz oscillator clock enable for some IPs Kernel
`RCC_CR_HSI48ON`		12	HSI48 clock enable clock enable
`RCC_CR_HSI48RDY`		13	HSI48 clock ready
`RCC_CR_D1CKRDY`		14	D1 domain clocks ready flag
`RCC_CR_D2CKRDY`		15	D2 domain clocks ready flag
`RCC_CR_HSEON`		16	External High Speed clock enable
`RCC_CR_HSERDY`		17	External High Speed clock ready
`RCC_CR_HSEBYP`		18	External High Speed clock Bypass
`RCC_CR_CSSHSEON`		19	HSE Clock security System enable
`RCC_CR_PLL1ON`		24	System PLL1 clock enable
`RCC_CR_PLLON`		24	System PLL clock enable
`RCC_CR_PLL1RDY`		25	System PLL1 clock ready
`RCC_CR_PLLRDY`		25	System PLL clock ready
`RCC_CR_PLL2ON`		26	System PLL2 clock enable
`RCC_CR_PLL2RDY`		27	System PLL2 clock ready
`RCC_CR_PLL3ON`		28	System PLL3 clock enable
`RCC_CR_PLL3RDY`		29	System PLL3 clock ready
`HSICFGR`	`0x04`	32	HSI Clock Calibration Register
`RCC_HSICFGR_HSICAL`		0:11	HSICAL[11:0] bits
`RCC_HSICFGR_HSITRIM`		24:30	HSITRIM[6:0] bits
`CRRCR`	`0x08`	32	Clock Recovery RC Register
`RCC_CRRCR_HSI48CAL`		0:9	HSI48CAL[9:0] bits
`CSICFGR`	`0x0C`	32	CSI Clock Calibration Register
`RCC_CSICFGR_CSICAL`		0:7	CSICAL[7:0] bits
`RCC_CSICFGR_CSITRIM`		24:29	CSITRIM[5:0] bits
`CFGR`	`0x10`	32	RCC clock configuration register
`RCC_CFGR_SW`		0:2	SW[2:0] bits (System clock Switch)
`RCC_CFGR_SWS`		3:5	SWS[2:0] bits (System Clock Switch Status)
`RCC_CFGR_STOPWUCK`		6	Wake Up from stop and CSS backup clock selection
`RCC_CFGR_STOPKERWUCK`		7	Kernel Clock Selection after a Wake Up from STOP
`D1CFGR`	`0x18`	32	RCC Domain 1 configuration register
`RCC_D1CFGR_HPRE`		0:3	HPRE[3:0] bits (AHB3 prescaler)
`RCC_D1CFGR_HPRE_DIV4`		0:3	AHB3 Clock divided by 4
`RCC_D1CFGR_HPRE_DIV16`		0:3	AHB3 Clock divided by 16
`RCC_D1CFGR_HPRE_DIV128`		0:3	AHB3 Clock divided by 128
`RCC_D1CFGR_HPRE_DIV512`		0:3	AHB3 Clock divided by 512
`RCC_D1CFGR_HPRE_DIV8`		1:3	AHB3 Clock divided by 8
`RCC_D1CFGR_HPRE_DIV256`		1:3	AHB3 Clock divided by 256
`RCC_D1CFGR_HPRE_DIV64`		2:3	AHB3 Clock divided by 64
`RCC_D1CFGR_HPRE_DIV2`		3	AHB3 Clock divided by 2
`RCC_D1CFGR_D1PPRE`		4:6	D1PRE[2:0] bits (APB3 prescaler)
`RCC_D1CFGR_D1PPRE_DIV4`		4:6	APB3 clock divided by 4
`RCC_D1CFGR_D1PPRE_DIV16`		4:6	APB3 clock divided by 16
`RCC_D1CFGR_D1PPRE_DIV8`		5:6	APB3 clock divided by 8
`RCC_D1CFGR_D1PPRE_DIV2`		6	APB3 clock divided by 2
`RCC_D1CFGR_D1CPRE`		8:11	D1CPRE[2:0] bits (Domain 1 Core prescaler)
`RCC_D1CFGR_D1CPRE_DIV4`		8:11	Domain 1 Core clock divided by 4
`RCC_D1CFGR_D1CPRE_DIV16`		8:11	Domain 1 Core clock divided by 16
`RCC_D1CFGR_D1CPRE_DIV128`		8:11	Domain 1 Core clock divided by 128
`RCC_D1CFGR_D1CPRE_DIV512`		8:11	Domain 1 Core clock divided by 512
`RCC_D1CFGR_D1CPRE_DIV8`		9:11	Domain 1 Core clock divided by 8
`RCC_D1CFGR_D1CPRE_DIV256`		9:11	Domain 1 Core clock divided by 256
`RCC_D1CFGR_D1CPRE_DIV64`		10:11	Domain 1 Core clock divided by 64
`RCC_D1CFGR_D1CPRE_DIV2`		11	Domain 1 Core clock divided by 2
`D2CFGR`	`0x1C`	32	RCC Domain 2 configuration register
`RCC_D2CFGR_D2PPRE1`		4:6	D1PPRE1[2:0] bits (APB1 prescaler)
`RCC_D2CFGR_D2PPRE1_DIV4`		4:6	APB1 clock divided by 4
`RCC_D2CFGR_D2PPRE1_DIV16`		4:6	APB1 clock divided by 16
`RCC_D2CFGR_D2PPRE1_DIV8`		5:6	APB1 clock divided by 8
`RCC_D2CFGR_D2PPRE1_DIV2`		6	APB1 clock divided by 2
`RCC_D2CFGR_D2PPRE2`		8:10	D2PPRE2[2:0] bits (APB2 prescaler)
`RCC_D2CFGR_D2PPRE2_DIV4`		8:10	APB2 clock divided by 4
`RCC_D2CFGR_D2PPRE2_DIV16`		8:10	APB2 clock divided by 16
`RCC_D2CFGR_D2PPRE2_DIV8`		9:10	APB2 clock divided by 8
`RCC_D2CFGR_D2PPRE2_DIV2`		10	APB2 clock divided by 2
`D3CFGR`	`0x20`	32	RCC Domain 3 configuration register
`RCC_D3CFGR_D3PPRE`		4:6	D3PPRE1[2:0] bits (APB4 prescaler)
`RCC_D3CFGR_D3PPRE_DIV4`		4:6	APB4 clock divided by 4
`RCC_D3CFGR_D3PPRE_DIV16`		4:6	APB4 clock divided by 16
`RCC_D3CFGR_D3PPRE_DIV8`		5:6	APB4 clock divided by 8
`RCC_D3CFGR_D3PPRE_DIV2`		6	APB4 clock divided by 2
`PLLCKSELR`	`0x28`	32	RCC PLLs Clock Source Selection Register
`RCC_PLLCKSELR_PLLSRC`		0:1
`RCC_PLLCKSELR_PLLSRC_CSI`		0	CSI source clock selected
`RCC_PLLCKSELR_PLLSRC_NONE`		0:1	No source clock selected
`RCC_PLLCKSELR_PLLSRC_HSE`		1	HSE source clock selected
`RCC_PLLCKSELR_DIVM1`		4:9
`RCC_PLLCKSELR_DIVM2`		12:17
`RCC_PLLCKSELR_DIVM3`		20:25
`PLLCFGR`	`0x2C`	32	RCC PLLs Configuration Register
`RCC_PLLCFGR_PLL1FRACEN`		0
`RCC_PLLCFGR_PLL1VCOSEL`		1
`RCC_PLLCFGR_PLL1RGE`		2:3
`RCC_PLLCFGR_PLL2FRACEN`		4
`RCC_PLLCFGR_PLL2VCOSEL`		5
`RCC_PLLCFGR_PLL2RGE`		6:7
`RCC_PLLCFGR_PLL3FRACEN`		8
`RCC_PLLCFGR_PLL3VCOSEL`		9
`RCC_PLLCFGR_PLL3RGE`		10:11
`RCC_PLLCFGR_DIVP1EN`		16
`RCC_PLLCFGR_DIVQ1EN`		17
`RCC_PLLCFGR_DIVR1EN`		18
`RCC_PLLCFGR_DIVP2EN`		19
`RCC_PLLCFGR_DIVQ2EN`		20
`RCC_PLLCFGR_DIVR2EN`		21
`RCC_PLLCFGR_DIVP3EN`		22
`RCC_PLLCFGR_DIVQ3EN`		23
`RCC_PLLCFGR_DIVR3EN`		24
`PLL1DIVR`	`0x30`	32	RCC PLL1 Dividers Configuration Register
`RCC_PLL1DIVR_N1`		0:8
`RCC_PLL1DIVR_P1`		9:15
`RCC_PLL1DIVR_Q1`		16:22
`RCC_PLL1DIVR_R1`		24:30
`PLL1FRACR`	`0x34`	32	RCC PLL1 Fractional Divider Configuration Register
`RCC_PLL1FRACR_FRACN1`		3:15
`PLL2DIVR`	`0x38`	32	RCC PLL2 Dividers Configuration Register
`RCC_PLL2DIVR_N2`		0:8
`RCC_PLL2DIVR_P2`		9:15
`RCC_PLL2DIVR_Q2`		16:22
`RCC_PLL2DIVR_R2`		24:30
`PLL2FRACR`	`0x3C`	32	RCC PLL2 Fractional Divider Configuration Register
`RCC_PLL2FRACR_FRACN2`		3:15
`PLL3DIVR`	`0x40`	32	RCC PLL3 Dividers Configuration Register
`RCC_PLL3DIVR_N3`		0:8
`RCC_PLL3DIVR_P3`		9:15
`RCC_PLL3DIVR_Q3`		16:22
`RCC_PLL3DIVR_R3`		24:30
`PLL3FRACR`	`0x44`	32	RCC PLL3 Fractional Divider Configuration Register
`RCC_PLL3FRACR_FRACN3`		3:15
`D1CCIPR`	`0x4C`	32	RCC Domain 1 Kernel Clock Configuration Register
`RCC_D1CCIPR_FMCSEL`		0:1
`RCC_D1CCIPR_QSPISEL`		4:5
`RCC_D1CCIPR_SDMMCSEL`		16
`RCC_D1CCIPR_CKPERSEL`		28:29
`D2CCIP1R`	`0x50`	32	RCC Domain 2 Kernel Clock Configuration Register
`RCC_D2CCIP1R_SAI1SEL`		0:2
`RCC_D2CCIP1R_SAI23SEL`		6:8
`RCC_D2CCIP1R_SPI123SEL`		12:14
`RCC_D2CCIP1R_SPI45SEL`		16:18
`RCC_D2CCIP1R_SPDIFSEL`		20:21
`RCC_D2CCIP1R_DFSDM1SEL`		24
`RCC_D2CCIP1R_FDCANSEL`		28:29
`RCC_D2CCIP1R_SWPSEL`		31
`D2CCIP2R`	`0x54`	32	RCC Domain 2 Kernel Clock Configuration Register
`RCC_D2CCIP2R_USART28SEL`		0:2
`RCC_D2CCIP2R_USART16SEL`		3:5
`RCC_D2CCIP2R_RNGSEL`		8:9
`RCC_D2CCIP2R_I2C123SEL`		12:13
`RCC_D2CCIP2R_USBSEL`		20:21
`RCC_D2CCIP2R_CECSEL`		22:23
`RCC_D2CCIP2R_LPTIM1SEL`		28:30
`D3CCIPR`	`0x58`	32	RCC Domain 3 Kernel Clock Configuration Register
`RCC_D3CCIPR_LPUART1SEL`		0:2
`RCC_D3CCIPR_I2C4SEL`		8:9
`RCC_D3CCIPR_LPTIM2SEL`		10:12
`RCC_D3CCIPR_LPTIM345SEL`		13:15
`RCC_D3CCIPR_ADCSEL`		16:17
`RCC_D3CCIPR_SAI4ASEL`		21:23
`RCC_D3CCIPR_SAI4BSEL`		24:26
`RCC_D3CCIPR_SPI6SEL`		28:30
`CIER`	`0x60`	32	RCC Clock Source Interrupt Enable Register
`RCC_CIER_LSIRDYIE`		0
`RCC_CIER_LSERDYIE`		1
`RCC_CIER_HSIRDYIE`		2
`RCC_CIER_HSERDYIE`		3
`RCC_CIER_CSIRDYIE`		4
`RCC_CIER_HSI48RDYIE`		5
`RCC_CIER_PLL1RDYIE`		6
`RCC_CIER_PLL2RDYIE`		7
`RCC_CIER_PLL3RDYIE`		8
`RCC_CIER_LSECSSIE`		9
`CIFR`	`0x64`	32	RCC Clock Source Interrupt Flag Register
`RCC_CIFR_LSIRDYF`		0
`RCC_CIFR_LSERDYF`		1
`RCC_CIFR_HSIRDYF`		2
`RCC_CIFR_HSERDYF`		3
`RCC_CIFR_CSIRDYF`		4
`RCC_CIFR_HSI48RDYF`		5
`RCC_CIFR_PLLRDYF`		6
`RCC_CIFR_PLL2RDYF`		7
`RCC_CIFR_PLL3RDYF`		8
`RCC_CIFR_LSECSSF`		9
`RCC_CIFR_HSECSSF`		10
`CICR`	`0x68`	32	RCC Clock Source Interrupt Clear Register
`RCC_CICR_LSIRDYC`		0
`RCC_CICR_LSERDYC`		1
`RCC_CICR_HSIRDYC`		2
`RCC_CICR_HSERDYC`		3
`RCC_CICR_CSIRDYC`		4
`RCC_CICR_HSI48RDYC`		5
`RCC_CICR_PLLRDYC`		6
`RCC_CICR_PLL2RDYC`		7
`RCC_CICR_PLL3RDYC`		8
`RCC_CICR_LSECSSC`		9
`RCC_CICR_HSECSSC`		10
`BDCR`	`0x70`	32	RCC Vswitch Backup Domain Control Register
`RCC_BDCR_LSEON`		0
`RCC_BDCR_LSERDY`		1
`RCC_BDCR_LSEBYP`		2
`RCC_BDCR_LSEDRV`		3:4
`RCC_BDCR_LSECSSON`		5
`RCC_BDCR_LSECSSD`		6
`RCC_BDCR_RTCSEL`		8:9
`RCC_BDCR_RTCEN`		15
`RCC_BDCR_BDRST`		16
`CSR`	`0x74`	32	RCC clock control & status register
`RCC_CSR_LSION`		0
`RCC_CSR_LSIRDY`		1
`AHB3RSTR`	`0x7C`	32	RCC AHB3 peripheral reset register
`RCC_AHB3RSTR_MDMARST`		0
`RCC_AHB3RSTR_DMA2DRST`		4
`RCC_AHB3RSTR_JPGDECRST`		5
`RCC_AHB3RSTR_FMCRST`		12
`RCC_AHB3RSTR_QSPIRST`		14
`RCC_AHB3RSTR_SDMMC1RST`		16
`AHB1RSTR`	`0x80`	32	RCC AHB1 peripheral reset register
`RCC_AHB1RSTR_DMA1RST`		0
`RCC_AHB1RSTR_DMA2RST`		1
`RCC_AHB1RSTR_ADC12RST`		5
`RCC_AHB1RSTR_ETH1MACRST`		15
`RCC_AHB1RSTR_USB1OTGHSRST`		25
`RCC_AHB1RSTR_USB2OTGFSRST`		27
`AHB2RSTR`	`0x84`	32	RCC AHB2 peripheral reset register
`RCC_AHB2RSTR_DCMIRST`		0
`RCC_AHB2RSTR_RNGRST`		6
`RCC_AHB2RSTR_SDMMC2RST`		9
`AHB4RSTR`	`0x88`	32	RCC AHB4 peripheral reset register
`RCC_AHB4RSTR_GPIOARST`		0
`RCC_AHB4RSTR_GPIOBRST`		1
`RCC_AHB4RSTR_GPIOCRST`		2
`RCC_AHB4RSTR_GPIODRST`		3
`RCC_AHB4RSTR_GPIOERST`		4
`RCC_AHB4RSTR_GPIOFRST`		5
`RCC_AHB4RSTR_GPIOGRST`		6
`RCC_AHB4RSTR_GPIOHRST`		7
`RCC_AHB4RSTR_GPIOIRST`		8
`RCC_AHB4RSTR_GPIOJRST`		9
`RCC_AHB4RSTR_GPIOKRST`		10
`RCC_AHB4RSTR_CRCRST`		19
`RCC_AHB4RSTR_BDMARST`		21
`RCC_AHB4RSTR_ADC3RST`		24
`RCC_AHB4RSTR_HSEMRST`		25
`APB3RSTR`	`0x8C`	32	RCC APB3 peripheral reset register
`RCC_APB3RSTR_LTDCRST`		3
`APB1LRSTR`	`0x90`	32	RCC APB1 peripheral reset Low Word register
`RCC_APB1LRSTR_TIM2RST`		0
`RCC_APB1LRSTR_TIM3RST`		1
`RCC_APB1LRSTR_TIM4RST`		2
`RCC_APB1LRSTR_TIM5RST`		3
`RCC_APB1LRSTR_TIM6RST`		4
`RCC_APB1LRSTR_TIM7RST`		5
`RCC_APB1LRSTR_TIM12RST`		6
`RCC_APB1LRSTR_TIM13RST`		7
`RCC_APB1LRSTR_TIM14RST`		8
`RCC_APB1LRSTR_LPTIM1RST`		9
`RCC_APB1LRSTR_SPI2RST`		14
`RCC_APB1LRSTR_SPI3RST`		15
`RCC_APB1LRSTR_SPDIFRXRST`		16
`RCC_APB1LRSTR_USART2RST`		17
`RCC_APB1LRSTR_USART3RST`		18
`RCC_APB1LRSTR_UART4RST`		19
`RCC_APB1LRSTR_UART5RST`		20
`RCC_APB1LRSTR_I2C1RST`		21
`RCC_APB1LRSTR_I2C2RST`		22
`RCC_APB1LRSTR_I2C3RST`		23
`RCC_APB1LRSTR_CECRST`		27
`RCC_APB1LRSTR_DAC12RST`		29
`RCC_APB1LRSTR_UART7RST`		30
`RCC_APB1LRSTR_UART8RST`		31
`APB1HRSTR`	`0x94`	32	RCC APB1 peripheral reset High Word register
`RCC_APB1HRSTR_CRSRST`		1
`RCC_APB1HRSTR_SWPMIRST`		2
`RCC_APB1HRSTR_OPAMPRST`		4
`RCC_APB1HRSTR_MDIOSRST`		5
`RCC_APB1HRSTR_FDCANRST`		8
`APB2RSTR`	`0x98`	32	RCC APB2 peripheral reset register
`RCC_APB2RSTR_TIM1RST`		0
`RCC_APB2RSTR_TIM8RST`		1
`RCC_APB2RSTR_USART1RST`		4
`RCC_APB2RSTR_USART6RST`		5
`RCC_APB2RSTR_SPI1RST`		12
`RCC_APB2RSTR_SPI4RST`		13
`RCC_APB2RSTR_TIM15RST`		16
`RCC_APB2RSTR_TIM16RST`		17
`RCC_APB2RSTR_TIM17RST`		18
`RCC_APB2RSTR_SPI5RST`		20
`RCC_APB2RSTR_SAI1RST`		22
`RCC_APB2RSTR_SAI2RST`		23
`RCC_APB2RSTR_SAI3RST`		24
`RCC_APB2RSTR_DFSDM1RST`		28
`RCC_APB2RSTR_HRTIMRST`		29
`APB4RSTR`	`0x9C`	32	RCC APB4 peripheral reset register
`RCC_APB4RSTR_SYSCFGRST`		1
`RCC_APB4RSTR_LPUART1RST`		3
`RCC_APB4RSTR_SPI6RST`		5
`RCC_APB4RSTR_I2C4RST`		7
`RCC_APB4RSTR_LPTIM2RST`		9
`RCC_APB4RSTR_LPTIM3RST`		10
`RCC_APB4RSTR_LPTIM4RST`		11
`RCC_APB4RSTR_LPTIM5RST`		12
`RCC_APB4RSTR_COMP12RST`		14
`RCC_APB4RSTR_VREFRST`		15
`RCC_APB4RSTR_SAI4RST`		21
`GCR`	`0xA0`	32	RCC RCC Global Control Register
`RCC_GCR_WW1RSC`		0
`D3AMR`	`0xA8`	32	RCC Domain 3 Autonomous Mode Register
`RCC_D3AMR_BDMAAMEN`		0
`RCC_D3AMR_LPUART1AMEN`		3
`RCC_D3AMR_SPI6AMEN`		5
`RCC_D3AMR_I2C4AMEN`		7
`RCC_D3AMR_LPTIM2AMEN`		9
`RCC_D3AMR_LPTIM3AMEN`		10
`RCC_D3AMR_LPTIM4AMEN`		11
`RCC_D3AMR_LPTIM5AMEN`		12
`RCC_D3AMR_COMP12AMEN`		14
`RCC_D3AMR_VREFAMEN`		15
`RCC_D3AMR_RTCAMEN`		16
`RCC_D3AMR_CRCAMEN`		19
`RCC_D3AMR_SAI4AMEN`		21
`RCC_D3AMR_ADC3AMEN`		24
`RCC_D3AMR_BKPRAMAMEN`		28
`RCC_D3AMR_SRAM4AMEN`		29
`RSR`	`0xD0`	32	RCC Reset status register
`RCC_RSR_RMVF`		16
`RCC_RSR_CPURSTF`		17
`RCC_RSR_D1RSTF`		19
`RCC_RSR_D2RSTF`		20
`RCC_RSR_BORRSTF`		21
`RCC_RSR_PINRSTF`		22
`RCC_RSR_PORRSTF`		23
`RCC_RSR_SFTRSTF`		24
`RCC_RSR_IWDG1RSTF`		26
`RCC_RSR_WWDG1RSTF`		28
`RCC_RSR_LPWRRSTF`		30
`AHB3ENR`	`0xD4`	32	RCC AHB3 peripheral clock register
`RCC_AHB3ENR_MDMAEN`		0
`RCC_AHB3ENR_DMA2DEN`		4
`RCC_AHB3ENR_JPGDECEN`		5
`RCC_AHB3ENR_FMCEN`		12
`RCC_AHB3ENR_QSPIEN`		14
`RCC_AHB3ENR_SDMMC1EN`		16
`AHB1ENR`	`0xD8`	32	RCC AHB1 peripheral clock register
`RCC_AHB1ENR_DMA1EN`		0
`RCC_AHB1ENR_DMA2EN`		1
`RCC_AHB1ENR_ADC12EN`		5
`RCC_AHB1ENR_ETH1MACEN`		15
`RCC_AHB1ENR_ETH1TXEN`		16
`RCC_AHB1ENR_ETH1RXEN`		17
`RCC_AHB1ENR_USB1OTGHSEN`		25
`RCC_AHB1ENR_USB1OTGHSULPIEN`		26
`RCC_AHB1ENR_USB2OTGFSEN`		27
`RCC_AHB1ENR_USB2OTGFSULPIEN`		28
`AHB2ENR`	`0xDC`	32	RCC AHB2 peripheral clock register
`RCC_AHB2ENR_DCMIEN`		0
`RCC_AHB2ENR_RNGEN`		6
`RCC_AHB2ENR_SDMMC2EN`		9
`RCC_AHB2ENR_SRAM1EN`		29
`RCC_AHB2ENR_SRAM2EN`		30
`RCC_AHB2ENR_SRAM3EN`		31
`AHB4ENR`	`0xE0`	32	RCC AHB4 peripheral clock register
`RCC_AHB4ENR_GPIOAEN`		0
`RCC_AHB4ENR_GPIOBEN`		1
`RCC_AHB4ENR_GPIOCEN`		2
`RCC_AHB4ENR_GPIODEN`		3
`RCC_AHB4ENR_GPIOEEN`		4
`RCC_AHB4ENR_GPIOFEN`		5
`RCC_AHB4ENR_GPIOGEN`		6
`RCC_AHB4ENR_GPIOHEN`		7
`RCC_AHB4ENR_GPIOIEN`		8
`RCC_AHB4ENR_GPIOJEN`		9
`RCC_AHB4ENR_GPIOKEN`		10
`RCC_AHB4ENR_CRCEN`		19
`RCC_AHB4ENR_BDMAEN`		21
`RCC_AHB4ENR_ADC3EN`		24
`RCC_AHB4ENR_HSEMEN`		25
`RCC_AHB4ENR_BKPRAMEN`		28
`APB3ENR`	`0xE4`	32	RCC APB3 peripheral clock register
`RCC_APB3ENR_LTDCEN`		3
`RCC_APB3ENR_WWDG1EN`		6
`APB1LENR`	`0xE8`	32	RCC APB1 peripheral clock Low Word register
`RCC_APB1LENR_TIM2EN`		0
`RCC_APB1LENR_TIM3EN`		1
`RCC_APB1LENR_TIM4EN`		2
`RCC_APB1LENR_TIM5EN`		3
`RCC_APB1LENR_TIM6EN`		4
`RCC_APB1LENR_TIM7EN`		5
`RCC_APB1LENR_TIM12EN`		6
`RCC_APB1LENR_TIM13EN`		7
`RCC_APB1LENR_TIM14EN`		8
`RCC_APB1LENR_LPTIM1EN`		9
`RCC_APB1LENR_SPI2EN`		14
`RCC_APB1LENR_SPI3EN`		15
`RCC_APB1LENR_SPDIFRXEN`		16
`RCC_APB1LENR_USART2EN`		17
`RCC_APB1LENR_USART3EN`		18
`RCC_APB1LENR_UART4EN`		19
`RCC_APB1LENR_UART5EN`		20
`RCC_APB1LENR_I2C1EN`		21
`RCC_APB1LENR_I2C2EN`		22
`RCC_APB1LENR_I2C3EN`		23
`RCC_APB1LENR_CECEN`		27
`RCC_APB1LENR_DAC12EN`		29
`RCC_APB1LENR_UART7EN`		30
`RCC_APB1LENR_UART8EN`		31
`APB1HENR`	`0xEC`	32	RCC APB1 peripheral clock High Word register
`RCC_APB1HENR_CRSEN`		1
`RCC_APB1HENR_SWPMIEN`		2
`RCC_APB1HENR_OPAMPEN`		4
`RCC_APB1HENR_MDIOSEN`		5
`RCC_APB1HENR_FDCANEN`		8
`APB2ENR`	`0xF0`	32	RCC APB2 peripheral clock register
`RCC_APB2ENR_TIM1EN`		0
`RCC_APB2ENR_TIM8EN`		1
`RCC_APB2ENR_USART1EN`		4
`RCC_APB2ENR_USART6EN`		5
`RCC_APB2ENR_SPI1EN`		12
`RCC_APB2ENR_SPI4EN`		13
`RCC_APB2ENR_TIM15EN`		16
`RCC_APB2ENR_TIM16EN`		17
`RCC_APB2ENR_TIM17EN`		18
`RCC_APB2ENR_SPI5EN`		20
`RCC_APB2ENR_SAI1EN`		22
`RCC_APB2ENR_SAI2EN`		23
`RCC_APB2ENR_SAI3EN`		24
`RCC_APB2ENR_DFSDM1EN`		28
`RCC_APB2ENR_HRTIMEN`		29
`APB4ENR`	`0xF4`	32	RCC APB4 peripheral clock register
`RCC_APB4ENR_SYSCFGEN`		1
`RCC_APB4ENR_LPUART1EN`		3
`RCC_APB4ENR_SPI6EN`		5
`RCC_APB4ENR_I2C4EN`		7
`RCC_APB4ENR_LPTIM2EN`		9
`RCC_APB4ENR_LPTIM3EN`		10
`RCC_APB4ENR_LPTIM4EN`		11
`RCC_APB4ENR_LPTIM5EN`		12
`RCC_APB4ENR_COMP12EN`		14
`RCC_APB4ENR_VREFEN`		15
`RCC_APB4ENR_RTCAPBEN`		16
`RCC_APB4ENR_SAI4EN`		21
`AHB3LPENR`	`0xFC`	32	RCC AHB3 peripheral sleep clock register
`RCC_AHB3LPENR_MDMALPEN`		0
`RCC_AHB3LPENR_DMA2DLPEN`		4
`RCC_AHB3LPENR_JPGDECLPEN`		5
`RCC_AHB3LPENR_FLASHLPEN`		8
`RCC_AHB3LPENR_FMCLPEN`		12
`RCC_AHB3LPENR_QSPILPEN`		14
`RCC_AHB3LPENR_SDMMC1LPEN`		16
`RCC_AHB3LPENR_DTCM1LPEN`		28
`RCC_AHB3LPENR_DTCM2LPEN`		29
`RCC_AHB3LPENR_ITCMLPEN`		30
`RCC_AHB3LPENR_AXISRAMLPEN`		31
`AHB1LPENR`	`0x100`	32	RCC AHB1 peripheral sleep clock register
`RCC_AHB1LPENR_DMA1LPEN`		0
`RCC_AHB1LPENR_DMA2LPEN`		1
`RCC_AHB1LPENR_ADC12LPEN`		5
`RCC_AHB1LPENR_ETH1MACLPEN`		15
`RCC_AHB1LPENR_ETH1TXLPEN`		16
`RCC_AHB1LPENR_ETH1RXLPEN`		17
`RCC_AHB1LPENR_USB1OTGHSLPEN`		25
`RCC_AHB1LPENR_USB1OTGHSULPILPEN`		26
`RCC_AHB1LPENR_USB2OTGFSLPEN`		27
`RCC_AHB1LPENR_USB2OTGFSULPILPEN`		28
`AHB2LPENR`	`0x104`	32	RCC AHB2 peripheral sleep clock register
`RCC_AHB2LPENR_DCMILPEN`		0
`RCC_AHB2LPENR_RNGLPEN`		6
`RCC_AHB2LPENR_SDMMC2LPEN`		9
`RCC_AHB2LPENR_SRAM1LPEN`		29
`RCC_AHB2LPENR_SRAM2LPEN`		30
`RCC_AHB2LPENR_SRAM3LPEN`		31
`AHB4LPENR`	`0x108`	32	RCC AHB4 peripheral sleep clock register
`RCC_AHB4LPENR_GPIOALPEN`		0
`RCC_AHB4LPENR_GPIOBLPEN`		1
`RCC_AHB4LPENR_GPIOCLPEN`		2
`RCC_AHB4LPENR_GPIODLPEN`		3
`RCC_AHB4LPENR_GPIOELPEN`		4
`RCC_AHB4LPENR_GPIOFLPEN`		5
`RCC_AHB4LPENR_GPIOGLPEN`		6
`RCC_AHB4LPENR_GPIOHLPEN`		7
`RCC_AHB4LPENR_GPIOILPEN`		8
`RCC_AHB4LPENR_GPIOJLPEN`		9
`RCC_AHB4LPENR_GPIOKLPEN`		10
`RCC_AHB4LPENR_CRCLPEN`		19
`RCC_AHB4LPENR_BDMALPEN`		21
`RCC_AHB4LPENR_ADC3LPEN`		24
`RCC_AHB4LPENR_BKPRAMLPEN`		28
`RCC_AHB4LPENR_SRAM4LPEN`		29
`APB3LPENR`	`0x10C`	32	RCC APB3 peripheral sleep clock register
`RCC_APB3LPENR_LTDCLPEN`		3
`RCC_APB3LPENR_WWDG1LPEN`		6
`APB1LLPENR`	`0x110`	32	RCC APB1 peripheral sleep clock Low Word register
`RCC_APB1LLPENR_TIM2LPEN`		0
`RCC_APB1LLPENR_TIM3LPEN`		1
`RCC_APB1LLPENR_TIM4LPEN`		2
`RCC_APB1LLPENR_TIM5LPEN`		3
`RCC_APB1LLPENR_TIM6LPEN`		4
`RCC_APB1LLPENR_TIM7LPEN`		5
`RCC_APB1LLPENR_TIM12LPEN`		6
`RCC_APB1LLPENR_TIM13LPEN`		7
`RCC_APB1LLPENR_TIM14LPEN`		8
`RCC_APB1LLPENR_LPTIM1LPEN`		9
`RCC_APB1LLPENR_SPI2LPEN`		14
`RCC_APB1LLPENR_SPI3LPEN`		15
`RCC_APB1LLPENR_SPDIFRXLPEN`		16
`RCC_APB1LLPENR_USART2LPEN`		17
`RCC_APB1LLPENR_USART3LPEN`		18
`RCC_APB1LLPENR_UART4LPEN`		19
`RCC_APB1LLPENR_UART5LPEN`		20
`RCC_APB1LLPENR_I2C1LPEN`		21
`RCC_APB1LLPENR_I2C2LPEN`		22
`RCC_APB1LLPENR_I2C3LPEN`		23
`RCC_APB1LLPENR_CECLPEN`		27
`RCC_APB1LLPENR_DAC12LPEN`		29
`RCC_APB1LLPENR_UART7LPEN`		30
`RCC_APB1LLPENR_UART8LPEN`		31
`APB1HLPENR`	`0x114`	32	RCC APB1 peripheral sleep clock High Word register
`RCC_APB1HLPENR_CRSLPEN`		1
`RCC_APB1HLPENR_SWPMILPEN`		2
`RCC_APB1HLPENR_OPAMPLPEN`		4
`RCC_APB1HLPENR_MDIOSLPEN`		5
`RCC_APB1HLPENR_FDCANLPEN`		8
`APB2LPENR`	`0x118`	32	RCC APB2 peripheral sleep clock register
`RCC_APB2LPENR_TIM1LPEN`		0
`RCC_APB2LPENR_TIM8LPEN`		1
`RCC_APB2LPENR_USART1LPEN`		4
`RCC_APB2LPENR_USART6LPEN`		5
`RCC_APB2LPENR_SPI1LPEN`		12
`RCC_APB2LPENR_SPI4LPEN`		13
`RCC_APB2LPENR_TIM15LPEN`		16
`RCC_APB2LPENR_TIM16LPEN`		17
`RCC_APB2LPENR_TIM17LPEN`		18
`RCC_APB2LPENR_SPI5LPEN`		20
`RCC_APB2LPENR_SAI1LPEN`		22
`RCC_APB2LPENR_SAI2LPEN`		23
`RCC_APB2LPENR_SAI3LPEN`		24
`RCC_APB2LPENR_DFSDM1LPEN`		28
`RCC_APB2LPENR_HRTIMLPEN`		29
`APB4LPENR`	`0x11C`	32	RCC APB4 peripheral sleep clock register
`RCC_APB4LPENR_SYSCFGLPEN`		1
`RCC_APB4LPENR_LPUART1LPEN`		3
`RCC_APB4LPENR_SPI6LPEN`		5
`RCC_APB4LPENR_I2C4LPEN`		7
`RCC_APB4LPENR_LPTIM2LPEN`		9
`RCC_APB4LPENR_LPTIM3LPEN`		10
`RCC_APB4LPENR_LPTIM4LPEN`		11
`RCC_APB4LPENR_LPTIM5LPEN`		12
`RCC_APB4LPENR_COMP12LPEN`		14
`RCC_APB4LPENR_VREFLPEN`		15
`RCC_APB4LPENR_RTCAPBLPEN`		16
`RCC_APB4LPENR_SAI4LPEN`		21

GPIO — Порты ввода-вывода (раздел 8)

Регистр	Смещение	Бит	Назначение
`MODER`	`0x00`	32	GPIO port mode register
`GPIO_MODER_MODE0`		0:1
`GPIO_MODER_MODE1`		2:3
`GPIO_MODER_MODE2`		4:5
`GPIO_MODER_MODE3`		6:7
`GPIO_MODER_MODE4`		8:9
`GPIO_MODER_MODE5`		10:11
`GPIO_MODER_MODE6`		12:13
`GPIO_MODER_MODE7`		14:15
`GPIO_MODER_MODE8`		16:17
`GPIO_MODER_MODE9`		18:19
`GPIO_MODER_MODE10`		20:21
`GPIO_MODER_MODE11`		22:23
`GPIO_MODER_MODE12`		24:25
`GPIO_MODER_MODE13`		26:27
`GPIO_MODER_MODE14`		28:29
`GPIO_MODER_MODE15`		30:31
`OTYPER`	`0x04`	32	GPIO port output type register
`GPIO_OTYPER_OT0`		0
`GPIO_OTYPER_OT1`		1
`GPIO_OTYPER_OT2`		2
`GPIO_OTYPER_OT3`		3
`GPIO_OTYPER_OT4`		4
`GPIO_OTYPER_OT5`		5
`GPIO_OTYPER_OT6`		6
`GPIO_OTYPER_OT7`		7
`GPIO_OTYPER_OT8`		8
`GPIO_OTYPER_OT9`		9
`GPIO_OTYPER_OT10`		10
`GPIO_OTYPER_OT11`		11
`GPIO_OTYPER_OT12`		12
`GPIO_OTYPER_OT13`		13
`GPIO_OTYPER_OT14`		14
`GPIO_OTYPER_OT15`		15
`OSPEEDR`	`0x08`	32	GPIO port output speed register
`GPIO_OSPEEDR_OSPEED0`		0:1
`GPIO_OSPEEDR_OSPEED1`		2:3
`GPIO_OSPEEDR_OSPEED2`		4:5
`GPIO_OSPEEDR_OSPEED3`		6:7
`GPIO_OSPEEDR_OSPEED4`		8:9
`GPIO_OSPEEDR_OSPEED5`		10:11
`GPIO_OSPEEDR_OSPEED6`		12:13
`GPIO_OSPEEDR_OSPEED7`		14:15
`GPIO_OSPEEDR_OSPEED8`		16:17
`GPIO_OSPEEDR_OSPEED9`		18:19
`GPIO_OSPEEDR_OSPEED10`		20:21
`GPIO_OSPEEDR_OSPEED11`		22:23
`GPIO_OSPEEDR_OSPEED12`		24:25
`GPIO_OSPEEDR_OSPEED13`		26:27
`GPIO_OSPEEDR_OSPEED14`		28:29
`GPIO_OSPEEDR_OSPEED15`		30:31
`PUPDR`	`0x0C`	32	GPIO port pull-up/pull-down register
`GPIO_PUPDR_PUPD0`		0:1
`GPIO_PUPDR_PUPD1`		2:3
`GPIO_PUPDR_PUPD2`		4:5
`GPIO_PUPDR_PUPD3`		6:7
`GPIO_PUPDR_PUPD4`		8:9
`GPIO_PUPDR_PUPD5`		10:11
`GPIO_PUPDR_PUPD6`		12:13
`GPIO_PUPDR_PUPD7`		14:15
`GPIO_PUPDR_PUPD8`		16:17
`GPIO_PUPDR_PUPD9`		18:19
`GPIO_PUPDR_PUPD10`		20:21
`GPIO_PUPDR_PUPD11`		22:23
`GPIO_PUPDR_PUPD12`		24:25
`GPIO_PUPDR_PUPD13`		26:27
`GPIO_PUPDR_PUPD14`		28:29
`GPIO_PUPDR_PUPD15`		30:31
`IDR`	`0x10`	32	GPIO port input data register
`GPIO_IDR_ID0`		0
`GPIO_IDR_ID1`		1
`GPIO_IDR_ID2`		2
`GPIO_IDR_ID3`		3
`GPIO_IDR_ID4`		4
`GPIO_IDR_ID5`		5
`GPIO_IDR_ID6`		6
`GPIO_IDR_ID7`		7
`GPIO_IDR_ID8`		8
`GPIO_IDR_ID9`		9
`GPIO_IDR_ID10`		10
`GPIO_IDR_ID11`		11
`GPIO_IDR_ID12`		12
`GPIO_IDR_ID13`		13
`GPIO_IDR_ID14`		14
`GPIO_IDR_ID15`		15
`ODR`	`0x14`	32	GPIO port output data register
`GPIO_ODR_OD0`		0
`GPIO_ODR_OD1`		1
`GPIO_ODR_OD2`		2
`GPIO_ODR_OD3`		3
`GPIO_ODR_OD4`		4
`GPIO_ODR_OD5`		5
`GPIO_ODR_OD6`		6
`GPIO_ODR_OD7`		7
`GPIO_ODR_OD8`		8
`GPIO_ODR_OD9`		9
`GPIO_ODR_OD10`		10
`GPIO_ODR_OD11`		11
`GPIO_ODR_OD12`		12
`GPIO_ODR_OD13`		13
`GPIO_ODR_OD14`		14
`GPIO_ODR_OD15`		15
`BSRR`	`0x18`	32	GPIO port bit set/reset
`GPIO_BSRR_BS0`		0
`GPIO_BSRR_BS1`		1
`GPIO_BSRR_BS2`		2
`GPIO_BSRR_BS3`		3
`GPIO_BSRR_BS4`		4
`GPIO_BSRR_BS5`		5
`GPIO_BSRR_BS6`		6
`GPIO_BSRR_BS7`		7
`GPIO_BSRR_BS8`		8
`GPIO_BSRR_BS9`		9
`GPIO_BSRR_BS10`		10
`GPIO_BSRR_BS11`		11
`GPIO_BSRR_BS12`		12
`GPIO_BSRR_BS13`		13
`GPIO_BSRR_BS14`		14
`GPIO_BSRR_BS15`		15
`GPIO_BSRR_BR0`		16
`GPIO_BSRR_BR1`		17
`GPIO_BSRR_BR2`		18
`GPIO_BSRR_BR3`		19
`GPIO_BSRR_BR4`		20
`GPIO_BSRR_BR5`		21
`GPIO_BSRR_BR6`		22
`GPIO_BSRR_BR7`		23
`GPIO_BSRR_BR8`		24
`GPIO_BSRR_BR9`		25
`GPIO_BSRR_BR10`		26
`GPIO_BSRR_BR11`		27
`GPIO_BSRR_BR12`		28
`GPIO_BSRR_BR13`		29
`GPIO_BSRR_BR14`		30
`GPIO_BSRR_BR15`		31
`LCKR`	`0x1C`	32	GPIO port configuration lock register
`GPIO_LCKR_LCK0`		0
`GPIO_LCKR_LCK1`		1
`GPIO_LCKR_LCK2`		2
`GPIO_LCKR_LCK3`		3
`GPIO_LCKR_LCK4`		4
`GPIO_LCKR_LCK5`		5
`GPIO_LCKR_LCK6`		6
`GPIO_LCKR_LCK7`		7
`GPIO_LCKR_LCK8`		8
`GPIO_LCKR_LCK9`		9
`GPIO_LCKR_LCK10`		10
`GPIO_LCKR_LCK11`		11
`GPIO_LCKR_LCK12`		12
`GPIO_LCKR_LCK13`		13
`GPIO_LCKR_LCK14`		14
`GPIO_LCKR_LCK15`		15
`GPIO_LCKR_LCKK`		16
`AFR`+2×4	`0x20`	32	GPIO alternate function registers

SYSCFG — Системная конфигурация (раздел 8)

Регистр	Смещение	Бит	Назначение
`PMCR`	`0x04`	32	SYSCFG peripheral mode configuration register
`SYSCFG_PMCR_I2C1_FMP`		0	I2C1 Fast mode plus
`SYSCFG_PMCR_I2C2_FMP`		1	I2C2 Fast mode plus
`SYSCFG_PMCR_I2C3_FMP`		2	I2C3 Fast mode plus
`SYSCFG_PMCR_I2C4_FMP`		3	I2C4 Fast mode plus
`SYSCFG_PMCR_I2C_PB6_FMP`		4	I2C PB6 Fast mode plus
`SYSCFG_PMCR_I2C_PB7_FMP`		5	I2C PB7 Fast mode plus
`SYSCFG_PMCR_I2C_PB8_FMP`		6	I2C PB8 Fast mode plus
`SYSCFG_PMCR_I2C_PB9_FMP`		7	I2C PB9 Fast mode plus
`SYSCFG_PMCR_BOOSTEN`		8	I/O analog switch voltage booster enable
`SYSCFG_PMCR_BOOSTVDDSEL`		9	Analog switch supply source selection : VDD/VDDA
`SYSCFG_PMCR_EPIS_SEL`		21:23	Ethernet PHY Interface Selection
`SYSCFG_PMCR_PA0SO`		24	PA0 Switch Open
`SYSCFG_PMCR_PA1SO`		25	PA1 Switch Open
`SYSCFG_PMCR_PC2SO`		26	PC2 Switch Open
`SYSCFG_PMCR_PC3SO`		27	PC3 Switch Open
`EXTICR`+4×4	`0x08`	32	SYSCFG external interrupt configuration registers
`CFGR`	`0x18`	32	SYSCFG configuration registers
`SYSCFG_CFGR_PVDL`		2	PVD lock enable bit
`SYSCFG_CFGR_FLASHL`		3	FLASH double ECC error lock bit
`SYSCFG_CFGR_CM7L`		6	Cortex-M7 LOCKUP (Hardfault) output enable bit
`SYSCFG_CFGR_BKRAML`		7	Backup SRAM double ECC error lock bit
`SYSCFG_CFGR_SRAM4L`		9	SRAM4 double ECC error lock bit
`SYSCFG_CFGR_SRAM3L`		10	SRAM3 double ECC error lock bit
`SYSCFG_CFGR_SRAM2L`		11	SRAM2 double ECC error lock bit
`SYSCFG_CFGR_SRAM1L`		12	SRAM1 double ECC error lock bit
`SYSCFG_CFGR_DTCML`		13	DTCM double ECC error lock bit
`SYSCFG_CFGR_ITCML`		14	ITCM double ECC error lock bit
`SYSCFG_CFGR_AXISRAML`		15	AXISRAM double ECC error lock bit
`CCCSR`	`0x20`	32	SYSCFG compensation cell control/status register
`SYSCFG_CCCSR_EN`		0	I/O compensation cell enable
`SYSCFG_CCCSR_CS`		1	I/O compensation cell code selection
`SYSCFG_CCCSR_READY`		8	I/O compensation cell ready flag
`SYSCFG_CCCSR_HSLV`		16	High-speed at low-voltage
`CCVR`	`0x24`	32	SYSCFG compensation cell value register
`SYSCFG_CCVR_NCV`		0:3	NMOS compensation value
`SYSCFG_CCVR_PCV`		4:7	PMOS compensation value
`CCCR`	`0x28`	32	SYSCFG compensation cell code register
`SYSCFG_CCCR_NCC`		0:3	NMOS compensation code
`SYSCFG_CCCR_PCC`		4:7	PMOS compensation code
`PWRCR`	`0x2C`	32	PWR control register
`SYSCFG_PWRCR_ODEN`		0	PWR overdrive enable
`PKGR`	`0x124`	32	SYSCFG package register
`SYSCFG_PKGR_PKG`		0:3	Package type
`UR0`	`0x300`	32	SYSCFG user register 0
`SYSCFG_UR0_BKS`		0	Bank Swap
`SYSCFG_UR0_RDP`		16:23	Readout protection
`UR1`	`0x304`	32	SYSCFG user register 1
`UR2`	`0x308`	32	SYSCFG user register 2
`SYSCFG_UR2_BORH`		0:1	Brown Out Reset High level
`SYSCFG_UR2_BOOT_ADD0`		16:31	Core Boot Address 0
`UR3`	`0x30C`	32	SYSCFG user register 3
`SYSCFG_UR3_BOOT_ADD1`		0:15	Core Boot Address 1
`UR4`	`0x310`	32	SYSCFG user register 4
`SYSCFG_UR4_MEPAD_BANK1`		16	Mass Erase Protected Area Disabled for bank 1
`UR5`	`0x314`	32	SYSCFG user register 5
`SYSCFG_UR5_MESAD_BANK1`		0	Mass erase secured area disabled for bank 1
`SYSCFG_UR5_WRPN_BANK1`		16:23	Write protection for flash bank 1
`UR6`	`0x318`	32	SYSCFG user register 6
`SYSCFG_UR6_PABEG_BANK1`		0:11	Protected area start address for bank 1
`SYSCFG_UR6_PAEND_BANK1`		16:27	Protected area end address for bank 1
`UR7`	`0x31C`	32	SYSCFG user register 7
`SYSCFG_UR7_SABEG_BANK1`		0:11	Secured area start address for bank 1
`SYSCFG_UR7_SAEND_BANK1`		16:27	Secured area end address for bank 1
`UR8`	`0x320`	32	SYSCFG user register 8
`SYSCFG_UR8_MEPAD_BANK2`		0	Mass erase Protected area disabled for bank 2
`SYSCFG_UR8_MESAD_BANK2`		16	Mass Erase Secured Area Disabled for bank 2
`UR9`	`0x324`	32	SYSCFG user register 9
`SYSCFG_UR9_WRPN_BANK2`		0:7	Write protection for flash bank 2
`SYSCFG_UR9_PABEG_BANK2`		16:27	Protected area start address for bank 2
`UR10`	`0x328`	32	SYSCFG user register 10
`SYSCFG_UR10_PAEND_BANK2`		0:11	Protected area end address for bank 2
`SYSCFG_UR10_SABEG_BANK2`		16:27	Secured area start address for bank 2
`UR11`	`0x32C`	32	SYSCFG user register 11
`SYSCFG_UR11_SAEND_BANK2`		0:11	Secured area end address for bank 2
`SYSCFG_UR11_IWDG1M`		16	Independent Watchdog 1 mode (SW or HW)
`UR12`	`0x330`	32	SYSCFG user register 12
`SYSCFG_UR12_SECURE`		16	Secure mode status
`UR13`	`0x334`	32	SYSCFG user register 13
`SYSCFG_UR13_SDRS`		0:1	Secured DTCM RAM Size
`SYSCFG_UR13_D1SBRST`		16	D1 Standby reset
`UR14`	`0x338`	32	SYSCFG user register 14
`SYSCFG_UR14_D1STPRST`		0	D1 Stop Reset
`UR15`	`0x33C`	32	SYSCFG user register 15
`SYSCFG_UR15_FZIWDGSTB`		16	Freeze independent watchdogs in Standby mode
`UR16`	`0x340`	32	SYSCFG user register 16
`SYSCFG_UR16_FZIWDGSTP`		0	Freeze independent watchdogs in Stop mode
`SYSCFG_UR16_PKP`		16	Private key programmed
`UR17`	`0x344`	32	SYSCFG user register 17
`SYSCFG_UR17_IOHSLV`		0	I/O high speed / low voltage

EXTI — Внешние прерывания (раздел 7)

Регистр	Смещение	Бит	Назначение
`RTSR1`	`0x00`	32	EXTI Rising trigger selection register
`EXTI_RTSR1_TR`		0:21	Rising trigger event configuration bit
`EXTI_RTSR1_TR0`		0	Rising trigger event configuration bit of line 0
`EXTI_RTSR1_TR1`		1	Rising trigger event configuration bit of line 1
`EXTI_RTSR1_TR2`		2	Rising trigger event configuration bit of line 2
`EXTI_RTSR1_TR3`		3	Rising trigger event configuration bit of line 3
`EXTI_RTSR1_TR4`		4	Rising trigger event configuration bit of line 4
`EXTI_RTSR1_TR5`		5	Rising trigger event configuration bit of line 5
`EXTI_RTSR1_TR6`		6	Rising trigger event configuration bit of line 6
`EXTI_RTSR1_TR7`		7	Rising trigger event configuration bit of line 7
`EXTI_RTSR1_TR8`		8	Rising trigger event configuration bit of line 8
`EXTI_RTSR1_TR9`		9	Rising trigger event configuration bit of line 9
`EXTI_RTSR1_TR10`		10	Rising trigger event configuration bit of line 10
`EXTI_RTSR1_TR11`		11	Rising trigger event configuration bit of line 11
`EXTI_RTSR1_TR12`		12	Rising trigger event configuration bit of line 12
`EXTI_RTSR1_TR13`		13	Rising trigger event configuration bit of line 13
`EXTI_RTSR1_TR14`		14	Rising trigger event configuration bit of line 14
`EXTI_RTSR1_TR15`		15	Rising trigger event configuration bit of line 15
`EXTI_RTSR1_TR16`		16	Rising trigger event configuration bit of line 16
`EXTI_RTSR1_TR17`		17	Rising trigger event configuration bit of line 17
`EXTI_RTSR1_TR18`		18	Rising trigger event configuration bit of line 18
`EXTI_RTSR1_TR19`		19	Rising trigger event configuration bit of line 19
`EXTI_RTSR1_TR20`		20	Rising trigger event configuration bit of line 20
`EXTI_RTSR1_TR21`		21	Rising trigger event configuration bit of line 21
`FTSR1`	`0x04`	32	EXTI Falling trigger selection register
`EXTI_FTSR1_TR`		0:21	Falling trigger event configuration bit
`EXTI_FTSR1_TR0`		0	Falling trigger event configuration bit of line 0
`EXTI_FTSR1_TR1`		1	Falling trigger event configuration bit of line 1
`EXTI_FTSR1_TR2`		2	Falling trigger event configuration bit of line 2
`EXTI_FTSR1_TR3`		3	Falling trigger event configuration bit of line 3
`EXTI_FTSR1_TR4`		4	Falling trigger event configuration bit of line 4
`EXTI_FTSR1_TR5`		5	Falling trigger event configuration bit of line 5
`EXTI_FTSR1_TR6`		6	Falling trigger event configuration bit of line 6
`EXTI_FTSR1_TR7`		7	Falling trigger event configuration bit of line 7
`EXTI_FTSR1_TR8`		8	Falling trigger event configuration bit of line 8
`EXTI_FTSR1_TR9`		9	Falling trigger event configuration bit of line 9
`EXTI_FTSR1_TR10`		10	Falling trigger event configuration bit of line 10
`EXTI_FTSR1_TR11`		11	Falling trigger event configuration bit of line 11
`EXTI_FTSR1_TR12`		12	Falling trigger event configuration bit of line 12
`EXTI_FTSR1_TR13`		13	Falling trigger event configuration bit of line 13
`EXTI_FTSR1_TR14`		14	Falling trigger event configuration bit of line 14
`EXTI_FTSR1_TR15`		15	Falling trigger event configuration bit of line 15
`EXTI_FTSR1_TR16`		16	Falling trigger event configuration bit of line 16
`EXTI_FTSR1_TR17`		17	Falling trigger event configuration bit of line 17
`EXTI_FTSR1_TR18`		18	Falling trigger event configuration bit of line 18
`EXTI_FTSR1_TR19`		19	Falling trigger event configuration bit of line 19
`EXTI_FTSR1_TR20`		20	Falling trigger event configuration bit of line 20
`EXTI_FTSR1_TR21`		21	Falling trigger event configuration bit of line 21
`SWIER1`	`0x08`	32	EXTI Software interrupt event register
`EXTI_SWIER1_SWIER0`		0	Software Interrupt on line 0
`EXTI_SWIER1_SWIER1`		1	Software Interrupt on line 1
`EXTI_SWIER1_SWIER2`		2	Software Interrupt on line 2
`EXTI_SWIER1_SWIER3`		3	Software Interrupt on line 3
`EXTI_SWIER1_SWIER4`		4	Software Interrupt on line 4
`EXTI_SWIER1_SWIER5`		5	Software Interrupt on line 5
`EXTI_SWIER1_SWIER6`		6	Software Interrupt on line 6
`EXTI_SWIER1_SWIER7`		7	Software Interrupt on line 7
`EXTI_SWIER1_SWIER8`		8	Software Interrupt on line 8
`EXTI_SWIER1_SWIER9`		9	Software Interrupt on line 9
`EXTI_SWIER1_SWIER10`		10	Software Interrupt on line 10
`EXTI_SWIER1_SWIER11`		11	Software Interrupt on line 11
`EXTI_SWIER1_SWIER12`		12	Software Interrupt on line 12
`EXTI_SWIER1_SWIER13`		13	Software Interrupt on line 13
`EXTI_SWIER1_SWIER14`		14	Software Interrupt on line 14
`EXTI_SWIER1_SWIER15`		15	Software Interrupt on line 15
`EXTI_SWIER1_SWIER16`		16	Software Interrupt on line 16
`EXTI_SWIER1_SWIER17`		17	Software Interrupt on line 17
`EXTI_SWIER1_SWIER18`		18	Software Interrupt on line 18
`EXTI_SWIER1_SWIER19`		19	Software Interrupt on line 19
`EXTI_SWIER1_SWIER20`		20	Software Interrupt on line 20
`EXTI_SWIER1_SWIER21`		21	Software Interrupt on line 21
`D3PMR1`	`0x0C`	32	EXTI D3 Pending mask register, (same register as to SRDPMR1)
`EXTI_D3PMR1_MR0`		0	Pending Mask Event for line 0
`EXTI_D3PMR1_MR1`		1	Pending Mask Event for line 1
`EXTI_D3PMR1_MR2`		2	Pending Mask Event for line 2
`EXTI_D3PMR1_MR3`		3	Pending Mask Event for line 3
`EXTI_D3PMR1_MR4`		4	Pending Mask Event for line 4
`EXTI_D3PMR1_MR5`		5	Pending Mask Event for line 5
`EXTI_D3PMR1_MR6`		6	Pending Mask Event for line 6
`EXTI_D3PMR1_MR7`		7	Pending Mask Event for line 7
`EXTI_D3PMR1_MR8`		8	Pending Mask Event for line 8
`EXTI_D3PMR1_MR9`		9	Pending Mask Event for line 9
`EXTI_D3PMR1_MR10`		10	Pending Mask Event for line 10
`EXTI_D3PMR1_MR11`		11	Pending Mask Event for line 11
`EXTI_D3PMR1_MR12`		12	Pending Mask Event for line 12
`EXTI_D3PMR1_MR13`		13	Pending Mask Event for line 13
`EXTI_D3PMR1_MR14`		14	Pending Mask Event for line 14
`EXTI_D3PMR1_MR15`		15	Pending Mask Event for line 15
`EXTI_D3PMR1_MR19`		19	Pending Mask Event for line 19
`EXTI_D3PMR1_MR20`		20	Pending Mask Event for line 20
`EXTI_D3PMR1_MR21`		21	Pending Mask Event for line 21
`EXTI_D3PMR1_MR25`		24	Pending Mask Event for line 25
`D3PCR1L`	`0x10`	32	EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)
`EXTI_D3PCR1L_PCS0`		0:1	D3 Pending request clear input signal selection on line 0
`EXTI_D3PCR1L_PCS2`		4:5	D3 Pending request clear input signal selection on line 2
`EXTI_D3PCR1L_PCS1`		6:7	D3 Pending request clear input signal selection on line 1
`EXTI_D3PCR1L_PCS3`		6:7	D3 Pending request clear input signal selection on line 3
`EXTI_D3PCR1L_PCS4`		8:9	D3 Pending request clear input signal selection on line 4
`EXTI_D3PCR1L_PCS5`		10:11	D3 Pending request clear input signal selection on line 5
`EXTI_D3PCR1L_PCS6`		12:13	D3 Pending request clear input signal selection on line 6
`EXTI_D3PCR1L_PCS7`		14:15	D3 Pending request clear input signal selection on line 7
`EXTI_D3PCR1L_PCS8`		16:17	D3 Pending request clear input signal selection on line 8
`EXTI_D3PCR1L_PCS9`		18:19	D3 Pending request clear input signal selection on line 9
`EXTI_D3PCR1L_PCS10`		20:21	D3 Pending request clear input signal selection on line 10
`EXTI_D3PCR1L_PCS11`		22:23	D3 Pending request clear input signal selection on line 11
`EXTI_D3PCR1L_PCS12`		24:25	D3 Pending request clear input signal selection on line 12
`EXTI_D3PCR1L_PCS13`		26:27	D3 Pending request clear input signal selection on line 13
`EXTI_D3PCR1L_PCS14`		28:29	D3 Pending request clear input signal selection on line 14
`EXTI_D3PCR1L_PCS15`		30:31	D3 Pending request clear input signal selection on line 15
`D3PCR1H`	`0x14`	32	EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)
`EXTI_D3PCR1H_PCS19`		6:7	D3 Pending request clear input signal selection on line 19
`EXTI_D3PCR1H_PCS20`		8:9	D3 Pending request clear input signal selection on line 20
`EXTI_D3PCR1H_PCS21`		10:11	D3 Pending request clear input signal selection on line 21
`EXTI_D3PCR1H_PCS25`		18:19	D3 Pending request clear input signal selection on line 25
`RTSR2`	`0x20`	32	EXTI Rising trigger selection register
`EXTI_RTSR2_TR`		17:19	Rising trigger event configuration bit
`EXTI_RTSR2_TR49`		17	Rising trigger event configuration bit of line 49
`EXTI_RTSR2_TR51`		19	Rising trigger event configuration bit of line 51
`FTSR2`	`0x24`	32	EXTI Falling trigger selection register
`EXTI_FTSR2_TR`		17:19	Falling trigger event configuration bit
`EXTI_FTSR2_TR49`		17	Falling trigger event configuration bit of line 49
`EXTI_FTSR2_TR51`		19	Falling trigger event configuration bit of line 51
`SWIER2`	`0x28`	32	EXTI Software interrupt event register
`EXTI_SWIER2_SWIER49`		17	Software Interrupt on line 49
`EXTI_SWIER2_SWIER51`		19	Software Interrupt on line 51
`D3PMR2`	`0x2C`	32	EXTI D3 Pending mask register, (same register as to SRDPMR2)
`EXTI_D3PMR2_MR34`		2	Pending Mask Event for line 34
`EXTI_D3PMR2_MR35`		3	Pending Mask Event for line 35
`EXTI_D3PMR2_MR41`		9	Pending Mask Event for line 41
`EXTI_D3PMR2_MR48`		16	Pending Mask Event for line 48
`EXTI_D3PMR2_MR49`		17	Pending Mask Event for line 49
`EXTI_D3PMR2_MR50`		18	Pending Mask Event for line 50
`EXTI_D3PMR2_MR51`		19	Pending Mask Event for line 51
`EXTI_D3PMR2_MR52`		20	Pending Mask Event for line 52
`EXTI_D3PMR2_MR53`		21	Pending Mask Event for line 53
`D3PCR2L`	`0x30`	32	EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)
`EXTI_D3PCR2L_PCS34`		4:5	D3 Pending request clear input signal selection on line 34
`EXTI_D3PCR2L_PCS35`		6:7	D3 Pending request clear input signal selection on line 35
`EXTI_D3PCR2L_PCS41`		18:19	D3 Pending request clear input signal selection on line 41
`D3PCR2H`	`0x34`	32	EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H)
`EXTI_D3PCR2H_PCS48`		0:1	D3 Pending request clear input signal selection on line 48
`EXTI_D3PCR2H_PCS49`		2:3	D3 Pending request clear input signal selection on line 49
`EXTI_D3PCR2H_PCS50`		4:5	D3 Pending request clear input signal selection on line 50
`EXTI_D3PCR2H_PCS51`		6:7	D3 Pending request clear input signal selection on line 51
`EXTI_D3PCR2H_PCS52`		8:9	D3 Pending request clear input signal selection on line 52
`EXTI_D3PCR2H_PCS53`		10:11	D3 Pending request clear input signal selection on line 53
`RTSR3`	`0x40`	32	EXTI Rising trigger selection register
`EXTI_RTSR3_TR`		18:22	Rising trigger event configuration bit
`EXTI_RTSR3_TR82`		18	Rising trigger event configuration bit of line 82
`EXTI_RTSR3_TR84`		20	Rising trigger event configuration bit of line 84
`EXTI_RTSR3_TR85`		21	Rising trigger event configuration bit of line 85
`EXTI_RTSR3_TR86`		22	Rising trigger event configuration bit of line 86
`FTSR3`	`0x44`	32	EXTI Falling trigger selection register
`EXTI_FTSR3_TR`		18:22	Falling trigger event configuration bit
`EXTI_FTSR3_TR82`		18	Falling trigger event configuration bit of line 82
`EXTI_FTSR3_TR84`		20	Falling trigger event configuration bit of line 84
`EXTI_FTSR3_TR85`		21	Falling trigger event configuration bit of line 85
`EXTI_FTSR3_TR86`		22	Falling trigger event configuration bit of line 86
`SWIER3`	`0x48`	32	EXTI Software interrupt event register
`EXTI_SWIER3_SWI`		18:22	Software Interrupt event bit
`EXTI_SWIER3_SWIER82`		18	Software Interrupt on line 82
`EXTI_SWIER3_SWIER84`		20	Software Interrupt on line 84
`EXTI_SWIER3_SWIER85`		21	Software Interrupt on line 85
`EXTI_SWIER3_SWIER86`		22	Software Interrupt on line 86
`D3PMR3`	`0x4C`	32	EXTI D3 Pending mask register, (same register as to SRDPMR3)
`D3PCR3L`	`0x50`	32	EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L)
`D3PCR3H`	`0x54`	32	EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H)
`IMR1`	`0x80`	32	EXTI Interrupt mask register
`EXTI_IMR1_IM`		0:31	Interrupt Mask
`EXTI_IMR1_IM0`		0	Interrupt Mask on line 0
`EXTI_IMR1_IM1`		1	Interrupt Mask on line 1
`EXTI_IMR1_IM2`		2	Interrupt Mask on line 2
`EXTI_IMR1_IM3`		3	Interrupt Mask on line 3
`EXTI_IMR1_IM4`		4	Interrupt Mask on line 4
`EXTI_IMR1_IM5`		5	Interrupt Mask on line 5
`EXTI_IMR1_IM6`		6	Interrupt Mask on line 6
`EXTI_IMR1_IM7`		7	Interrupt Mask on line 7
`EXTI_IMR1_IM8`		8	Interrupt Mask on line 8
`EXTI_IMR1_IM9`		9	Interrupt Mask on line 9
`EXTI_IMR1_IM10`		10	Interrupt Mask on line 10
`EXTI_IMR1_IM11`		11	Interrupt Mask on line 11
`EXTI_IMR1_IM12`		12	Interrupt Mask on line 12
`EXTI_IMR1_IM13`		13	Interrupt Mask on line 13
`EXTI_IMR1_IM14`		14	Interrupt Mask on line 14
`EXTI_IMR1_IM15`		15	Interrupt Mask on line 15
`EXTI_IMR1_IM16`		16	Interrupt Mask on line 16
`EXTI_IMR1_IM17`		17	Interrupt Mask on line 17
`EXTI_IMR1_IM18`		18	Interrupt Mask on line 18
`EXTI_IMR1_IM19`		19	Interrupt Mask on line 19
`EXTI_IMR1_IM20`		20	Interrupt Mask on line 20
`EXTI_IMR1_IM21`		21	Interrupt Mask on line 21
`EXTI_IMR1_IM22`		22	Interrupt Mask on line 22
`EXTI_IMR1_IM23`		23	Interrupt Mask on line 23
`EXTI_IMR1_IM24`		24	Interrupt Mask on line 24
`EXTI_IMR1_IM25`		25	Interrupt Mask on line 25
`EXTI_IMR1_IM26`		26	Interrupt Mask on line 26
`EXTI_IMR1_IM27`		27	Interrupt Mask on line 27
`EXTI_IMR1_IM28`		28	Interrupt Mask on line 28
`EXTI_IMR1_IM29`		29	Interrupt Mask on line 29
`EXTI_IMR1_IM30`		30	Interrupt Mask on line 30
`EXTI_IMR1_IM31`		31	Interrupt Mask on line 31
`EMR1`	`0x84`	32	EXTI Event mask register
`EXTI_EMR1_EM`		0:31	Event Mask
`EXTI_EMR1_EM0`		0	Event Mask on line 0
`EXTI_EMR1_EM1`		1	Event Mask on line 1
`EXTI_EMR1_EM2`		2	Event Mask on line 2
`EXTI_EMR1_EM3`		3	Event Mask on line 3
`EXTI_EMR1_EM4`		4	Event Mask on line 4
`EXTI_EMR1_EM5`		5	Event Mask on line 5
`EXTI_EMR1_EM6`		6	Event Mask on line 6
`EXTI_EMR1_EM7`		7	Event Mask on line 7
`EXTI_EMR1_EM8`		8	Event Mask on line 8
`EXTI_EMR1_EM9`		9	Event Mask on line 9
`EXTI_EMR1_EM10`		10	Event Mask on line 10
`EXTI_EMR1_EM11`		11	Event Mask on line 11
`EXTI_EMR1_EM12`		12	Event Mask on line 12
`EXTI_EMR1_EM13`		13	Event Mask on line 13
`EXTI_EMR1_EM14`		14	Event Mask on line 14
`EXTI_EMR1_EM15`		15	Event Mask on line 15
`EXTI_EMR1_EM16`		16	Event Mask on line 16
`EXTI_EMR1_EM17`		17	Event Mask on line 17
`EXTI_EMR1_EM18`		18	Event Mask on line 18
`EXTI_EMR1_EM20`		20	Event Mask on line 20
`EXTI_EMR1_EM21`		21	Event Mask on line 21
`EXTI_EMR1_EM22`		22	Event Mask on line 22
`EXTI_EMR1_EM23`		23	Event Mask on line 23
`EXTI_EMR1_EM24`		24	Event Mask on line 24
`EXTI_EMR1_EM25`		25	Event Mask on line 25
`EXTI_EMR1_EM26`		26	Event Mask on line 26
`EXTI_EMR1_EM27`		27	Event Mask on line 27
`EXTI_EMR1_EM28`		28	Event Mask on line 28
`EXTI_EMR1_EM29`		29	Event Mask on line 29
`EXTI_EMR1_EM30`		30	Event Mask on line 30
`EXTI_EMR1_EM31`		31	Event Mask on line 31
`PR1`	`0x88`	32	EXTI Pending register
`EXTI_PR1_PR`		0:21	Pending bit
`EXTI_PR1_PR0`		0	Pending bit for line 0
`EXTI_PR1_PR1`		1	Pending bit for line 1
`EXTI_PR1_PR2`		2	Pending bit for line 2
`EXTI_PR1_PR3`		3	Pending bit for line 3
`EXTI_PR1_PR4`		4	Pending bit for line 4
`EXTI_PR1_PR5`		5	Pending bit for line 5
`EXTI_PR1_PR6`		6	Pending bit for line 6
`EXTI_PR1_PR7`		7	Pending bit for line 7
`EXTI_PR1_PR8`		8	Pending bit for line 8
`EXTI_PR1_PR9`		9	Pending bit for line 9
`EXTI_PR1_PR10`		10	Pending bit for line 10
`EXTI_PR1_PR11`		11	Pending bit for line 11
`EXTI_PR1_PR12`		12	Pending bit for line 12
`EXTI_PR1_PR13`		13	Pending bit for line 13
`EXTI_PR1_PR14`		14	Pending bit for line 14
`EXTI_PR1_PR15`		15	Pending bit for line 15
`EXTI_PR1_PR16`		16	Pending bit for line 16
`EXTI_PR1_PR17`		17	Pending bit for line 17
`EXTI_PR1_PR18`		18	Pending bit for line 18
`EXTI_PR1_PR19`		19	Pending bit for line 19
`EXTI_PR1_PR20`		20	Pending bit for line 20
`EXTI_PR1_PR21`		21	Pending bit for line 21
`IMR2`	`0x90`	32	EXTI Interrupt mask register
`EXTI_IMR2_IM`		0:31	Interrupt Mask
`EXTI_IMR2_IM32`		0	Interrupt Mask on line 32
`EXTI_IMR2_IM33`		1	Interrupt Mask on line 33
`EXTI_IMR2_IM34`		2	Interrupt Mask on line 34
`EXTI_IMR2_IM35`		3	Interrupt Mask on line 35
`EXTI_IMR2_IM36`		4	Interrupt Mask on line 36
`EXTI_IMR2_IM37`		5	Interrupt Mask on line 37
`EXTI_IMR2_IM38`		6	Interrupt Mask on line 38
`EXTI_IMR2_IM39`		7	Interrupt Mask on line 39
`EXTI_IMR2_IM40`		8	Interrupt Mask on line 40
`EXTI_IMR2_IM41`		9	Interrupt Mask on line 41
`EXTI_IMR2_IM42`		10	Interrupt Mask on line 42
`EXTI_IMR2_IM43`		11	Interrupt Mask on line 43
`EXTI_IMR2_IM44`		12	Interrupt Mask on line 44
`EXTI_IMR2_IM46`		14	Interrupt Mask on line 46
`EXTI_IMR2_IM47`		15	Interrupt Mask on line 47
`EXTI_IMR2_IM48`		16	Interrupt Mask on line 48
`EXTI_IMR2_IM49`		17	Interrupt Mask on line 49
`EXTI_IMR2_IM50`		18	Interrupt Mask on line 50
`EXTI_IMR2_IM51`		19	Interrupt Mask on line 51
`EXTI_IMR2_IM52`		20	Interrupt Mask on line 52
`EXTI_IMR2_IM53`		21	Interrupt Mask on line 53
`EXTI_IMR2_IM54`		22	Interrupt Mask on line 54
`EXTI_IMR2_IM55`		23	Interrupt Mask on line 55
`EXTI_IMR2_IM56`		24	Interrupt Mask on line 56
`EXTI_IMR2_IM57`		25	Interrupt Mask on line 57
`EXTI_IMR2_IM58`		26	Interrupt Mask on line 58
`EXTI_IMR2_IM59`		27	Interrupt Mask on line 59
`EXTI_IMR2_IM60`		28	Interrupt Mask on line 60
`EXTI_IMR2_IM61`		29	Interrupt Mask on line 61
`EXTI_IMR2_IM62`		30	Interrupt Mask on line 62
`EXTI_IMR2_IM63`		31	Interrupt Mask on line 63
`EMR2`	`0x94`	32	EXTI Event mask register
`EXTI_EMR2_EM`		0:31	Event Mask
`EXTI_EMR2_EM32`		0	Event Mask on line 32
`EXTI_EMR2_EM33`		1	Event Mask on line 33
`EXTI_EMR2_EM34`		2	Event Mask on line 34
`EXTI_EMR2_EM35`		3	Event Mask on line 35
`EXTI_EMR2_EM36`		4	Event Mask on line 36
`EXTI_EMR2_EM37`		5	Event Mask on line 37
`EXTI_EMR2_EM38`		6	Event Mask on line 38
`EXTI_EMR2_EM39`		7	Event Mask on line 39
`EXTI_EMR2_EM40`		8	Event Mask on line 40
`EXTI_EMR2_EM41`		9	Event Mask on line 41
`EXTI_EMR2_EM42`		10	Event Mask on line 42
`EXTI_EMR2_EM43`		11	Event Mask on line 43
`EXTI_EMR2_EM44`		12	Event Mask on line 44
`EXTI_EMR2_EM46`		14	Event Mask on line 46
`EXTI_EMR2_EM47`		15	Event Mask on line 47
`EXTI_EMR2_EM48`		16	Event Mask on line 48
`EXTI_EMR2_EM49`		17	Event Mask on line 49
`EXTI_EMR2_EM50`		18	Event Mask on line 50
`EXTI_EMR2_EM51`		19	Event Mask on line 51
`EXTI_EMR2_EM52`		20	Event Mask on line 52
`EXTI_EMR2_EM53`		21	Event Mask on line 53
`EXTI_EMR2_EM54`		22	Event Mask on line 54
`EXTI_EMR2_EM55`		23	Event Mask on line 55
`EXTI_EMR2_EM56`		24	Event Mask on line 56
`EXTI_EMR2_EM57`		25	Event Mask on line 57
`EXTI_EMR2_EM58`		26	Event Mask on line 58
`EXTI_EMR2_EM59`		27	Event Mask on line 59
`EXTI_EMR2_EM60`		28	Event Mask on line 60
`EXTI_EMR2_EM61`		29	Event Mask on line 61
`EXTI_EMR2_EM62`		30	Event Mask on line 62
`EXTI_EMR2_EM63`		31	Event Mask on line 63
`PR2`	`0x98`	32	EXTI Pending register
`EXTI_PR2_PR`		17:19	Pending bit
`EXTI_PR2_PR49`		17	Pending bit for line 49
`EXTI_PR2_PR51`		19	Pending bit for line 51
`IMR3`	`0xA0`	32	EXTI Interrupt mask register
`EXTI_IMR3_IM`		0:23	Interrupt Mask
`EXTI_IMR3_IM64`		0	Interrupt Mask on line 64
`EXTI_IMR3_IM65`		1	Interrupt Mask on line 65
`EXTI_IMR3_IM66`		2	Interrupt Mask on line 66
`EXTI_IMR3_IM67`		3	Interrupt Mask on line 67
`EXTI_IMR3_IM68`		4	Interrupt Mask on line 68
`EXTI_IMR3_IM69`		5	Interrupt Mask on line 69
`EXTI_IMR3_IM70`		6	Interrupt Mask on line 70
`EXTI_IMR3_IM71`		7	Interrupt Mask on line 71
`EXTI_IMR3_IM72`		8	Interrupt Mask on line 72
`EXTI_IMR3_IM73`		9	Interrupt Mask on line 73
`EXTI_IMR3_IM74`		10	Interrupt Mask on line 74
`EXTI_IMR3_IM75`		11	Interrupt Mask on line 75
`EXTI_IMR3_IM76`		12	Interrupt Mask on line 76
`EXTI_IMR3_IM77`		13	Interrupt Mask on line 77
`EXTI_IMR3_IM78`		14	Interrupt Mask on line 78
`EXTI_IMR3_IM79`		15	Interrupt Mask on line 79
`EXTI_IMR3_IM80`		16	Interrupt Mask on line 80
`EXTI_IMR3_IM82`		18	Interrupt Mask on line 82
`EXTI_IMR3_IM84`		20	Interrupt Mask on line 84
`EXTI_IMR3_IM85`		21	Interrupt Mask on line 85
`EXTI_IMR3_IM86`		22	Interrupt Mask on line 86
`EXTI_IMR3_IM87`		23	Interrupt Mask on line 87
`EMR3`	`0xA4`	32	EXTI Event mask register
`EXTI_EMR3_EM`		0:23	Event Mask
`EXTI_EMR3_EM64`		0	Event Mask on line 64
`EXTI_EMR3_EM65`		1	Event Mask on line 65
`EXTI_EMR3_EM66`		2	Event Mask on line 66
`EXTI_EMR3_EM67`		3	Event Mask on line 67
`EXTI_EMR3_EM68`		4	Event Mask on line 68
`EXTI_EMR3_EM69`		5	Event Mask on line 69
`EXTI_EMR3_EM70`		6	Event Mask on line 70
`EXTI_EMR3_EM71`		7	Event Mask on line 71
`EXTI_EMR3_EM72`		8	Event Mask on line 72
`EXTI_EMR3_EM73`		9	Event Mask on line 73
`EXTI_EMR3_EM74`		10	Event Mask on line 74
`EXTI_EMR3_EM75`		11	Event Mask on line 75
`EXTI_EMR3_EM76`		12	Event Mask on line 76
`EXTI_EMR3_EM77`		13	Event Mask on line 77
`EXTI_EMR3_EM78`		14	Event Mask on line 78
`EXTI_EMR3_EM79`		15	Event Mask on line 79
`EXTI_EMR3_EM80`		16	Event Mask on line 80
`EXTI_EMR3_EM81`		17	Event Mask on line 81
`EXTI_EMR3_EM82`		18	Event Mask on line 82
`EXTI_EMR3_EM84`		20	Event Mask on line 84
`EXTI_EMR3_EM85`		21	Event Mask on line 85
`EXTI_EMR3_EM86`		22	Event Mask on line 86
`EXTI_EMR3_EM87`		23	Event Mask on line 87
`PR3`	`0xA8`	32	EXTI Pending register
`EXTI_PR3_PR`		18:22	Pending bit
`EXTI_PR3_PR82`		18	Pending bit for line 82
`EXTI_PR3_PR84`		20	Pending bit for line 84
`EXTI_PR3_PR85`		21	Pending bit for line 85
`EXTI_PR3_PR86`		22	Pending bit for line 86

DMA — Поток DMA (раздел 9)

Регистр	Смещение	Бит	Назначение
`CR`	`0x00`	32	DMA stream x configuration register
`NDTR`	`0x04`	32	DMA stream x number of data register
`PAR`	`0x08`	32	DMA stream x peripheral address register
`M0AR`	`0x0C`	32	DMA stream x memory 0 address register
`M1AR`	`0x10`	32	DMA stream x memory 1 address register
`FCR`	`0x14`	32	DMA stream x FIFO control register

PWR — Питание и режимы сна (раздел 10)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	PWR power control register 1
`PWR_CR1_LPDS`		0	Low Power Deepsleep with SVOS3
`PWR_CR1_PVDEN`		4	Programmable Voltage detector enable
`PWR_CR1_PLS`		5:7	Programmable Voltage Detector level selection
`PWR_CR1_PLS_LEV1`		5	PVD level 1
`PWR_CR1_PLS_LEV3`		5:6	PVD level 3
`PWR_CR1_PLS_LEV5`		5:7	PVD level 5
`PWR_CR1_PLS_LEV7`		5:7	PVD level 7
`PWR_CR1_PLS_LEV2`		6	PVD level 2
`PWR_CR1_PLS_LEV6`		6:7	PVD level 6
`PWR_CR1_PLS_LEV4`		7	PVD level 4
`PWR_CR1_DBP`		8	Disable Back-up domain Protection
`PWR_CR1_FLPS`		9	Flash low power mode in DSTOP
`PWR_CR1_SVOS`		14:15	System STOP mode Voltage Scaling selection
`PWR_CR1_AVDEN`		16	Analog Voltage Detector Enable
`PWR_CR1_ALS`		17:18	Analog Voltage Detector level selection
`PWR_CR1_ALS_LEV1`		17	AVD level 1
`PWR_CR1_ALS_LEV3`		17:18	AVD level 3
`PWR_CR1_ALS_LEV2`		18	AVD level 2
`CSR1`	`0x04`	32	PWR power control status register 1
`PWR_CSR1_PVDO`		4	Programmable Voltage Detect Output
`PWR_CSR1_ACTVOSRDY`		13	Ready bit for current actual used VOS for VDD11 Voltage Scaling
`PWR_CSR1_ACTVOS`		14:15	Current actual used VOS for VDD11 Voltage Scaling
`PWR_CSR1_AVDO`		16	Analog Voltage Detect Output
`CR2`	`0x08`	32	PWR power control register 2
`PWR_CR2_BREN`		0	Backup regulator enable
`PWR_CR2_MONEN`		4	VBAT and temperature monitoring enable
`PWR_CR2_BRRDY`		16	Backup regulator ready
`PWR_CR2_VBATL`		20	Monitored VBAT level above low threshold
`PWR_CR2_VBATH`		21	Monitored VBAT level above high threshold
`PWR_CR2_TEMPL`		22	Monitored temperature level above low threshold
`PWR_CR2_TEMPH`		23	Monitored temperature level above high threshold
`CR3`	`0x0C`	32	PWR power control register 3
`PWR_CR3_BYPASS`		0	Power Management Unit bypass
`PWR_CR3_LDOEN`		1	Low Drop Output regulator enable
`PWR_CR3_SCUEN`		2	Supply configuration update enable
`PWR_CR3_VBE`		8	VBAT charging enable
`PWR_CR3_VBRS`		9	VBAT charging resistor selection
`PWR_CR3_USB33DEN`		24	VDD33_USB voltage level detector enable
`PWR_CR3_USBREGEN`		25	USB regulator enable
`PWR_CR3_USB33RDY`		26	USB supply ready
`CPUCR`	`0x10`	32	PWR CPU control register
`PWR_CPUCR_PDDS_D1`		0	D1 domain Power Down Deepsleep selection
`PWR_CPUCR_PDDS_D2`		1	D2 domain Power Down Deepsleep
`PWR_CPUCR_PDDS_D3`		2	System D3 domain Power Down Deepsleep
`PWR_CPUCR_STOPF`		5	STOP Flag
`PWR_CPUCR_SBF`		6	System STANDBY Flag
`PWR_CPUCR_SBF_D1`		7	D1 domain DSTANDBY Flag
`PWR_CPUCR_SBF_D2`		8	D2 domain DSTANDBY Flag
`PWR_CPUCR_CSSF`		9	Clear D1 domain CPU1 STANDBY, STOP and HOLD flags
`PWR_CPUCR_RUN_D3`		11	Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes
`D3CR`	`0x18`	32	PWR D3 domain control register
`PWR_D3CR_VOSRDY`		13	VOS Ready bit for VDD11 Voltage Scaling output selection
`PWR_D3CR_VOS`		14:15	Voltage Scaling selection according performance
`WKUPCR`	`0x20`	32	PWR wakeup clear register
`PWR_WKUPCR_WKUPC1`		0	Clear Wakeup Pin Flag 1
`PWR_WKUPCR_WKUPC2`		1	Clear Wakeup Pin Flag 2
`PWR_WKUPCR_WKUPC3`		2	Clear Wakeup Pin Flag 3
`PWR_WKUPCR_WKUPC4`		3	Clear Wakeup Pin Flag 4
`PWR_WKUPCR_WKUPC5`		4	Clear Wakeup Pin Flag 5
`PWR_WKUPCR_WKUPC6`		5	Clear Wakeup Pin Flag 6
`WKUPFR`	`0x24`	32	PWR wakeup flag register
`PWR_WKUPFR_WKUPF1`		0	Wakeup Pin Flag 1
`PWR_WKUPFR_WKUPF2`		1	Wakeup Pin Flag 2
`PWR_WKUPFR_WKUPF3`		2	Wakeup Pin Flag 3
`PWR_WKUPFR_WKUPF4`		3	Wakeup Pin Flag 4
`PWR_WKUPFR_WKUPF5`		4	Wakeup Pin Flag 5
`PWR_WKUPFR_WKUPF6`		5	Wakeup Pin Flag 6
`WKUPEPR`	`0x28`	32	PWR wakeup enable and polarity register
`PWR_WKUPEPR_WKUPEN1`		0	Enable Wakeup Pin WKUP1
`PWR_WKUPEPR_WKUPEN`		0:5	Enable all Wakeup Pin
`PWR_WKUPEPR_WKUPEN2`		1	Enable Wakeup Pin WKUP2
`PWR_WKUPEPR_WKUPEN3`		2	Enable Wakeup Pin WKUP3
`PWR_WKUPEPR_WKUPEN4`		3	Enable Wakeup Pin WKUP4
`PWR_WKUPEPR_WKUPEN5`		4	Enable Wakeup Pin WKUP5
`PWR_WKUPEPR_WKUPEN6`		5	Enable Wakeup Pin WKUP6
`PWR_WKUPEPR_WKUPP1`		8	Wakeup Pin Polarity for WKUP1
`PWR_WKUPEPR_WKUPP2`		9	Wakeup Pin Polarity for WKUP2
`PWR_WKUPEPR_WKUPP3`		10	Wakeup Pin Polarity for WKUP3
`PWR_WKUPEPR_WKUPP4`		11	Wakeup Pin Polarity for WKUP4
`PWR_WKUPEPR_WKUPP5`		12	Wakeup Pin Polarity for WKUP5
`PWR_WKUPEPR_WKUPP6`		13	Wakeup Pin Polarity for WKUP6
`PWR_WKUPEPR_WKUPPUPD1`		16:17	Wakeup Pin pull configuration for WKUP1
`PWR_WKUPEPR_WKUPPUPD2`		18:19	Wakeup Pin pull configuration for WKUP2
`PWR_WKUPEPR_WKUPPUPD3`		20:21	Wakeup Pin pull configuration for WKUP3
`PWR_WKUPEPR_WKUPPUPD4`		22:23	Wakeup Pin pull configuration for WKUP4
`PWR_WKUPEPR_WKUPPUPD5`		24:25	Wakeup Pin pull configuration for WKUP5
`PWR_WKUPEPR_WKUPPUPD6`		26:27	Wakeup Pin pull configuration for WKUP6

FLASH — Контроллер флеш-памяти (раздел 11)

Регистр	Смещение	Бит	Назначение
`ACR`	`0x00`	32	FLASH access control register
`FLASH_ACR_LATENCY`		0:3	Read Latency
`FLASH_ACR_WRHIGHFREQ`		4:5	Flash signal delay
`KEYR1`	`0x04`	32	Flash Key Register for bank1
`OPTKEYR`	`0x08`	32	Flash Option Key Register
`CR1`	`0x0C`	32	Flash Control Register for bank1
`SR1`	`0x10`	32	Flash Status Register for bank1
`CCR1`	`0x14`	32	Flash Control Register for bank1
`OPTCR`	`0x18`	32	Flash Option Control Register
`FLASH_OPTCR_OPTLOCK`		0	FLASH_OPTCR lock option configuration bit
`FLASH_OPTCR_OPTSTART`		1	Option byte start change option configuration bit
`FLASH_OPTCR_MER`		4	Mass erase request
`FLASH_OPTCR_OPTCHANGEERRIE`		30	Option byte change error interrupt enable bit
`FLASH_OPTCR_SWAP_BANK`		31	Bank swapping option configuration bit
`OPTSR_CUR`	`0x1C`	32	Flash Option Status Current Register
`OPTSR_PRG`	`0x20`	32	Flash Option Status to Program Register
`OPTCCR`	`0x24`	32	Flash Option Clear Control Register
`FLASH_OPTCCR_CLR_OPTCHANGEERR`		30	OPTCHANGEERR reset bit
`PRAR_CUR1`	`0x28`	32	Flash Current Protection Address Register for bank1
`PRAR_PRG1`	`0x2C`	32	Flash Protection Address to Program Register for bank1
`SCAR_CUR1`	`0x30`	32	Flash Current Secure Address Register for bank1
`SCAR_PRG1`	`0x34`	32	Flash Secure Address to Program Register for bank1
`WPSN_CUR1`	`0x38`	32	Flash Current Write Protection Register on bank1
`WPSN_PRG1`	`0x3C`	32	Flash Write Protection to Program Register on bank1
`BOOT_CUR`	`0x40`	32	Flash Current Boot Address for Pelican Core Register
`BOOT_PRG`	`0x44`	32	Flash Boot Address to Program for Pelican Core Register
`CRCCR1`	`0x50`	32	Flash CRC Control register For Bank1 Register
`CRCSADD1`	`0x54`	32	Flash CRC Start Address Register for Bank1
`CRCEADD1`	`0x58`	32	Flash CRC End Address Register for Bank1
`CRCDATA`	`0x5C`	32	Flash CRC Data Register for Bank1
`FLASH_CRCDATA_CRC_DATA`		0:31	CRC result
`ECC_FA1`	`0x60`	32	Flash ECC Fail Address For Bank1 Register
`KEYR2`	`0x104`	32	Flash Key Register for bank2
`CR2`	`0x10C`	32	Flash Control Register for bank2
`SR2`	`0x110`	32	Flash Status Register for bank2
`CCR2`	`0x114`	32	Flash Status Register for bank2
`PRAR_CUR2`	`0x128`	32	Flash Current Protection Address Register for bank2
`PRAR_PRG2`	`0x12C`	32	Flash Protection Address to Program Register for bank2
`SCAR_CUR2`	`0x130`	32	Flash Current Secure Address Register for bank2
`SCAR_PRG2`	`0x134`	32	Flash Secure Address Register for bank2
`WPSN_CUR2`	`0x138`	32	Flash Current Write Protection Register on bank2
`WPSN_PRG2`	`0x13C`	32	Flash Write Protection to Program Register on bank2
`CRCCR2`	`0x150`	32	Flash CRC Control register For Bank2 Register
`CRCSADD2`	`0x154`	32	Flash CRC Start Address Register for Bank2
`CRCEADD2`	`0x158`	32	Flash CRC End Address Register for Bank2
`CRCDATA2`	`0x15C`	32	Flash CRC Data Register for Bank2
`ECC_FA2`	`0x160`	32	Flash ECC Fail Address For Bank2 Register

IWDG — Независимый сторож (раздел 12)

Регистр	Смещение	Бит	Назначение
`KR`	`0x00`	32	IWDG Key register
`IWDG_KR_KEY`		0:15	Key value (write only, read 0000h)
`PR`	`0x04`	32	IWDG Prescaler register
`IWDG_PR_PR`		0:2	PR[2:0] (Prescaler divider)
`RLR`	`0x08`	32	IWDG Reload register
`IWDG_RLR_RL`		0:11	Watchdog counter reload value
`SR`	`0x0C`	32	IWDG Status register
`IWDG_SR_PVU`		0	Watchdog prescaler value update
`IWDG_SR_RVU`		1	Watchdog counter reload value update
`IWDG_SR_WVU`		2	Watchdog counter window value update
`WINR`	`0x10`	32	IWDG Window register
`IWDG_WINR_WIN`		0:11	Watchdog counter window value

WWDG — Оконный сторож (раздел 12)

Регистр	Смещение	Бит	Назначение
`CR`	`0x00`	32	WWDG Control register
`WWDG_CR_T`		0:6	T[6:0] bits (7-Bit counter (MSB to LSB))
`WWDG_CR_WDGA`		7	Activation bit
`CFR`	`0x04`	32	WWDG Configuration register
`WWDG_CFR_W`		0:6	W[6:0] bits (7-bit window value)
`WWDG_CFR_EWI`		9	Early Wakeup Interrupt
`WWDG_CFR_WDGTB`		11:13	WDGTB[2:0] bits (Timer Base)
`SR`	`0x08`	32	WWDG Status register
`WWDG_SR_EWIF`		0	Early Wakeup Interrupt Flag

CRC — Контрольная сумма (раздел 12)

Регистр	Смещение	Бит	Назначение
`DR`	`0x00`	32	CRC Data register
`CRC_DR_DR`		0:31	Data register bits
`IDR`	`0x04`	32	CRC Independent data register
`CRC_IDR_IDR`		0:31	General-purpose 32-bit data register bits
`CR`	`0x08`	32	CRC Control register
`CRC_CR_RESET`		0	RESET the CRC computation unit bit
`CRC_CR_POLYSIZE`		3:4	Polynomial size bits
`CRC_CR_REV_IN`		5:6	REV_IN Reverse Input Data bits
`CRC_CR_REV_OUT`		7	REV_OUT Reverse Output Data bits
`INIT`	`0x10`	32	Initial CRC value register
`CRC_INIT_INIT`		0:31	Initial CRC value bits
`POL`	`0x14`	32	CRC polynomial register
`CRC_POL_POL`		0:31	Coefficients of the polynomial

RTC — Часы реального времени (раздел 12)

Регистр	Смещение	Бит	Назначение
`TR`	`0x00`	32	RTC time register
`RTC_TR_SU`		0:3
`RTC_TR_ST`		4:6
`RTC_TR_MNU`		8:11
`RTC_TR_MNT`		12:14
`RTC_TR_HU`		16:19
`RTC_TR_HT`		20:21
`RTC_TR_PM`		22
`DR`	`0x04`	32	RTC date register
`RTC_DR_DU`		0:3
`RTC_DR_DT`		4:5
`RTC_DR_MU`		8:11
`RTC_DR_MT`		12
`RTC_DR_WDU`		13:15
`RTC_DR_YU`		16:19
`RTC_DR_YT`		20:23
`CR`	`0x08`	32	RTC control register
`RTC_CR_WUCKSEL`		0:2
`RTC_CR_TSEDGE`		3
`RTC_CR_REFCKON`		4
`RTC_CR_BYPSHAD`		5
`RTC_CR_FMT`		6
`RTC_CR_ALRAE`		8
`RTC_CR_ALRBE`		9
`RTC_CR_WUTE`		10
`RTC_CR_TSE`		11
`RTC_CR_ALRAIE`		12
`RTC_CR_ALRBIE`		13
`RTC_CR_WUTIE`		14
`RTC_CR_TSIE`		15
`RTC_CR_ADD1H`		16
`RTC_CR_SUB1H`		17
`RTC_CR_BKP`		18
`RTC_CR_COSEL`		19
`RTC_CR_POL`		20
`RTC_CR_OSEL`		21:22
`RTC_CR_COE`		23
`RTC_CR_ITSE`		24
`ISR`	`0x0C`	32	RTC initialization and status register
`RTC_ISR_ALRAWF`		0
`RTC_ISR_ALRBWF`		1
`RTC_ISR_WUTWF`		2
`RTC_ISR_SHPF`		3
`RTC_ISR_INITS`		4
`RTC_ISR_RSF`		5
`RTC_ISR_INITF`		6
`RTC_ISR_INIT`		7
`RTC_ISR_ALRAF`		8
`RTC_ISR_ALRBF`		9
`RTC_ISR_WUTF`		10
`RTC_ISR_TSF`		11
`RTC_ISR_TSOVF`		12
`RTC_ISR_TAMP1F`		13
`RTC_ISR_TAMP2F`		14
`RTC_ISR_TAMP3F`		15
`RTC_ISR_RECALPF`		16
`RTC_ISR_ITSF`		17
`PRER`	`0x10`	32	RTC prescaler register
`RTC_PRER_PREDIV_S`		0:14
`RTC_PRER_PREDIV_A`		16:22
`WUTR`	`0x14`	32	RTC wakeup timer register
`RTC_WUTR_WUT`		0:15
`ALRMAR`	`0x1C`	32	RTC alarm A register
`RTC_ALRMAR_SU`		0:3
`RTC_ALRMAR_ST`		4:6
`RTC_ALRMAR_MSK1`		7
`RTC_ALRMAR_MNU`		8:11
`RTC_ALRMAR_MNT`		12:14
`RTC_ALRMAR_MSK2`		15
`RTC_ALRMAR_HU`		16:19
`RTC_ALRMAR_HT`		20:21
`RTC_ALRMAR_PM`		22
`RTC_ALRMAR_MSK3`		23
`RTC_ALRMAR_DU`		24:27
`RTC_ALRMAR_DT`		28:29
`RTC_ALRMAR_WDSEL`		30
`RTC_ALRMAR_MSK4`		31
`ALRMBR`	`0x20`	32	RTC alarm B register
`RTC_ALRMBR_SU`		0:3
`RTC_ALRMBR_ST`		4:6
`RTC_ALRMBR_MSK1`		7
`RTC_ALRMBR_MNU`		8:11
`RTC_ALRMBR_MNT`		12:14
`RTC_ALRMBR_MSK2`		15
`RTC_ALRMBR_HU`		16:19
`RTC_ALRMBR_HT`		20:21
`RTC_ALRMBR_PM`		22
`RTC_ALRMBR_MSK3`		23
`RTC_ALRMBR_DU`		24:27
`RTC_ALRMBR_DT`		28:29
`RTC_ALRMBR_WDSEL`		30
`RTC_ALRMBR_MSK4`		31
`WPR`	`0x24`	32	RTC write protection register
`RTC_WPR_KEY`		0:7
`SSR`	`0x28`	32	RTC sub second register
`RTC_SSR_SS`		0:15
`SHIFTR`	`0x2C`	32	RTC shift control register
`RTC_SHIFTR_SUBFS`		0:14
`RTC_SHIFTR_ADD1S`		31
`TSTR`	`0x30`	32	RTC time stamp time register
`RTC_TSTR_SU`		0:3
`RTC_TSTR_ST`		4:6
`RTC_TSTR_MNU`		8:11
`RTC_TSTR_MNT`		12:14
`RTC_TSTR_HU`		16:19
`RTC_TSTR_HT`		20:21
`RTC_TSTR_PM`		22
`TSDR`	`0x34`	32	RTC time stamp date register
`RTC_TSDR_DU`		0:3
`RTC_TSDR_DT`		4:5
`RTC_TSDR_MU`		8:11
`RTC_TSDR_MT`		12
`RTC_TSDR_WDU`		13:15
`TSSSR`	`0x38`	32	RTC time-stamp sub second register
`RTC_TSSSR_SS`		0:15
`CALR`	`0x3C`	32	RTC calibration register
`RTC_CALR_CALM`		0:8
`RTC_CALR_CALW16`		13
`RTC_CALR_CALW8`		14
`RTC_CALR_CALP`		15
`TAMPCR`	`0x40`	32	RTC tamper configuration register
`RTC_TAMPCR_TAMP1E`		0
`RTC_TAMPCR_TAMP1TRG`		1
`RTC_TAMPCR_TAMPIE`		2
`RTC_TAMPCR_TAMP2E`		3
`RTC_TAMPCR_TAMP2TRG`		4
`RTC_TAMPCR_TAMP3E`		5
`RTC_TAMPCR_TAMP3TRG`		6
`RTC_TAMPCR_TAMPTS`		7
`RTC_TAMPCR_TAMPFREQ`		8:10
`RTC_TAMPCR_TAMPFLT`		11:12
`RTC_TAMPCR_TAMPPRCH`		13:14
`RTC_TAMPCR_TAMPPUDIS`		15
`RTC_TAMPCR_TAMP1IE`		16
`RTC_TAMPCR_TAMP1NOERASE`		17
`RTC_TAMPCR_TAMP1MF`		18
`RTC_TAMPCR_TAMP2IE`		19
`RTC_TAMPCR_TAMP2NOERASE`		20
`RTC_TAMPCR_TAMP2MF`		21
`RTC_TAMPCR_TAMP3IE`		22
`RTC_TAMPCR_TAMP3NOERASE`		23
`RTC_TAMPCR_TAMP3MF`		24
`ALRMASSR`	`0x44`	32	RTC alarm A sub second register
`RTC_ALRMASSR_SS`		0:14
`RTC_ALRMASSR_MASKSS`		24:27
`ALRMBSSR`	`0x48`	32	RTC alarm B sub second register
`RTC_ALRMBSSR_SS`		0:14
`RTC_ALRMBSSR_MASKSS`		24:27
`OR`	`0x4C`	32	RTC option register
`RTC_OR_ALARMOUTTYPE`		0
`RTC_OR_OUT_RMP`		1
`BKP0R`	`0x50`	32	RTC backup register 0
`BKP1R`	`0x54`	32	RTC backup register 1
`BKP2R`	`0x58`	32	RTC backup register 2
`BKP3R`	`0x5C`	32	RTC backup register 3
`BKP4R`	`0x60`	32	RTC backup register 4
`BKP5R`	`0x64`	32	RTC backup register 5
`BKP6R`	`0x68`	32	RTC backup register 6
`BKP7R`	`0x6C`	32	RTC backup register 7
`BKP8R`	`0x70`	32	RTC backup register 8
`BKP9R`	`0x74`	32	RTC backup register 9
`BKP10R`	`0x78`	32	RTC backup register 10
`BKP11R`	`0x7C`	32	RTC backup register 11
`BKP12R`	`0x80`	32	RTC backup register 12
`BKP13R`	`0x84`	32	RTC backup register 13
`BKP14R`	`0x88`	32	RTC backup register 14
`BKP15R`	`0x8C`	32	RTC backup register 15
`BKP16R`	`0x90`	32	RTC backup register 16
`BKP17R`	`0x94`	32	RTC backup register 17
`BKP18R`	`0x98`	32	RTC backup register 18
`BKP19R`	`0x9C`	32	RTC backup register 19
`BKP20R`	`0xA0`	32	RTC backup register 20
`BKP21R`	`0xA4`	32	RTC backup register 21
`BKP22R`	`0xA8`	32	RTC backup register 22
`BKP23R`	`0xAC`	32	RTC backup register 23
`BKP24R`	`0xB0`	32	RTC backup register 24
`BKP25R`	`0xB4`	32	RTC backup register 25
`BKP26R`	`0xB8`	32	RTC backup register 26
`BKP27R`	`0xBC`	32	RTC backup register 27
`BKP28R`	`0xC0`	32	RTC backup register 28
`BKP29R`	`0xC4`	32	RTC backup register 29
`BKP30R`	`0xC8`	32	RTC backup register 30
`BKP31R`	`0xCC`	32	RTC backup register 31

TIM — Таймеры (раздел 13)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	TIM control register 1
`TIM_CR1_CEN`		0	Counter enable
`TIM_CR1_UDIS`		1	Update disable
`TIM_CR1_URS`		2	Update request source
`TIM_CR1_OPM`		3	One pulse mode
`TIM_CR1_DIR`		4	Direction
`TIM_CR1_CMS`		5:6	CMS[1:0] bits (Center-aligned mode selection)
`TIM_CR1_ARPE`		7	Auto-reload preload enable
`TIM_CR1_CKD`		8:9	CKD[1:0] bits (clock division)
`TIM_CR1_UIFREMAP`		11	Update interrupt flag remap
`CR2`	`0x04`	32	TIM control register 2
`TIM_CR2_CCPC`		0	Capture/Compare Preloaded Control
`TIM_CR2_CCUS`		2	Capture/Compare Control Update Selection
`TIM_CR2_CCDS`		3	Capture/Compare DMA Selection
`TIM_CR2_MMS`		4:6	MMS[2:0] bits (Master Mode Selection)
`TIM_CR2_TI1S`		7	TI1 Selection
`TIM_CR2_OIS1`		8	Output Idle state 1 (OC1 output)
`TIM_CR2_OIS1N`		9	Output Idle state 1 (OC1N output)
`TIM_CR2_OIS2`		10	Output Idle state 2 (OC2 output)
`TIM_CR2_OIS2N`		11	Output Idle state 2 (OC2N output)
`TIM_CR2_OIS3`		12	Output Idle state 3 (OC3 output)
`TIM_CR2_OIS3N`		13	Output Idle state 3 (OC3N output)
`TIM_CR2_OIS4`		14	Output Idle state 4 (OC4 output)
`TIM_CR2_OIS5`		16	Output Idle state 4 (OC4 output)
`TIM_CR2_OIS6`		18	Output Idle state 4 (OC4 output)
`TIM_CR2_MMS2`		20:23	MMS[2:0] bits (Master Mode Selection)
`SMCR`	`0x08`	32	TIM slave mode control register
`TIM_SMCR_SMS`		0:16	SMS[2:0] bits (Slave mode selection)
`TIM_SMCR_TS`		4:21	TS[4:0] bits (Trigger selection)
`TIM_SMCR_MSM`		7	Master/slave mode
`TIM_SMCR_ETF`		8:11	ETF[3:0] bits (External trigger filter)
`TIM_SMCR_ETPS`		12:13	ETPS[1:0] bits (External trigger prescaler)
`TIM_SMCR_ECE`		14	External clock enable
`TIM_SMCR_ETP`		15	External trigger polarity
`DIER`	`0x0C`	32	TIM DMA/interrupt enable register
`TIM_DIER_UIE`		0	Update interrupt enable
`TIM_DIER_CC1IE`		1	Capture/Compare 1 interrupt enable
`TIM_DIER_CC2IE`		2	Capture/Compare 2 interrupt enable
`TIM_DIER_CC3IE`		3	Capture/Compare 3 interrupt enable
`TIM_DIER_CC4IE`		4	Capture/Compare 4 interrupt enable
`TIM_DIER_COMIE`		5	COM interrupt enable
`TIM_DIER_TIE`		6	Trigger interrupt enable
`TIM_DIER_BIE`		7	Break interrupt enable
`TIM_DIER_UDE`		8	Update DMA request enable
`TIM_DIER_CC1DE`		9	Capture/Compare 1 DMA request enable
`TIM_DIER_CC2DE`		10	Capture/Compare 2 DMA request enable
`TIM_DIER_CC3DE`		11	Capture/Compare 3 DMA request enable
`TIM_DIER_CC4DE`		12	Capture/Compare 4 DMA request enable
`TIM_DIER_COMDE`		13	COM DMA request enable
`TIM_DIER_TDE`		14	Trigger DMA request enable
`SR`	`0x10`	32	TIM status register
`TIM_SR_UIF`		0	Update interrupt Flag
`TIM_SR_CC1IF`		1	Capture/Compare 1 interrupt Flag
`TIM_SR_CC2IF`		2	Capture/Compare 2 interrupt Flag
`TIM_SR_CC3IF`		3	Capture/Compare 3 interrupt Flag
`TIM_SR_CC4IF`		4	Capture/Compare 4 interrupt Flag
`TIM_SR_COMIF`		5	COM interrupt Flag
`TIM_SR_TIF`		6	Trigger interrupt Flag
`TIM_SR_BIF`		7	Break interrupt Flag
`TIM_SR_B2IF`		8	Break2 interrupt Flag
`TIM_SR_CC1OF`		9	Capture/Compare 1 Overcapture Flag
`TIM_SR_CC2OF`		10	Capture/Compare 2 Overcapture Flag
`TIM_SR_CC3OF`		11	Capture/Compare 3 Overcapture Flag
`TIM_SR_CC4OF`		12	Capture/Compare 4 Overcapture Flag
`TIM_SR_SBIF`		13	System Break Flag
`TIM_SR_CC5IF`		16	Capture/Compare 5 interrupt Flag
`TIM_SR_CC6IF`		17	Capture/Compare 6 interrupt Flag
`EGR`	`0x14`	32	TIM event generation register
`TIM_EGR_UG`		0	Update Generation
`TIM_EGR_CC1G`		1	Capture/Compare 1 Generation
`TIM_EGR_CC2G`		2	Capture/Compare 2 Generation
`TIM_EGR_CC3G`		3	Capture/Compare 3 Generation
`TIM_EGR_CC4G`		4	Capture/Compare 4 Generation
`TIM_EGR_COMG`		5	Capture/Compare Control Update Generation
`TIM_EGR_TG`		6	Trigger Generation
`TIM_EGR_BG`		7	Break Generation
`TIM_EGR_B2G`		8	Break Generation
`CCMR1`	`0x18`	32	TIM capture/compare mode register 1
`TIM_CCMR1_CC1S`		0:1	CC1S[1:0] bits (Capture/Compare 1 Selection)
`TIM_CCMR1_OC1FE`		2	Output Compare 1 Fast enable
`TIM_CCMR1_IC1PSC`		2:3	IC1PSC[1:0] bits (Input Capture 1 Prescaler)
`TIM_CCMR1_OC1PE`		3	Output Compare 1 Preload enable
`TIM_CCMR1_OC1M`		4:16	OC1M[2:0] bits (Output Compare 1 Mode)
`TIM_CCMR1_IC1F`		4:7	IC1F[3:0] bits (Input Capture 1 Filter)
`TIM_CCMR1_OC1CE`		7	Output Compare 1Clear Enable
`TIM_CCMR1_CC2S`		8:9	CC2S[1:0] bits (Capture/Compare 2 Selection)
`TIM_CCMR1_OC2FE`		10	Output Compare 2 Fast enable
`TIM_CCMR1_IC2PSC`		10:11	IC2PSC[1:0] bits (Input Capture 2 Prescaler)
`TIM_CCMR1_OC2PE`		11	Output Compare 2 Preload enable
`TIM_CCMR1_OC2M`		12:24	OC2M[2:0] bits (Output Compare 2 Mode)
`TIM_CCMR1_IC2F`		12:15	IC2F[3:0] bits (Input Capture 2 Filter)
`TIM_CCMR1_OC2CE`		15	Output Compare 2 Clear Enable
`CCMR2`	`0x1C`	32	TIM capture/compare mode register 2
`TIM_CCMR2_CC3S`		0:1	CC3S[1:0] bits (Capture/Compare 3 Selection)
`TIM_CCMR2_OC3FE`		2	Output Compare 3 Fast enable
`TIM_CCMR2_IC3PSC`		2:3	IC3PSC[1:0] bits (Input Capture 3 Prescaler)
`TIM_CCMR2_OC3PE`		3	Output Compare 3 Preload enable
`TIM_CCMR2_OC3M`		4:16	OC3M[3:0] bits (Output Compare 3 Mode)
`TIM_CCMR2_IC3F`		4:7	IC3F[3:0] bits (Input Capture 3 Filter)
`TIM_CCMR2_OC3CE`		7	Output Compare 3 Clear Enable
`TIM_CCMR2_CC4S`		8:9	CC4S[1:0] bits (Capture/Compare 4 Selection)
`TIM_CCMR2_OC4FE`		10	Output Compare 4 Fast enable
`TIM_CCMR2_IC4PSC`		10:11	IC4PSC[1:0] bits (Input Capture 4 Prescaler)
`TIM_CCMR2_OC4PE`		11	Output Compare 4 Preload enable
`TIM_CCMR2_OC4M`		12:24	OC4M[3:0] bits (Output Compare 4 Mode)
`TIM_CCMR2_IC4F`		12:15	IC4F[3:0] bits (Input Capture 4 Filter)
`TIM_CCMR2_OC4CE`		15	Output Compare 4 Clear Enable
`CCER`	`0x20`	32	TIM capture/compare enable register
`TIM_CCER_CC1E`		0	Capture/Compare 1 output enable
`TIM_CCER_CC1P`		1	Capture/Compare 1 output Polarity
`TIM_CCER_CC1NE`		2	Capture/Compare 1 Complementary output enable
`TIM_CCER_CC1NP`		3	Capture/Compare 1 Complementary output Polarity
`TIM_CCER_CC2E`		4	Capture/Compare 2 output enable
`TIM_CCER_CC2P`		5	Capture/Compare 2 output Polarity
`TIM_CCER_CC2NE`		6	Capture/Compare 2 Complementary output enable
`TIM_CCER_CC2NP`		7	Capture/Compare 2 Complementary output Polarity
`TIM_CCER_CC3E`		8	Capture/Compare 3 output enable
`TIM_CCER_CC3P`		9	Capture/Compare 3 output Polarity
`TIM_CCER_CC3NE`		10	Capture/Compare 3 Complementary output enable
`TIM_CCER_CC3NP`		11	Capture/Compare 3 Complementary output Polarity
`TIM_CCER_CC4E`		12	Capture/Compare 4 output enable
`TIM_CCER_CC4P`		13	Capture/Compare 4 output Polarity
`TIM_CCER_CC4NP`		15	Capture/Compare 4 Complementary output Polarity
`TIM_CCER_CC5E`		16	Capture/Compare 5 output enable
`TIM_CCER_CC5P`		17	Capture/Compare 5 output Polarity
`TIM_CCER_CC6E`		20	Capture/Compare 6 output enable
`TIM_CCER_CC6P`		21	Capture/Compare 6 output Polarity
`CNT`	`0x24`	32	TIM counter register
`TIM_CNT_CNT`		0:31	Counter Value
`TIM_CNT_UIFCPY`		31	Update interrupt flag copy
`PSC`	`0x28`	32	TIM prescaler
`TIM_PSC_PSC`		0:15	Prescaler Value
`ARR`	`0x2C`	32	TIM auto-reload register
`TIM_ARR_ARR`		0:31	actual auto-reload Value
`RCR`	`0x30`	32	TIM repetition counter register
`TIM_RCR_REP`		0:7	Repetition Counter Value
`CCR1`	`0x34`	32	TIM capture/compare register 1
`TIM_CCR1_CCR1`		0:15	Capture/Compare 1 Value
`CCR2`	`0x38`	32	TIM capture/compare register 2
`TIM_CCR2_CCR2`		0:15	Capture/Compare 2 Value
`CCR3`	`0x3C`	32	TIM capture/compare register 3
`TIM_CCR3_CCR3`		0:15	Capture/Compare 3 Value
`CCR4`	`0x40`	32	TIM capture/compare register 4
`TIM_CCR4_CCR4`		0:15	Capture/Compare 4 Value
`BDTR`	`0x44`	32	TIM break and dead-time register
`TIM_BDTR_DTG`		0:7	DTG[0:7] bits (Dead-Time Generator set-up)
`TIM_BDTR_LOCK`		8:9	LOCK[1:0] bits (Lock Configuration)
`TIM_BDTR_OSSI`		10	Off-State Selection for Idle mode
`TIM_BDTR_OSSR`		11	Off-State Selection for Run mode
`TIM_BDTR_BKE`		12	Break enable for Break1
`TIM_BDTR_BKP`		13	Break Polarity for Break1
`TIM_BDTR_AOE`		14	Automatic Output enable
`TIM_BDTR_MOE`		15	Main Output enable
`TIM_BDTR_BKF`		16:19	Break Filter for Break1
`TIM_BDTR_BK2F`		20:23	Break Filter for Break2
`TIM_BDTR_BK2E`		24	Break enable for Break2
`TIM_BDTR_BK2P`		25	Break Polarity for Break2
`DCR`	`0x48`	32	TIM DMA control register
`TIM_DCR_DBA`		0:4	DBA[4:0] bits (DMA Base Address)
`TIM_DCR_DBL`		8:12	DBL[4:0] bits (DMA Burst Length)
`DMAR`	`0x4C`	32	TIM DMA address for full transfer
`TIM_DMAR_DMAB`		0:15	DMA register for burst accesses
`CCMR3`	`0x54`	32	TIM capture/compare mode register 3
`TIM_CCMR3_OC5FE`		2	Output Compare 5 Fast enable
`TIM_CCMR3_OC5PE`		3	Output Compare 5 Preload enable
`TIM_CCMR3_OC5M`		4:16	OC5M[3:0] bits (Output Compare 5 Mode)
`TIM_CCMR3_OC5CE`		7	Output Compare 5 Clear Enable
`TIM_CCMR3_OC6FE`		10	Output Compare 4 Fast enable
`TIM_CCMR3_OC6PE`		11	Output Compare 4 Preload enable
`TIM_CCMR3_OC6M`		12:24	OC4M[3:0] bits (Output Compare 4 Mode)
`TIM_CCMR3_OC6CE`		15	Output Compare 4 Clear Enable
`CCR5`	`0x58`	32	TIM capture/compare register5
`TIM_CCR5_CCR5`		0:31	Capture/Compare 5 Value
`TIM_CCR5_GC5C1`		29	Group Channel 5 and Channel 1
`TIM_CCR5_GC5C2`		30	Group Channel 5 and Channel 2
`TIM_CCR5_GC5C3`		31	Group Channel 5 and Channel 3
`CCR6`	`0x5C`	32	TIM capture/compare register6
`TIM_CCR6_CCR6`		0:15	Capture/Compare 6 Value
`AF1`	`0x60`	32	TIM alternate function option register 1
`AF2`	`0x64`	32	TIM alternate function option register 2
`TISEL`	`0x68`	32	TIM Input Selection register
`TIM_TISEL_TI1SEL`		0:3	TI1SEL[3:0] bits (TIM TI1 SEL)
`TIM_TISEL_TI2SEL`		8:11	TI2SEL[3:0] bits (TIM TI2 SEL)
`TIM_TISEL_TI3SEL`		16:19	TI3SEL[3:0] bits (TIM TI3 SEL)
`TIM_TISEL_TI4SEL`		24:27	TI4SEL[3:0] bits (TIM TI4 SEL)

LPTIM — Таймер с малым потреблением (раздел 46)

Регистр	Смещение	Бит	Назначение
`ISR`	`0x00`	32	LPTIM Interrupt and Status register
`LPTIM_ISR_CMPM`		0	Compare match
`LPTIM_ISR_ARRM`		1	Autoreload match
`LPTIM_ISR_EXTTRIG`		2	External trigger edge event
`LPTIM_ISR_CMPOK`		3	Compare register update OK
`LPTIM_ISR_ARROK`		4	Autoreload register update OK
`LPTIM_ISR_UP`		5	Counter direction change down to up
`LPTIM_ISR_DOWN`		6	Counter direction change up to down
`ICR`	`0x04`	32	LPTIM Interrupt Clear register
`LPTIM_ICR_CMPMCF`		0	Compare match Clear Flag
`LPTIM_ICR_ARRMCF`		1	Autoreload match Clear Flag
`LPTIM_ICR_EXTTRIGCF`		2	External trigger edge event Clear Flag
`LPTIM_ICR_CMPOKCF`		3	Compare register update OK Clear Flag
`LPTIM_ICR_ARROKCF`		4	Autoreload register update OK Clear Flag
`LPTIM_ICR_UPCF`		5	Counter direction change down to up Clear Flag
`LPTIM_ICR_DOWNCF`		6	Counter direction change up to down Clear Flag
`IER`	`0x08`	32	LPTIM Interrupt Enable register
`LPTIM_IER_CMPMIE`		0	Compare match Interrupt Enable
`LPTIM_IER_ARRMIE`		1	Autoreload match Interrupt Enable
`LPTIM_IER_EXTTRIGIE`		2	External trigger edge event Interrupt Enable
`LPTIM_IER_CMPOKIE`		3	Compare register update OK Interrupt Enable
`LPTIM_IER_ARROKIE`		4	Autoreload register update OK Interrupt Enable
`LPTIM_IER_UPIE`		5	Counter direction change down to up Interrupt Enable
`LPTIM_IER_DOWNIE`		6	Counter direction change up to down Interrupt Enable
`CFGR`	`0x0C`	32	LPTIM Configuration register
`LPTIM_CFGR_CKSEL`		0	Clock selector
`LPTIM_CFGR_CKPOL`		1:2	CKPOL[1:0] bits (Clock polarity)
`LPTIM_CFGR_CKFLT`		3:4	CKFLT[1:0] bits (Configurable digital filter for external clock)
`LPTIM_CFGR_TRGFLT`		6:7	TRGFLT[1:0] bits (Configurable digital filter for trigger)
`LPTIM_CFGR_PRESC`		9:11	PRESC[2:0] bits (Clock prescaler)
`LPTIM_CFGR_TRIGSEL`		13:15	TRIGSEL[2:0]] bits (Trigger selector)
`LPTIM_CFGR_TRIGEN`		17:18	TRIGEN[1:0] bits (Trigger enable and polarity)
`LPTIM_CFGR_TIMOUT`		19	Timout enable
`LPTIM_CFGR_WAVE`		20	Waveform shape
`LPTIM_CFGR_WAVPOL`		21	Waveform shape polarity
`LPTIM_CFGR_PRELOAD`		22	Reg update mode
`LPTIM_CFGR_COUNTMODE`		23	Counter mode enable
`LPTIM_CFGR_ENC`		24	Encoder mode enable
`CR`	`0x10`	32	LPTIM Control register
`LPTIM_CR_ENABLE`		0	LPTIMer enable
`LPTIM_CR_SNGSTRT`		1:19	Timer start in single mode
`LPTIM_CR_CNTSTRT`		2	Timer start in continuous mode
`LPTIM_CR_COUNTRST`		3	Timer Counter reset in synchronous mode
`LPTIM_CR_RSTARE`		4	Timer Counter reset after read enable (asynchronously)
`CMP`	`0x14`	32	LPTIM Compare register
`LPTIM_CMP_CMP`		0:15	Compare register
`ARR`	`0x18`	32	LPTIM Autoreload register
`LPTIM_ARR_ARR`		0:15	Auto reload register
`CNT`	`0x1C`	32	LPTIM Counter register
`LPTIM_CNT_CNT`		0:15	Counter register
`CFGR2`	`0x24`	32	LPTIM Configuration register
`LPTIM_CFGR2_IN1SEL`		0:1	IN1SEL[1:0] bits (Remap selection)
`LPTIM_CFGR2_IN2SEL`		4:5	IN2SEL[5:4] bits (Remap selection)

ADC — АЦП (раздел 14)

Регистр	Смещение	Бит	Назначение
`ISR`	`0x00`	32	ADC Interrupt and Status Register
`ADC_ISR_ADRDY`		0	ADC Ready (ADRDY) flag
`ADC_ISR_EOSMP`		1	ADC End of Sampling flag
`ADC_ISR_EOC`		2	ADC End of Regular Conversion flag
`ADC_ISR_EOS`		3	ADC End of Regular sequence of Conversions flag
`ADC_ISR_OVR`		4	ADC overrun flag
`ADC_ISR_JEOC`		5	ADC End of Injected Conversion flag
`ADC_ISR_JEOS`		6	ADC End of Injected sequence of Conversions flag
`ADC_ISR_AWD1`		7	ADC Analog watchdog 1 flag
`ADC_ISR_AWD2`		8	ADC Analog watchdog 2 flag
`ADC_ISR_AWD3`		9	ADC Analog watchdog 3 flag
`ADC_ISR_JQOVF`		10	ADC Injected Context Queue Overflow flag
`ADC_ISR_LDORDY`		12	ADC LDO output voltage ready bit
`IER`	`0x04`	32	ADC Interrupt Enable Register
`ADC_IER_ADRDYIE`		0	ADC Ready (ADRDY) interrupt source
`ADC_IER_EOSMPIE`		1	ADC End of Sampling interrupt source
`ADC_IER_EOCIE`		2	ADC End of Regular Conversion interrupt source
`ADC_IER_EOSIE`		3	ADC End of Regular sequence of Conversions interrupt source
`ADC_IER_OVRIE`		4	ADC overrun interrupt source
`ADC_IER_JEOCIE`		5	ADC End of Injected Conversion interrupt source
`ADC_IER_JEOSIE`		6	ADC End of Injected sequence of Conversions interrupt source
`ADC_IER_AWD1IE`		7	ADC Analog watchdog 1 interrupt source
`ADC_IER_AWD2IE`		8	ADC Analog watchdog 2 interrupt source
`ADC_IER_AWD3IE`		9	ADC Analog watchdog 3 interrupt source
`ADC_IER_JQOVFIE`		10	ADC Injected Context Queue Overflow interrupt source
`CR`	`0x08`	32	ADC control register
`ADC_CR_ADEN`		0	ADC Enable control
`ADC_CR_ADDIS`		1	ADC Disable command
`ADC_CR_ADSTART`		2	ADC Start of Regular conversion
`ADC_CR_JADSTART`		3	ADC Start of injected conversion
`ADC_CR_ADSTP`		4	ADC Stop of Regular conversion
`ADC_CR_JADSTP`		5	ADC Stop of injected conversion
`ADC_CR_BOOST`		8:9	ADC Boost Mode configuration
`ADC_CR_ADCALLIN`		16	ADC Linearity calibration
`ADC_CR_LINCALRDYW1`		22	ADC Linearity calibration ready Word 1
`ADC_CR_LINCALRDYW2`		23	ADC Linearity calibration ready Word 2
`ADC_CR_LINCALRDYW3`		24	ADC Linearity calibration ready Word 3
`ADC_CR_LINCALRDYW4`		25	ADC Linearity calibration ready Word 4
`ADC_CR_LINCALRDYW5`		26	ADC Linearity calibration ready Word 5
`ADC_CR_LINCALRDYW6`		27	ADC Linearity calibration ready Word 6
`ADC_CR_ADVREGEN`		28	ADC Voltage regulator Enable
`ADC_CR_DEEPPWD`		29	ADC Deep power down Enable
`ADC_CR_ADCALDIF`		30	ADC Differential Mode for calibration
`ADC_CR_ADCAL`		31	ADC Calibration
`CFGR`	`0x0C`	32	ADC Configuration register
`ADC_CFGR_DMNGT`		0:1	ADC Data Management configuration
`ADC_CFGR_RES`		2:4	ADC Data resolution
`ADC_CFGR_EXTSEL`		5:9	ADC External trigger selection for regular group
`ADC_CFGR_EXTEN`		10:11	ADC External trigger enable and polarity selection for regular channels
`ADC_CFGR_OVRMOD`		12	ADC overrun mode
`ADC_CFGR_CONT`		13	ADC Single/continuous conversion mode for regular conversion
`ADC_CFGR_AUTDLY`		14	ADC Delayed conversion mode
`ADC_CFGR_DISCEN`		16	ADC Discontinuous mode for regular channels
`ADC_CFGR_DISCNUM`		17:19	ADC Discontinuous mode channel count
`ADC_CFGR_JDISCEN`		20	ADC Discontinuous mode on injected channels
`ADC_CFGR_JQM`		21	ADC JSQR Queue mode
`ADC_CFGR_AWD1SGL`		22	Enable the watchdog 1 on a single channel or on all channels
`ADC_CFGR_AWD1EN`		23	ADC Analog watchdog 1 enable on regular Channels
`ADC_CFGR_JAWD1EN`		24	ADC Analog watchdog 1 enable on injected Channels
`ADC_CFGR_JAUTO`		25	ADC Automatic injected group conversion
`ADC_CFGR_AWD1CH`		26:30	ADC Analog watchdog 1 Channel selection
`ADC_CFGR_JQDIS`		31	ADC Injected queue disable
`CFGR2`	`0x10`	32	ADC Configuration register 2
`ADC_CFGR2_ROVSE`		0	ADC Regular group oversampler enable
`ADC_CFGR2_JOVSE`		1	ADC Injected group oversampler enable
`ADC_CFGR2_OVSS`		5:8	ADC Regular Oversampling shift
`ADC_CFGR2_TROVS`		9	ADC Triggered regular Oversampling
`ADC_CFGR2_ROVSM`		10	ADC Regular oversampling mode
`ADC_CFGR2_RSHIFT1`		11	ADC Right-shift data after Offset 1 correction
`ADC_CFGR2_RSHIFT2`		12	ADC Right-shift data after Offset 2 correction
`ADC_CFGR2_RSHIFT3`		13	ADC Right-shift data after Offset 3 correction
`ADC_CFGR2_RSHIFT4`		14	ADC Right-shift data after Offset 4 correction
`ADC_CFGR2_OVSR`		16:25	ADC oversampling Ratio
`ADC_CFGR2_LSHIFT`		28:31	ADC Left shift factor
`SMPR1`	`0x14`	32	ADC sample time register 1
`ADC_SMPR1_SMP0`		0:2	ADC Channel 0 Sampling time selection
`ADC_SMPR1_SMP1`		3:5	ADC Channel 1 Sampling time selection
`ADC_SMPR1_SMP2`		6:8	ADC Channel 2 Sampling time selection
`ADC_SMPR1_SMP3`		9:11	ADC Channel 3 Sampling time selection
`ADC_SMPR1_SMP4`		12:14	ADC Channel 4 Sampling time selection
`ADC_SMPR1_SMP5`		15:17	ADC Channel 5 Sampling time selection
`ADC_SMPR1_SMP6`		18:20	ADC Channel 6 Sampling time selection
`ADC_SMPR1_SMP7`		21:23	ADC Channel 7 Sampling time selection
`ADC_SMPR1_SMP8`		24:26	ADC Channel 8 Sampling time selection
`ADC_SMPR1_SMP9`		27:29	ADC Channel 9 Sampling time selection
`SMPR2`	`0x18`	32	ADC sample time register 2
`ADC_SMPR2_SMP10`		0:2	ADC Channel 10 Sampling time selection
`ADC_SMPR2_SMP11`		3:5	ADC Channel 11 Sampling time selection
`ADC_SMPR2_SMP12`		6:8	ADC Channel 12 Sampling time selection
`ADC_SMPR2_SMP13`		9:11	ADC Channel 13 Sampling time selection
`ADC_SMPR2_SMP14`		12:14	ADC Channel 14 Sampling time selection
`ADC_SMPR2_SMP15`		15:17	ADC Channel 15 Sampling time selection
`ADC_SMPR2_SMP16`		18:20	ADC Channel 16 Sampling time selection
`ADC_SMPR2_SMP17`		21:23	ADC Channel 17 Sampling time selection
`ADC_SMPR2_SMP18`		24:26	ADC Channel 18 Sampling time selection
`ADC_SMPR2_SMP19`		27:29	ADC Channel 19 Sampling time selection
`PCSEL`	`0x1C`	32	ADC pre-channel selection
`ADC_PCSEL_PCSEL`		0:19	ADC pre channel selection
`LTR1`	`0x20`	32	ADC watchdog Lower threshold register 1
`HTR1`	`0x24`	32	ADC watchdog higher threshold register 1
`SQR1`	`0x30`	32	ADC regular sequence register 1
`ADC_SQR1_L`		0:3	ADC regular channel sequence length
`ADC_SQR1_SQ1`		6:10	ADC 1st conversion in regular sequence
`ADC_SQR1_SQ2`		12:16	ADC 2nd conversion in regular sequence
`ADC_SQR1_SQ3`		18:22	ADC 3rd conversion in regular sequence
`ADC_SQR1_SQ4`		24:28	ADC 4th conversion in regular sequence
`SQR2`	`0x34`	32	ADC regular sequence register 2
`ADC_SQR2_SQ5`		0:4	ADC 5th conversion in regular sequence
`ADC_SQR2_SQ6`		6:10	ADC 6th conversion in regular sequence
`ADC_SQR2_SQ7`		12:16	ADC 7th conversion in regular sequence
`ADC_SQR2_SQ8`		18:22	ADC 8th conversion in regular sequence
`ADC_SQR2_SQ9`		24:28	ADC 9th conversion in regular sequence
`SQR3`	`0x38`	32	ADC regular sequence register 3
`ADC_SQR3_SQ10`		0:4	ADC 10th conversion in regular sequence
`ADC_SQR3_SQ11`		6:10	ADC 11th conversion in regular sequence
`ADC_SQR3_SQ12`		12:16	ADC 12th conversion in regular sequence
`ADC_SQR3_SQ13`		18:22	ADC 13th conversion in regular sequence
`ADC_SQR3_SQ14`		24:28	ADC 14th conversion in regular sequence
`SQR4`	`0x3C`	32	ADC regular sequence register 4
`ADC_SQR4_SQ15`		0:4	ADC 15th conversion in regular sequence
`ADC_SQR4_SQ16`		6:10	ADC 16th conversion in regular sequence
`DR`	`0x40`	32	ADC regular data register
`ADC_DR_RDATA`		0:31	ADC regular Data converted
`JSQR`	`0x4C`	32	ADC injected sequence register
`ADC_JSQR_JL`		0:1	ADC injected channel sequence length
`ADC_JSQR_JEXTSEL`		2:6	ADC external trigger selection for injected group
`ADC_JSQR_JEXTEN`		7:8	ADC external trigger enable and polarity selection for injected channels
`ADC_JSQR_JSQ1`		9:13	ADC 1st conversion in injected sequence
`ADC_JSQR_JSQ2`		15:19	ADC 2nd conversion in injected sequence
`ADC_JSQR_JSQ3`		21:25	ADC 3rd conversion in injected sequence
`ADC_JSQR_JSQ4`		27:31	ADC 4th conversion in injected sequence
`OFR1`	`0x60`	32	ADC offset register 1
`ADC_OFR1_OFFSET1`		0:25	ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0]
`ADC_OFR1_OFFSET1_CH`		26:30	ADC Channel selection for the data offset 1
`ADC_OFR1_SSATE`		31	ADC Signed saturation Enable
`OFR2`	`0x64`	32	ADC offset register 2
`ADC_OFR2_OFFSET2`		0:25	ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0]
`ADC_OFR2_OFFSET2_CH`		26:30	ADC Channel selection for the data offset 2
`ADC_OFR2_SSATE`		31	ADC Signed saturation Enable
`OFR3`	`0x68`	32	ADC offset register 3
`ADC_OFR3_OFFSET3`		0:25	ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0]
`ADC_OFR3_OFFSET3_CH`		26:30	ADC Channel selection for the data offset 3
`ADC_OFR3_SSATE`		31	ADC Signed saturation Enable
`OFR4`	`0x6C`	32	ADC offset register 4
`ADC_OFR4_OFFSET4`		0:25	ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0]
`ADC_OFR4_OFFSET4_CH`		26:30	ADC Channel selection for the data offset 4
`ADC_OFR4_SSATE`		31	ADC Signed saturation Enable
`JDR1`	`0x80`	32	ADC injected data register 1
`ADC_JDR1_JDATA`		0:31	ADC Injected DATA
`JDR2`	`0x84`	32	ADC injected data register 2
`ADC_JDR2_JDATA`		0:31	ADC Injected DATA
`JDR3`	`0x88`	32	ADC injected data register 3
`ADC_JDR3_JDATA`		0:31	ADC Injected DATA
`JDR4`	`0x8C`	32	ADC injected data register 4
`ADC_JDR4_JDATA`		0:31	ADC Injected DATA
`AWD2CR`	`0xA0`	32	ADC Analog Watchdog 2 Configuration Register
`ADC_AWD2CR_AWD2CH`		0:19	ADC Analog watchdog 2 channel selection
`AWD3CR`	`0xA4`	32	ADC Analog Watchdog 3 Configuration Register
`ADC_AWD3CR_AWD3CH`		0:19	ADC Analog watchdog 2 channel selection
`LTR2`	`0xB0`	32	ADC watchdog Lower threshold register 2
`HTR2`	`0xB4`	32	ADC watchdog Higher threshold register 2
`LTR3`	`0xB8`	32	ADC watchdog Lower threshold register 3
`HTR3`	`0xBC`	32	ADC watchdog Higher threshold register 3
`DIFSEL`	`0xC0`	32	ADC Differential Mode Selection Register
`ADC_DIFSEL_DIFSEL`		0:19	ADC differential modes for channels 1 to 18
`CALFACT`	`0xC4`	32	ADC Calibration Factors
`ADC_CALFACT_CALFACT_S`		0:10	ADC calibration factors in single-ended mode
`ADC_CALFACT_CALFACT_D`		16:26	ADC calibration factors in differential mode
`CALFACT2`	`0xC8`	32	ADC Linearity Calibration Factors
`ADC_CALFACT2_LINCALFACT`		0:29	ADC Linearity calibration factors

ADC_Common — АЦП: общие регистры (раздел 14)

Регистр	Смещение	Бит	Назначение
`CSR`	`0x00`	32	ADC Common status register
`ADC_CSR_ADRDY_MST`		0	Master ADC ready
`ADC_CSR_EOSMP_MST`		1	End of sampling phase flag of the master ADC
`ADC_CSR_EOC_MST`		2	End of regular conversion of the master ADC
`ADC_CSR_EOS_MST`		3	End of regular sequence flag of the master ADC
`ADC_CSR_OVR_MST`		4	Overrun flag of the master ADC
`ADC_CSR_JEOC_MST`		5	End of injected conversion of the master ADC
`ADC_CSR_JEOS_MST`		6	End of injected sequence flag of the master ADC
`ADC_CSR_AWD1_MST`		7	Analog watchdog 1 flag of the master ADC
`ADC_CSR_AWD2_MST`		8	Analog watchdog 2 flag of the master ADC
`ADC_CSR_AWD3_MST`		9	Analog watchdog 3 flag of the master ADC
`ADC_CSR_JQOVF_MST`		10	Injected context queue overflow flag of the master ADC
`ADC_CSR_ADRDY_SLV`		16	Slave ADC ready
`ADC_CSR_EOSMP_SLV`		17	End of sampling phase flag of the slave ADC
`ADC_CSR_EOC_SLV`		18	End of regular conversion of the slave ADC
`ADC_CSR_EOS_SLV`		19	End of regular sequence flag of the slave ADC
`ADC_CSR_OVR_SLV`		20	Overrun flag of the slave ADC
`ADC_CSR_JEOC_SLV`		21	End of injected conversion of the slave ADC
`ADC_CSR_JEOS_SLV`		22	End of injected sequence flag of the slave ADC
`ADC_CSR_AWD1_SLV`		23	Analog watchdog 1 flag of the slave ADC
`ADC_CSR_AWD2_SLV`		24	Analog watchdog 2 flag of the slave ADC
`ADC_CSR_AWD3_SLV`		25	Analog watchdog 3 flag of the slave ADC
`ADC_CSR_JQOVF_SLV`		26	Injected context queue overflow flag of the slave ADC
`CCR`	`0x08`	32	ADC common control register
`ADC_CCR_DUAL`		0:4	Dual ADC mode selection
`ADC_CCR_DELAY`		8:11	Delay between 2 sampling phases
`ADC_CCR_DAMDF`		14:15	Dual ADC mode Data format
`ADC_CCR_CKMODE`		16:17	ADC clock mode
`ADC_CCR_PRESC`		18:21	ADC prescaler
`ADC_CCR_VREFEN`		22	VREFINT enable
`ADC_CCR_TSEN`		23	Temperature sensor enable
`ADC_CCR_VBATEN`		24	VBAT enable
`CDR`	`0x0C`	32	ADC common regular data register for dual
`ADC_CDR_RDATA_MST`		0:15	ADC multimode master group regular conversion data
`ADC_CDR_RDATA_SLV`		16:31	ADC multimode slave group regular conversion data
`CDR2`	`0x10`	32	ADC common regular data register for 32-bit dual mode
`ADC_CDR2_RDATA_ALT`		0:31	Regular data of the master/slave alternated ADCs

DAC — ЦАП (раздел 15)

Регистр	Смещение	Бит	Назначение
`CR`	`0x00`	32	DAC control register
`DAC_CR_EN1`		0	DAC channel1 enable
`DAC_CR_TEN1`		1	DAC channel1 Trigger enable
`DAC_CR_TSEL1`		2:5	TSEL1[2:0] (DAC channel1 Trigger selection)
`DAC_CR_WAVE1`		6:7	WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
`DAC_CR_MAMP1`		8:11	MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
`DAC_CR_DMAEN1`		12	DAC channel1 DMA enable
`DAC_CR_DMAUDRIE1`		13	DAC channel 1 DMA underrun interrupt enable >
`DAC_CR_CEN1`		14	DAC channel 1 calibration enable >
`DAC_CR_EN2`		16	DAC channel2 enable
`DAC_CR_TEN2`		17	DAC channel2 Trigger enable
`DAC_CR_TSEL2`		18:21	TSEL2[2:0] (DAC channel2 Trigger selection)
`DAC_CR_WAVE2`		22:23	WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)
`DAC_CR_MAMP2`		24:27	MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)
`DAC_CR_DMAEN2`		28	DAC channel2 DMA enabled
`DAC_CR_DMAUDRIE2`		29	DAC channel2 DMA underrun interrupt enable >
`DAC_CR_CEN2`		30	DAC channel2 calibration enable >
`SWTRIGR`	`0x04`	32	DAC software trigger register
`DAC_SWTRIGR_SWTRIG1`		0	DAC channel1 software trigger
`DAC_SWTRIGR_SWTRIG2`		1	DAC channel2 software trigger
`DHR12R1`	`0x08`	32	DAC channel1 12-bit right-aligned data holding register
`DAC_DHR12R1_DACC1DHR`		0:11	DAC channel1 12-bit Right aligned data
`DHR12L1`	`0x0C`	32	DAC channel1 12-bit left aligned data holding register
`DAC_DHR12L1_DACC1DHR`		4:15	DAC channel1 12-bit Left aligned data
`DHR8R1`	`0x10`	32	DAC channel1 8-bit right aligned data holding register
`DAC_DHR8R1_DACC1DHR`		0:7	DAC channel1 8-bit Right aligned data
`DHR12R2`	`0x14`	32	DAC channel2 12-bit right aligned data holding register
`DAC_DHR12R2_DACC2DHR`		0:11	DAC channel2 12-bit Right aligned data
`DHR12L2`	`0x18`	32	DAC channel2 12-bit left aligned data holding register
`DAC_DHR12L2_DACC2DHR`		4:15	DAC channel2 12-bit Left aligned data
`DHR8R2`	`0x1C`	32	DAC channel2 8-bit right-aligned data holding register
`DAC_DHR8R2_DACC2DHR`		0:7	DAC channel2 8-bit Right aligned data
`DHR12RD`	`0x20`	32	Dual DAC 12-bit right-aligned data holding register
`DAC_DHR12RD_DACC1DHR`		0:11	DAC channel1 12-bit Right aligned data
`DAC_DHR12RD_DACC2DHR`		16:27	DAC channel2 12-bit Right aligned data
`DHR12LD`	`0x24`	32	DUAL DAC 12-bit left aligned data holding register
`DAC_DHR12LD_DACC1DHR`		4:15	DAC channel1 12-bit Left aligned data
`DAC_DHR12LD_DACC2DHR`		20:31	DAC channel2 12-bit Left aligned data
`DHR8RD`	`0x28`	32	DUAL DAC 8-bit right aligned data holding register
`DAC_DHR8RD_DACC1DHR`		0:7	DAC channel1 8-bit Right aligned data
`DAC_DHR8RD_DACC2DHR`		8:15	DAC channel2 8-bit Right aligned data
`DOR1`	`0x2C`	32	DAC channel1 data output register
`DAC_DOR1_DACC1DOR`		0:11	DAC channel1 data output
`DOR2`	`0x30`	32	DAC channel2 data output register
`DAC_DOR2_DACC2DOR`		0:11	DAC channel2 data output
`SR`	`0x34`	32	DAC status register
`DAC_SR_DMAUDR1`		13	DAC channel1 DMA underrun flag
`DAC_SR_CAL_FLAG1`		14	DAC channel1 calibration offset status
`DAC_SR_BWST1`		15:29	DAC channel1 busy writing sample time flag
`DAC_SR_DMAUDR2`		29	DAC channel2 DMA underrun flag
`DAC_SR_CAL_FLAG2`		30	DAC channel2 calibration offset status
`DAC_SR_BWST2`		31	DAC channel2 busy writing sample time flag
`CCR`	`0x38`	32	DAC calibration control register
`DAC_CCR_OTRIM1`		0:4	DAC channel1 offset trimming value
`DAC_CCR_OTRIM2`		16:20	DAC channel2 offset trimming value
`MCR`	`0x3C`	32	DAC mode control register
`DAC_MCR_MODE1`		0:2	MODE1[2:0] (DAC channel1 mode)
`DAC_MCR_MODE2`		16:18	MODE2[2:0] (DAC channel2 mode)
`SHSR1`	`0x40`	32	DAC Sample and Hold sample time register 1
`DAC_SHSR1_TSAMPLE1`		0:9	DAC channel1 sample time
`SHSR2`	`0x44`	32	DAC Sample and Hold sample time register 2
`DAC_SHSR2_TSAMPLE2`		0:9	DAC channel2 sample time
`SHHR`	`0x48`	32	DAC Sample and Hold hold time register
`DAC_SHHR_THOLD1`		0:9	DAC channel1 hold time
`DAC_SHHR_THOLD2`		16:25	DAC channel2 hold time
`SHRR`	`0x4C`	32	DAC Sample and Hold refresh time register
`DAC_SHRR_TREFRESH1`		0:7	DAC channel1 refresh time
`DAC_SHRR_TREFRESH2`		16:23	DAC channel2 refresh time

COMP — Компаратор (раздел 44)

Регистр	Смещение	Бит	Назначение
`CFGR`	`0x00`	32	Comparator configuration register

OPAMP — Операционный усилитель (раздел 44)

Регистр	Смещение	Бит	Назначение
`CSR`	`0x00`	32	OPAMP control/status register
`OPAMP_CSR_OPAMPxEN`		0	OPAMP enable
`OPAMP_CSR_FORCEVP`		1	Force internal reference on VP
`OPAMP_CSR_VPSEL`		2:3	Non inverted input selection
`OPAMP_CSR_VMSEL`		5:6	Inverting input selection
`OPAMP_CSR_OPAHSM`		8	Operational amplifier high speed mode
`OPAMP_CSR_CALON`		11	Calibration mode enable
`OPAMP_CSR_CALSEL`		12:13	Calibration selection
`OPAMP_CSR_PGGAIN`		14:17	Operational amplifier Programmable amplifier gain value
`OPAMP_CSR_USERTRIM`		18	User trimming enable
`OPAMP_CSR_TSTREF`		29	OpAmp calibration reference voltage output control
`OPAMP_CSR_CALOUT`		30	Operational amplifier calibration output
`OTR`	`0x04`	32	OPAMP offset trimming register for normal mode
`OPAMP_OTR_TRIMOFFSETN`		0:4	Trim for NMOS differential pairs
`OPAMP_OTR_TRIMOFFSETP`		8:12	Trim for PMOS differential pairs
`HSOTR`	`0x08`	32	OPAMP offset trimming register for high speed mode
`OPAMP_HSOTR_TRIMHSOFFSETN`		0:4	Trim for NMOS differential pairs
`OPAMP_HSOTR_TRIMHSOFFSETP`		8:12	Trim for PMOS differential pairs

USART — UART / USART / LPUART (раздел 16)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	USART Control register 1
`USART_CR1_UE`		0	USART Enable
`USART_CR1_UESM`		1	USART Enable in STOP Mode
`USART_CR1_RE`		2	Receiver Enable
`USART_CR1_TE`		3	Transmitter Enable
`USART_CR1_IDLEIE`		4	IDLE Interrupt Enable
`USART_CR1_RXNEIE_RXFNEIE`		5	RXNE and RX FIFO Not Empty Interrupt Enable
`USART_CR1_TCIE`		6	Transmission Complete Interrupt Enable
`USART_CR1_TXEIE_TXFNFIE`		7	TXE and TX FIFO Not Full Interrupt Enable
`USART_CR1_PEIE`		8	PE Interrupt Enable
`USART_CR1_PS`		9	Parity Selection
`USART_CR1_PCE`		10	Parity Control Enable
`USART_CR1_WAKE`		11	Receiver Wakeup method
`USART_CR1_M`		12:28	Word length
`USART_CR1_M0`		12	Word length - Bit 0
`USART_CR1_MME`		13	Mute Mode Enable
`USART_CR1_CMIE`		14	Character match interrupt enable
`USART_CR1_OVER8`		15	Oversampling by 8-bit or 16-bit mode
`USART_CR1_DEDT`		16:20	DEDT[4:0] bits (Driver Enable Deassertion Time)
`USART_CR1_DEAT`		21:25	DEAT[4:0] bits (Driver Enable Assertion Time)
`USART_CR1_RTOIE`		26	Receive Time Out interrupt enable
`USART_CR1_EOBIE`		27	End of Block interrupt enable
`USART_CR1_M1`		28	Word length - Bit 1
`USART_CR1_FIFOEN`		29	FIFO mode enable
`USART_CR1_TXFEIE`		30	TXFIFO empty interrupt enable
`USART_CR1_RXFFIE`		31	RXFIFO Full interrupt enable
`CR2`	`0x04`	32	USART Control register 2
`USART_CR2_SLVEN`		0	Synchronous Slave mode Enable
`USART_CR2_DIS_NSS`		3	Negative Slave Select (NSS) pin management
`USART_CR2_ADDM7`		4	7-bit or 4-bit Address Detection
`USART_CR2_LBDL`		5	LIN Break Detection Length
`USART_CR2_LBDIE`		6	LIN Break Detection Interrupt Enable
`USART_CR2_LBCL`		8	Last Bit Clock pulse
`USART_CR2_CPHA`		9	Clock Phase
`USART_CR2_CPOL`		10	Clock Polarity
`USART_CR2_CLKEN`		11	Clock Enable
`USART_CR2_STOP`		12:13	STOP[1:0] bits (STOP bits)
`USART_CR2_LINEN`		14	LIN mode enable
`USART_CR2_SWAP`		15	SWAP TX/RX pins
`USART_CR2_RXINV`		16	RX pin active level inversion
`USART_CR2_TXINV`		17	TX pin active level inversion
`USART_CR2_DATAINV`		18	Binary data inversion
`USART_CR2_MSBFIRST`		19	Most Significant Bit First
`USART_CR2_ABREN`		20	Auto Baud-Rate Enable
`USART_CR2_ABRMODE`		21:22	ABRMOD[1:0] bits (Auto Baud-Rate Mode)
`USART_CR2_RTOEN`		23	Receiver Time-Out enable
`USART_CR2_ADD`		24:31	Address of the USART node
`CR3`	`0x08`	32	USART Control register 3
`USART_CR3_EIE`		0	Error Interrupt Enable
`USART_CR3_IREN`		1	IrDA mode Enable
`USART_CR3_IRLP`		2	IrDA Low-Power
`USART_CR3_HDSEL`		3	Half-Duplex Selection
`USART_CR3_NACK`		4	SmartCard NACK enable
`USART_CR3_SCEN`		5	SmartCard mode enable
`USART_CR3_DMAR`		6	DMA Enable Receiver
`USART_CR3_DMAT`		7	DMA Enable Transmitter
`USART_CR3_RTSE`		8	RTS Enable
`USART_CR3_CTSE`		9	CTS Enable
`USART_CR3_CTSIE`		10	CTS Interrupt Enable
`USART_CR3_ONEBIT`		11	One sample bit method enable
`USART_CR3_OVRDIS`		12	Overrun Disable
`USART_CR3_DDRE`		13	DMA Disable on Reception Error
`USART_CR3_DEM`		14	Driver Enable Mode
`USART_CR3_DEP`		15	Driver Enable Polarity Selection
`USART_CR3_SCARCNT`		17:19	SCARCNT[2:0] bits (SmartCard Auto-Retry Count)
`USART_CR3_WUS`		20:21	WUS[1:0] bits (Wake UP Interrupt Flag Selection)
`USART_CR3_WUFIE`		22	Wake Up Interrupt Enable
`USART_CR3_TXFTIE`		23	TXFIFO threshold interrupt enable
`USART_CR3_TCBGTIE`		24	Transmission Complete before guard time, interrupt enable
`USART_CR3_RXFTCFG`		25:27	RXFTCFG [2:0]Receive FIFO threshold configuration
`USART_CR3_RXFTIE`		28	RXFIFO threshold interrupt enable
`USART_CR3_TXFTCFG`		29:31	TXFIFO [2:0] threshold configuration
`BRR`	`0x0C`	32	USART Baud rate register
`USART_BRR_DIV_FRACTION`		0:3	Fraction of USARTDIV
`USART_BRR_DIV_MANTISSA`		4:15	Mantissa of USARTDIV
`GTPR`	`0x10`	32	USART Guard time and prescaler register
`USART_GTPR_PSC`		0:7	PSC[7:0] bits (Prescaler value)
`USART_GTPR_GT`		8:15	GT[7:0] bits (Guard time value)
`RTOR`	`0x14`	32	USART Receiver Time Out register
`USART_RTOR_RTO`		0:23	Receiver Time Out Value
`USART_RTOR_BLEN`		24:31	Block Length
`RQR`	`0x18`	32	USART Request register
`USART_RQR_ABRRQ`		0	Auto-Baud Rate Request
`USART_RQR_SBKRQ`		1	Send Break Request
`USART_RQR_MMRQ`		2	Mute Mode Request
`USART_RQR_RXFRQ`		3	Receive Data flush Request
`USART_RQR_TXFRQ`		4	Transmit data flush Request
`ISR`	`0x1C`	32	USART Interrupt and status register
`USART_ISR_PE`		0	Parity Error
`USART_ISR_FE`		1	Framing Error
`USART_ISR_NE`		2	Noise detected Flag
`USART_ISR_ORE`		3	OverRun Error
`USART_ISR_IDLE`		4	IDLE line detected
`USART_ISR_RXNE_RXFNE`		5	Read Data Register or RX FIFO Not Empty
`USART_ISR_TC`		6	Transmission Complete
`USART_ISR_TXE_TXFNF`		7	Transmit Data Register Empty or TX FIFO Not Full Flag
`USART_ISR_LBDF`		8	LIN Break Detection Flag
`USART_ISR_CTSIF`		9	CTS interrupt flag
`USART_ISR_CTS`		10	CTS flag
`USART_ISR_RTOF`		11	Receiver Time Out
`USART_ISR_EOBF`		12	End Of Block Flag
`USART_ISR_UDR`		13	SPI slave underrun error flag
`USART_ISR_ABRE`		14	Auto-Baud Rate Error
`USART_ISR_ABRF`		15	Auto-Baud Rate Flag
`USART_ISR_BUSY`		16	Busy Flag
`USART_ISR_CMF`		17	Character Match Flag
`USART_ISR_SBKF`		18	Send Break Flag
`USART_ISR_RWU`		19	Receive Wake Up from mute mode Flag
`USART_ISR_WUF`		20	Wake Up from stop mode Flag
`USART_ISR_TEACK`		21	Transmit Enable Acknowledge Flag
`USART_ISR_REACK`		22	Receive Enable Acknowledge Flag
`USART_ISR_TXFE`		23	TXFIFO Empty
`USART_ISR_RXFF`		24	RXFIFO Full Flag
`USART_ISR_TCBGT`		25	Transmission complete before guard time Flag
`USART_ISR_RXFT`		26	RXFIFO threshold Flag
`USART_ISR_TXFT`		27	TXFIFO threshold Flag
`ICR`	`0x20`	32	USART Interrupt flag Clear register
`USART_ICR_PECF`		0	Parity Error Clear Flag
`USART_ICR_FECF`		1	Framing Error Clear Flag
`USART_ICR_NECF`		2	Noise detected Clear Flag
`USART_ICR_ORECF`		3	OverRun Error Clear Flag
`USART_ICR_IDLECF`		4	IDLE line detected Clear Flag
`USART_ICR_TXFECF`		5	TXFIFO empty clear flag
`USART_ICR_TCCF`		6	Transmission Complete Clear Flag
`USART_ICR_TCBGTCF`		7	Transmission complete before guard time Clear Flag
`USART_ICR_LBDCF`		8	LIN Break Detection Clear Flag
`USART_ICR_CTSCF`		9	CTS Interrupt Clear Flag
`USART_ICR_RTOCF`		11	Receiver Time Out Clear Flag
`USART_ICR_EOBCF`		12	End Of Block Clear Flag
`USART_ICR_UDRCF`		13	SPI slave underrun clear flag
`USART_ICR_CMCF`		17	Character Match Clear Flag
`USART_ICR_WUCF`		20	Wake Up from stop mode Clear Flag
`RDR`	`0x24`	32	USART Receive Data register
`USART_RDR_RDR`		0:8	RDR[8:0] bits (Receive Data value)
`TDR`	`0x28`	32	USART Transmit Data register
`USART_TDR_TDR`		0:8	TDR[8:0] bits (Transmit Data value)
`PRESC`	`0x2C`	32	USART clock Prescaler register
`USART_PRESC_PRESCALER`		0:3	PRESCALER[3:0] bits (Clock prescaler)

I2C — I²C (раздел 17)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	I2C Control register 1
`I2C_CR1_PE`		0	Peripheral enable
`I2C_CR1_TXIE`		1	TX interrupt enable
`I2C_CR1_RXIE`		2	RX interrupt enable
`I2C_CR1_ADDRIE`		3	Address match interrupt enable
`I2C_CR1_NACKIE`		4	NACK received interrupt enable
`I2C_CR1_STOPIE`		5	STOP detection interrupt enable
`I2C_CR1_TCIE`		6	Transfer complete interrupt enable
`I2C_CR1_ERRIE`		7	Errors interrupt enable
`I2C_CR1_DNF`		8:11	Digital noise filter
`I2C_CR1_ANFOFF`		12	Analog noise filter OFF
`I2C_CR1_TXDMAEN`		14	DMA transmission requests enable
`I2C_CR1_RXDMAEN`		15	DMA reception requests enable
`I2C_CR1_SBC`		16	Slave byte control
`I2C_CR1_NOSTRETCH`		17	Clock stretching disable
`I2C_CR1_WUPEN`		18	Wakeup from STOP enable
`I2C_CR1_GCEN`		19	General call enable
`I2C_CR1_SMBHEN`		20	SMBus host address enable
`I2C_CR1_SMBDEN`		21	SMBus device default address enable
`I2C_CR1_ALERTEN`		22	SMBus alert enable
`I2C_CR1_PECEN`		23	PEC enable
`CR2`	`0x04`	32	I2C Control register 2
`I2C_CR2_SADD`		0:9	Slave address (master mode)
`I2C_CR2_RD_WRN`		10	Transfer direction (master mode)
`I2C_CR2_ADD10`		11	10-bit addressing mode (master mode)
`I2C_CR2_HEAD10R`		12	10-bit address header only read direction (master mode)
`I2C_CR2_START`		13	START generation
`I2C_CR2_STOP`		14	STOP generation (master mode)
`I2C_CR2_NACK`		15	NACK generation (slave mode)
`I2C_CR2_NBYTES`		16:23	Number of bytes
`I2C_CR2_RELOAD`		24	NBYTES reload mode
`I2C_CR2_AUTOEND`		25	Automatic end mode (master mode)
`I2C_CR2_PECBYTE`		26	Packet error checking byte
`OAR1`	`0x08`	32	I2C Own address 1 register
`I2C_OAR1_OA1`		0:9	Interface own address 1
`I2C_OAR1_OA1MODE`		10	Own address 1 10-bit mode
`I2C_OAR1_OA1EN`		15	Own address 1 enable
`OAR2`	`0x0C`	32	I2C Own address 2 register
`I2C_OAR2_OA2`		1:7	Interface own address 2
`I2C_OAR2_OA2MSK`		8:10	Own address 2 masks
`I2C_OAR2_OA2MASK01`		8	OA2[1] is masked, Only OA2[7:2] are compared
`I2C_OAR2_OA2MASK03`		8:9	OA2[3:1] is masked, Only OA2[7:4] are compared
`I2C_OAR2_OA2MASK05`		8:10	OA2[5:1] is masked, Only OA2[7:6] are compared
`I2C_OAR2_OA2MASK07`		8:10	OA2[7:1] is masked, No comparison is done
`I2C_OAR2_OA2MASK02`		9	OA2[2:1] is masked, Only OA2[7:3] are compared
`I2C_OAR2_OA2MASK06`		9:10	OA2[6:1] is masked, Only OA2[7] are compared
`I2C_OAR2_OA2MASK04`		10	OA2[4:1] is masked, Only OA2[7:5] are compared
`I2C_OAR2_OA2EN`		15	Own address 2 enable
`TIMINGR`	`0x10`	32	I2C Timing register
`I2C_TIMINGR_SCLL`		0:7	SCL low period (master mode)
`I2C_TIMINGR_SCLH`		8:15	SCL high period (master mode)
`I2C_TIMINGR_SDADEL`		16:19	Data hold time
`I2C_TIMINGR_SCLDEL`		20:23	Data setup time
`I2C_TIMINGR_PRESC`		28:31	Timings prescaler
`TIMEOUTR`	`0x14`	32	I2C Timeout register
`I2C_TIMEOUTR_TIMEOUTA`		0:11	Bus timeout A
`I2C_TIMEOUTR_TIDLE`		12	Idle clock timeout detection
`I2C_TIMEOUTR_TIMOUTEN`		15	Clock timeout enable
`I2C_TIMEOUTR_TIMEOUTB`		16:27	Bus timeout B
`I2C_TIMEOUTR_TEXTEN`		31	Extended clock timeout enable
`ISR`	`0x18`	32	I2C Interrupt and status register
`I2C_ISR_TXE`		0	Transmit data register empty
`I2C_ISR_TXIS`		1	Transmit interrupt status
`I2C_ISR_RXNE`		2	Receive data register not empty
`I2C_ISR_ADDR`		3	Address matched (slave mode)
`I2C_ISR_NACKF`		4	NACK received flag
`I2C_ISR_STOPF`		5	STOP detection flag
`I2C_ISR_TC`		6	Transfer complete (master mode)
`I2C_ISR_TCR`		7	Transfer complete reload
`I2C_ISR_BERR`		8	Bus error
`I2C_ISR_ARLO`		9	Arbitration lost
`I2C_ISR_OVR`		10	Overrun/Underrun
`I2C_ISR_PECERR`		11	PEC error in reception
`I2C_ISR_TIMEOUT`		12	Timeout or Tlow detection flag
`I2C_ISR_ALERT`		13	SMBus alert
`I2C_ISR_BUSY`		15	Bus busy
`I2C_ISR_DIR`		16	Transfer direction (slave mode)
`I2C_ISR_ADDCODE`		17:23	Address match code (slave mode)
`ICR`	`0x1C`	32	I2C Interrupt clear register
`I2C_ICR_ADDRCF`		3	Address matched clear flag
`I2C_ICR_NACKCF`		4	NACK clear flag
`I2C_ICR_STOPCF`		5	STOP detection clear flag
`I2C_ICR_BERRCF`		8	Bus error clear flag
`I2C_ICR_ARLOCF`		9	Arbitration lost clear flag
`I2C_ICR_OVRCF`		10	Overrun/Underrun clear flag
`I2C_ICR_PECCF`		11	PAC error clear flag
`I2C_ICR_TIMOUTCF`		12	Timeout clear flag
`I2C_ICR_ALERTCF`		13	Alert clear flag
`PECR`	`0x20`	32	I2C PEC register
`I2C_PECR_PEC`		0:7	PEC register
`RXDR`	`0x24`	32	I2C Receive data register
`I2C_RXDR_RXDATA`		0:7	8-bit receive data
`TXDR`	`0x28`	32	I2C Transmit data register
`I2C_TXDR_TXDATA`		0:7	8-bit transmit data

SPI — SPI / I²S (раздел 18)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	SPI/I2S Control register 1
`SPI_CR1_SPE`		0	Serial Peripheral Enable
`SPI_CR1_MASRX`		8	Master automatic SUSP in Receive mode
`SPI_CR1_CSTART`		9	Master transfer start
`SPI_CR1_CSUSP`		10	Master SUSPend request
`SPI_CR1_HDDIR`		11	Rx/Tx direction at Half-duplex mode
`SPI_CR1_SSI`		12	Internal SS signal input level
`SPI_CR1_CRC33_17`		13	32-bit CRC polynomial configuration
`SPI_CR1_RCRCINI`		14	CRC init pattern control for receiver
`SPI_CR1_TCRCINI`		15	CRC init pattern control for transmitter
`SPI_CR1_IOLOCK`		16	Locking the AF configuration of associated IOs
`CR2`	`0x04`	32	SPI Control register 2
`SPI_CR2_TSIZE`		0:15	Number of data at current transfer
`SPI_CR2_TSER`		16:31	Number of data transfer extension
`CFG1`	`0x08`	32	SPI Configuration register 1
`SPI_CFG1_DSIZE`		0:4	DSIZE[4:0]: Bits number in single SPI data frame
`SPI_CFG1_FTHLV`		5:8	FTHVL [3:0]: FIFO threshold level
`SPI_CFG1_UDRCFG`		9:10	UDRCFG[1:0]: Behavior of transmitter at underrun
`SPI_CFG1_UDRDET`		11:12	UDRDET[1:0]: Detection of underrun condition
`SPI_CFG1_RXDMAEN`		14	Rx DMA stream enable
`SPI_CFG1_TXDMAEN`		15	Tx DMA stream enable
`SPI_CFG1_CRCSIZE`		16:20	CRCSIZE [4:0]: Length of CRC frame
`SPI_CFG1_CRCEN`		22	Hardware CRC computation enable
`SPI_CFG1_MBR`		28:30	Master baud rate
`CFG2`	`0x0C`	32	SPI Configuration register 2
`SPI_CFG2_MSSI`		0:3	Master SS Idleness
`SPI_CFG2_MIDI`		4:7	Master Inter-Data Idleness
`SPI_CFG2_IOSWP`		15	Swap functionality of MISO and MOSI pins
`SPI_CFG2_COMM`		17:18	COMM [1:0]: SPI Communication Mode
`SPI_CFG2_SP`		19:21	SP[2:0]: Serial Protocol
`SPI_CFG2_MASTER`		22	SPI Master
`SPI_CFG2_LSBFRST`		23	Data frame format
`SPI_CFG2_CPHA`		24	Clock Phase
`SPI_CFG2_CPOL`		25	Clock Polarity
`SPI_CFG2_SSM`		26	Software slave management
`SPI_CFG2_SSIOP`		28	SS input/output polarity
`SPI_CFG2_SSOE`		29	SS output enable
`SPI_CFG2_SSOM`		30	SS output management in master mode
`SPI_CFG2_AFCNTR`		31	Alternate function GPIOs control
`IER`	`0x10`	32	SPI/I2S Interrupt Enable register
`SPI_IER_RXPIE`		0	RXP Interrupt Enable
`SPI_IER_TXPIE`		1	TXP interrupt enable
`SPI_IER_DXPIE`		2	DXP interrupt enable
`SPI_IER_EOTIE`		3	EOT/SUSP/TXC interrupt enable
`SPI_IER_TXTFIE`		4	TXTF interrupt enable
`SPI_IER_UDRIE`		5	UDR interrupt enable
`SPI_IER_OVRIE`		6	OVR interrupt enable
`SPI_IER_CRCEIE`		7	CRCE interrupt enable
`SPI_IER_TIFREIE`		8	TI Frame Error interrupt enable
`SPI_IER_MODFIE`		9	MODF interrupt enable
`SPI_IER_TSERFIE`		10	TSERF interrupt enable
`SR`	`0x14`	32	SPI/I2S Status register
`SPI_SR_RXP`		0	Rx-Packet available
`SPI_SR_TXP`		1	Tx-Packet space available
`SPI_SR_DXP`		2	Duplex Packet available
`SPI_SR_EOT`		3	Duplex Packet available
`SPI_SR_TXTF`		4	Transmission Transfer Filled
`SPI_SR_UDR`		5	UDR at Slave transmission
`SPI_SR_OVR`		6	Rx-Packet available
`SPI_SR_CRCE`		7	CRC Error Detected
`SPI_SR_TIFRE`		8	TI frame format error Detected
`SPI_SR_MODF`		9	Mode Fault Detected
`SPI_SR_TSERF`		10	Number of SPI data to be transacted reloaded
`SPI_SR_SUSP`		11	SUSP is set by hardware
`SPI_SR_TXC`		12	TxFIFO transmission complete
`SPI_SR_RXPLVL`		13:14	RxFIFO Packing Level
`SPI_SR_RXWNE`		15	Rx FIFO Word Not Empty
`SPI_SR_CTSIZE`		16:31	Number of data frames remaining in TSIZE
`IFCR`	`0x18`	32	SPI/I2S Interrupt/Status flags clear register
`SPI_IFCR_EOTC`		3	End Of Transfer flag clear
`SPI_IFCR_TXTFC`		4	Transmission Transfer Filled flag clear
`SPI_IFCR_UDRC`		5	Underrun flag clear
`SPI_IFCR_OVRC`		6	Overrun flag clear
`SPI_IFCR_CRCEC`		7	CRC Error flag clear
`SPI_IFCR_TIFREC`		8	TI frame format error flag clear
`SPI_IFCR_MODFC`		9	Mode Fault flag clear
`SPI_IFCR_TSERFC`		10	TSERFC flag clear
`SPI_IFCR_SUSPC`		11	SUSPend flag clear
`TXDR`	`0x20`	32	SPI/I2S Transmit data register
`SPI_TXDR_TXDR`		0:31
`RXDR`	`0x30`	32	SPI/I2S Receive data register
`SPI_RXDR_RXDR`		0:31
`CRCPOLY`	`0x40`	32	SPI CRC Polynomial register
`SPI_CRCPOLY_CRCPOLY`		0:31
`TXCRC`	`0x44`	32	SPI Transmitter CRC register
`SPI_TXCRC_TXCRC`		0:31
`RXCRC`	`0x48`	32	SPI Receiver CRC register
`SPI_RXCRC_RXCRC`		0:31
`UDRDR`	`0x4C`	32	SPI Underrun data register
`SPI_UDRDR_UDRDR`		0:31
`I2SCFGR`	`0x50`	32	I2S Configuration register
`SPI_I2SCFGR_I2SMOD`		0	I2S mode selection
`SPI_I2SCFGR_I2SCFG`		1:3	I2SCFG[2:0] I2S configuration mode
`SPI_I2SCFGR_I2SSTD`		4:5	I2SSTD[1:0] I2S standard selection
`SPI_I2SCFGR_PCMSYNC`		7	PCM frame synchronization
`SPI_I2SCFGR_DATLEN`		8:9	DATLEN[1:0] Data length to be transferred
`SPI_I2SCFGR_CHLEN`		10	Channel length (number of bits per audio channel)
`SPI_I2SCFGR_CKPOL`		11	Steady state clock polarity
`SPI_I2SCFGR_FIXCH`		12	Fixed channel length in SLAVE
`SPI_I2SCFGR_WSINV`		13	Word select inversion
`SPI_I2SCFGR_DATFMT`		14	Data format
`SPI_I2SCFGR_I2SDIV`		16:23	I2S Linear prescaler
`SPI_I2SCFGR_ODD`		24	Odd factor for the prescaler
`SPI_I2SCFGR_MCKOE`		25	Master Clock Output Enable

FDCAN — FDCAN (раздел 19)

Регистр	Смещение	Бит	Назначение
`CREL`	`0x00`	32	FDCAN Core Release register
`FDCAN_CREL_DAY`		0:7	Timestamp Day
`FDCAN_CREL_MON`		8:15	Timestamp Month
`FDCAN_CREL_YEAR`		16:19	Timestamp Year
`FDCAN_CREL_SUBSTEP`		20:23	Sub-step of Core release
`FDCAN_CREL_STEP`		24:27	Step of Core release
`FDCAN_CREL_REL`		28:31	Core release
`ENDN`	`0x04`	32	FDCAN Endian register
`FDCAN_ENDN_ETV`		0:31	Endianness Test Value
`DBTP`	`0x0C`	32	FDCAN Data Bit Timing & Prescaler register
`FDCAN_DBTP_DSJW`		0:3	Synchronization Jump Width
`FDCAN_DBTP_DTSEG2`		4:7	Data time segment after sample point
`FDCAN_DBTP_DTSEG1`		8:12	Data time segment before sample point
`FDCAN_DBTP_DBRP`		16:20	Data BIt Rate Prescaler
`FDCAN_DBTP_TDC`		23	Transceiver Delay Compensation
`TEST`	`0x10`	32	FDCAN Test register
`FDCAN_TEST_LBCK`		4	Loop Back mode
`FDCAN_TEST_TX`		5:6	Control of Transmit Pin
`FDCAN_TEST_RX`		7	Receive Pin
`RWD`	`0x14`	32	FDCAN RAM Watchdog register
`FDCAN_RWD_WDC`		0:7	Watchdog configuration
`FDCAN_RWD_WDV`		8:15	Watchdog value
`CCCR`	`0x18`	32	FDCAN CC Control register
`FDCAN_CCCR_INIT`		0	Initialization
`FDCAN_CCCR_CCE`		1	Configuration Change Enable
`FDCAN_CCCR_ASM`		2	ASM Restricted Operation Mode
`FDCAN_CCCR_CSA`		3	Clock Stop Acknowledge
`FDCAN_CCCR_CSR`		4	Clock Stop Request
`FDCAN_CCCR_MON`		5	Bus Monitoring Mode
`FDCAN_CCCR_DAR`		6	Disable Automatic Retransmission
`FDCAN_CCCR_TEST`		7	Test Mode Enable
`FDCAN_CCCR_FDOE`		8	FD Operation Enable
`FDCAN_CCCR_BRSE`		9	FDCAN Bit Rate Switching
`FDCAN_CCCR_PXHD`		12	Protocol Exception Handling Disable
`FDCAN_CCCR_EFBI`		13	Edge Filtering during Bus Integration
`FDCAN_CCCR_TXP`		14	Two CAN bit times Pause
`FDCAN_CCCR_NISO`		15	Non ISO Operation
`NBTP`	`0x1C`	32	FDCAN Nominal Bit Timing & Prescaler register
`FDCAN_NBTP_NTSEG2`		0:6	Nominal Time segment after sample point
`FDCAN_NBTP_NTSEG1`		8:15	Nominal Time segment before sample point
`FDCAN_NBTP_NBRP`		16:24	Bit Rate Prescaler
`FDCAN_NBTP_NSJW`		25:31	Nominal (Re)Synchronization Jump Width
`TSCC`	`0x20`	32	FDCAN Timestamp Counter Configuration register
`FDCAN_TSCC_TSS`		0:1	Timestamp Select
`FDCAN_TSCC_TCP`		16:19	Timestamp Counter Prescaler
`TSCV`	`0x24`	32	FDCAN Timestamp Counter Value register
`FDCAN_TSCV_TSC`		0:15	Timestamp Counter
`TOCC`	`0x28`	32	FDCAN Timeout Counter Configuration register
`FDCAN_TOCC_ETOC`		0	Enable Timeout Counter
`FDCAN_TOCC_TOS`		1:2	Timeout Select
`FDCAN_TOCC_TOP`		16:31	Timeout Period
`TOCV`	`0x2C`	32	FDCAN Timeout Counter Value register
`FDCAN_TOCV_TOC`		0:15	Timeout Counter
`ECR`	`0x40`	32	FDCAN Error Counter register
`FDCAN_ECR_TEC`		0:7	Transmit Error Counter
`FDCAN_ECR_REC`		8:14	Receive Error Counter
`FDCAN_ECR_RP`		15	Receive Error Passive
`FDCAN_ECR_CEL`		16:23	CAN Error Logging
`PSR`	`0x44`	32	FDCAN Protocol Status register
`FDCAN_PSR_LEC`		0:2	Last Error Code
`FDCAN_PSR_ACT`		3:4	Activity
`FDCAN_PSR_EP`		5	Error Passive
`FDCAN_PSR_EW`		6	Warning Status
`FDCAN_PSR_BO`		7	Bus_Off Status
`FDCAN_PSR_DLEC`		8:10	Data Last Error Code
`FDCAN_PSR_RESI`		11	ESI flag of last received FDCAN Message
`FDCAN_PSR_RBRS`		12	BRS flag of last received FDCAN Message
`FDCAN_PSR_REDL`		13	Received FDCAN Message
`FDCAN_PSR_PXE`		14	Protocol Exception Event
`FDCAN_PSR_TDCV`		16:22	Transmitter Delay Compensation Value
`TDCR`	`0x48`	32	FDCAN Transmitter Delay Compensation register
`FDCAN_TDCR_TDCF`		0:6	Transmitter Delay Compensation Filter
`FDCAN_TDCR_TDCO`		8:14	Transmitter Delay Compensation Offset
`IR`	`0x50`	32	FDCAN Interrupt register
`FDCAN_IR_RF0N`		0	Rx FIFO 0 New Message
`FDCAN_IR_RF0W`		1	Rx FIFO 0 Watermark Reached
`FDCAN_IR_RF0F`		2	Rx FIFO 0 Full
`FDCAN_IR_RF0L`		3	Rx FIFO 0 Message Lost
`FDCAN_IR_RF1N`		4	Rx FIFO 1 New Message
`FDCAN_IR_RF1W`		5	Rx FIFO 1 Watermark Reached
`FDCAN_IR_RF1F`		6	Rx FIFO 1 Full
`FDCAN_IR_RF1L`		7	Rx FIFO 1 Message Lost
`FDCAN_IR_HPM`		8	High Priority Message
`FDCAN_IR_TC`		9	Transmission Completed
`FDCAN_IR_TCF`		10	Transmission Cancellation Finished
`FDCAN_IR_TFE`		11	Tx FIFO Empty
`FDCAN_IR_TEFN`		12	Tx Event FIFO New Entry
`FDCAN_IR_TEFW`		13	Tx Event FIFO Watermark Reached
`FDCAN_IR_TEFF`		14	Tx Event FIFO Full
`FDCAN_IR_TEFL`		15	Tx Event FIFO Element Lost
`FDCAN_IR_TSW`		16	Timestamp Wraparound
`FDCAN_IR_MRAF`		17	Message RAM Access Failure
`FDCAN_IR_TOO`		18	Timeout Occurred
`FDCAN_IR_DRX`		19	Message stored to Dedicated Rx Buffer
`FDCAN_IR_ELO`		22	Error Logging Overflow
`FDCAN_IR_EP`		23	Error Passive
`FDCAN_IR_EW`		24	Warning Status
`FDCAN_IR_BO`		25	Bus_Off Status
`FDCAN_IR_WDI`		26	Watchdog Interrupt
`FDCAN_IR_PEA`		27	Protocol Error in Arbitration Phase
`FDCAN_IR_PED`		28	Protocol Error in Data Phase
`FDCAN_IR_ARA`		29	Access to Reserved Address
`IE`	`0x54`	32	FDCAN Interrupt Enable register
`FDCAN_IE_RF0NE`		0	Rx FIFO 0 New Message Enable
`FDCAN_IE_RF0WE`		1	Rx FIFO 0 Watermark Reached Enable
`FDCAN_IE_RF0FE`		2	Rx FIFO 0 Full Enable
`FDCAN_IE_RF0LE`		3	Rx FIFO 0 Message Lost Enable
`FDCAN_IE_RF1NE`		4	Rx FIFO 1 New Message Enable
`FDCAN_IE_RF1WE`		5	Rx FIFO 1 Watermark Reached Enable
`FDCAN_IE_RF1FE`		6	Rx FIFO 1 Full Enable
`FDCAN_IE_RF1LE`		7	Rx FIFO 1 Message Lost Enable
`FDCAN_IE_HPME`		8	High Priority Message Enable
`FDCAN_IE_TCE`		9	Transmission Completed Enable
`FDCAN_IE_TCFE`		10	Transmission Cancellation Finished Enable
`FDCAN_IE_TFEE`		11	Tx FIFO Empty Enable
`FDCAN_IE_TEFNE`		12	Tx Event FIFO New Entry Enable
`FDCAN_IE_TEFWE`		13	Tx Event FIFO Watermark Reached Enable
`FDCAN_IE_TEFFE`		14	Tx Event FIFO Full Enable
`FDCAN_IE_TEFLE`		15	Tx Event FIFO Element Lost Enable
`FDCAN_IE_TSWE`		16	Timestamp Wraparound Enable
`FDCAN_IE_MRAFE`		17	Message RAM Access Failure Enable
`FDCAN_IE_TOOE`		18	Timeout Occurred Enable
`FDCAN_IE_DRXE`		19	Message stored to Dedicated Rx Buffer Enable
`FDCAN_IE_BECE`		20	Bit Error Corrected Interrupt Enable
`FDCAN_IE_BEUE`		21	Bit Error Uncorrected Interrupt Enable
`FDCAN_IE_ELOE`		22	Error Logging Overflow Enable
`FDCAN_IE_EPE`		23	Error Passive Enable
`FDCAN_IE_EWE`		24	Warning Status Enable
`FDCAN_IE_BOE`		25	Bus_Off Status Enable
`FDCAN_IE_WDIE`		26	Watchdog Interrupt Enable
`FDCAN_IE_PEAE`		27	Protocol Error in Arbitration Phase Enable
`FDCAN_IE_PEDE`		28	Protocol Error in Data Phase Enable
`FDCAN_IE_ARAE`		29	Access to Reserved Address Enable
`ILS`	`0x58`	32	FDCAN Interrupt Line Select register
`FDCAN_ILS_RF0NL`		0	Rx FIFO 0 New Message Line
`FDCAN_ILS_RF0WL`		1	Rx FIFO 0 Watermark Reached Line
`FDCAN_ILS_RF0FL`		2	Rx FIFO 0 Full Line
`FDCAN_ILS_RF0LL`		3	Rx FIFO 0 Message Lost Line
`FDCAN_ILS_RF1NL`		4	Rx FIFO 1 New Message Line
`FDCAN_ILS_RF1WL`		5	Rx FIFO 1 Watermark Reached Line
`FDCAN_ILS_RF1FL`		6	Rx FIFO 1 Full Line
`FDCAN_ILS_RF1LL`		7	Rx FIFO 1 Message Lost Line
`FDCAN_ILS_HPML`		8	High Priority Message Line
`FDCAN_ILS_TCL`		9	Transmission Completed Line
`FDCAN_ILS_TCFL`		10	Transmission Cancellation Finished Line
`FDCAN_ILS_TFEL`		11	Tx FIFO Empty Line
`FDCAN_ILS_TEFNL`		12	Tx Event FIFO New Entry Line
`FDCAN_ILS_TEFWL`		13	Tx Event FIFO Watermark Reached Line
`FDCAN_ILS_TEFFL`		14	Tx Event FIFO Full Line
`FDCAN_ILS_TEFLL`		15	Tx Event FIFO Element Lost Line
`FDCAN_ILS_TSWL`		16	Timestamp Wraparound Line
`FDCAN_ILS_MRAFE`		17	Message RAM Access Failure Line
`FDCAN_ILS_TOOE`		18	Timeout Occurred Line
`FDCAN_ILS_DRXE`		19	Message stored to Dedicated Rx Buffer Line
`FDCAN_ILS_BECE`		20	Bit Error Corrected Interrupt Line
`FDCAN_ILS_BEUE`		21	Bit Error Uncorrected Interrupt Line
`FDCAN_ILS_ELOE`		22	Error Logging Overflow Line
`FDCAN_ILS_EPE`		23	Error Passive Line
`FDCAN_ILS_EWE`		24	Warning Status Line
`FDCAN_ILS_BOE`		25	Bus_Off Status Line
`FDCAN_ILS_WDIE`		26	Watchdog Interrupt Line
`FDCAN_ILS_PEAE`		27	Protocol Error in Arbitration Phase Line
`FDCAN_ILS_PEDE`		28	Protocol Error in Data Phase Line
`FDCAN_ILS_ARAE`		29	Access to Reserved Address Line
`ILE`	`0x5C`	32	FDCAN Interrupt Line Enable register
`FDCAN_ILE_EINT0`		0	Enable Interrupt Line 0
`FDCAN_ILE_EINT1`		1	Enable Interrupt Line 1
`GFC`	`0x80`	32	FDCAN Global Filter Configuration register
`FDCAN_GFC_RRFE`		0	Reject Remote Frames Extended
`FDCAN_GFC_RRFS`		1	Reject Remote Frames Standard
`FDCAN_GFC_ANFE`		2:3	Accept Non-matching Frames Extended
`FDCAN_GFC_ANFS`		4:5	Accept Non-matching Frames Standard
`SIDFC`	`0x84`	32	FDCAN Standard ID Filter Configuration register
`FDCAN_SIDFC_FLSSA`		2:15	Filter List Standard Start Address
`FDCAN_SIDFC_LSS`		16:23	List Size Standard
`XIDFC`	`0x88`	32	FDCAN Extended ID Filter Configuration register
`FDCAN_XIDFC_FLESA`		2:15	Filter List Standard Start Address
`FDCAN_XIDFC_LSE`		16:22	List Size Extended
`XIDAM`	`0x90`	32	FDCAN Extended ID AND Mask register
`FDCAN_XIDAM_EIDM`		0:28	Extended ID Mask
`HPMS`	`0x94`	32	FDCAN High Priority Message Status register
`FDCAN_HPMS_BIDX`		0:5	Buffer Index
`FDCAN_HPMS_MSI`		6:7	Message Storage Indicator
`FDCAN_HPMS_FIDX`		8:14	Filter Index
`FDCAN_HPMS_FLST`		15	Filter List
`NDAT1`	`0x98`	32	FDCAN New Data 1 register
`FDCAN_NDAT1_ND0`		0	New Data flag of Rx Buffer 0
`FDCAN_NDAT1_ND1`		1	New Data flag of Rx Buffer 1
`FDCAN_NDAT1_ND2`		2	New Data flag of Rx Buffer 2
`FDCAN_NDAT1_ND3`		3	New Data flag of Rx Buffer 3
`FDCAN_NDAT1_ND4`		4	New Data flag of Rx Buffer 4
`FDCAN_NDAT1_ND5`		5	New Data flag of Rx Buffer 5
`FDCAN_NDAT1_ND6`		6	New Data flag of Rx Buffer 6
`FDCAN_NDAT1_ND7`		7	New Data flag of Rx Buffer 7
`FDCAN_NDAT1_ND8`		8	New Data flag of Rx Buffer 8
`FDCAN_NDAT1_ND9`		9	New Data flag of Rx Buffer 9
`FDCAN_NDAT1_ND10`		10	New Data flag of Rx Buffer 10
`FDCAN_NDAT1_ND11`		11	New Data flag of Rx Buffer 11
`FDCAN_NDAT1_ND12`		12	New Data flag of Rx Buffer 12
`FDCAN_NDAT1_ND13`		13	New Data flag of Rx Buffer 13
`FDCAN_NDAT1_ND14`		14	New Data flag of Rx Buffer 14
`FDCAN_NDAT1_ND15`		15	New Data flag of Rx Buffer 15
`FDCAN_NDAT1_ND16`		16	New Data flag of Rx Buffer 16
`FDCAN_NDAT1_ND17`		17	New Data flag of Rx Buffer 17
`FDCAN_NDAT1_ND18`		18	New Data flag of Rx Buffer 18
`FDCAN_NDAT1_ND19`		19	New Data flag of Rx Buffer 19
`FDCAN_NDAT1_ND20`		20	New Data flag of Rx Buffer 20
`FDCAN_NDAT1_ND21`		21	New Data flag of Rx Buffer 21
`FDCAN_NDAT1_ND22`		22	New Data flag of Rx Buffer 22
`FDCAN_NDAT1_ND23`		23	New Data flag of Rx Buffer 23
`FDCAN_NDAT1_ND24`		24	New Data flag of Rx Buffer 24
`FDCAN_NDAT1_ND25`		25	New Data flag of Rx Buffer 25
`FDCAN_NDAT1_ND26`		26	New Data flag of Rx Buffer 26
`FDCAN_NDAT1_ND27`		27	New Data flag of Rx Buffer 27
`FDCAN_NDAT1_ND28`		28	New Data flag of Rx Buffer 28
`FDCAN_NDAT1_ND29`		29	New Data flag of Rx Buffer 29
`FDCAN_NDAT1_ND30`		30	New Data flag of Rx Buffer 30
`FDCAN_NDAT1_ND31`		31	New Data flag of Rx Buffer 31
`NDAT2`	`0x9C`	32	FDCAN New Data 2 register
`FDCAN_NDAT2_ND32`		0	New Data flag of Rx Buffer 32
`FDCAN_NDAT2_ND33`		1	New Data flag of Rx Buffer 33
`FDCAN_NDAT2_ND34`		2	New Data flag of Rx Buffer 34
`FDCAN_NDAT2_ND35`		3	New Data flag of Rx Buffer 35
`FDCAN_NDAT2_ND36`		4	New Data flag of Rx Buffer 36
`FDCAN_NDAT2_ND37`		5	New Data flag of Rx Buffer 37
`FDCAN_NDAT2_ND38`		6	New Data flag of Rx Buffer 38
`FDCAN_NDAT2_ND39`		7	New Data flag of Rx Buffer 39
`FDCAN_NDAT2_ND40`		8	New Data flag of Rx Buffer 40
`FDCAN_NDAT2_ND41`		9	New Data flag of Rx Buffer 41
`FDCAN_NDAT2_ND42`		10	New Data flag of Rx Buffer 42
`FDCAN_NDAT2_ND43`		11	New Data flag of Rx Buffer 43
`FDCAN_NDAT2_ND44`		12	New Data flag of Rx Buffer 44
`FDCAN_NDAT2_ND45`		13	New Data flag of Rx Buffer 45
`FDCAN_NDAT2_ND46`		14	New Data flag of Rx Buffer 46
`FDCAN_NDAT2_ND47`		15	New Data flag of Rx Buffer 47
`FDCAN_NDAT2_ND48`		16	New Data flag of Rx Buffer 48
`FDCAN_NDAT2_ND49`		17	New Data flag of Rx Buffer 49
`FDCAN_NDAT2_ND50`		18	New Data flag of Rx Buffer 50
`FDCAN_NDAT2_ND51`		19	New Data flag of Rx Buffer 51
`FDCAN_NDAT2_ND52`		20	New Data flag of Rx Buffer 52
`FDCAN_NDAT2_ND53`		21	New Data flag of Rx Buffer 53
`FDCAN_NDAT2_ND54`		22	New Data flag of Rx Buffer 54
`FDCAN_NDAT2_ND55`		23	New Data flag of Rx Buffer 55
`FDCAN_NDAT2_ND56`		24	New Data flag of Rx Buffer 56
`FDCAN_NDAT2_ND57`		25	New Data flag of Rx Buffer 57
`FDCAN_NDAT2_ND58`		26	New Data flag of Rx Buffer 58
`FDCAN_NDAT2_ND59`		27	New Data flag of Rx Buffer 59
`FDCAN_NDAT2_ND60`		28	New Data flag of Rx Buffer 60
`FDCAN_NDAT2_ND61`		29	New Data flag of Rx Buffer 61
`FDCAN_NDAT2_ND62`		30	New Data flag of Rx Buffer 62
`FDCAN_NDAT2_ND63`		31	New Data flag of Rx Buffer 63
`RXF0C`	`0xA0`	32	FDCAN Rx FIFO 0 Configuration register
`FDCAN_RXF0C_F0SA`		2:15	Rx FIFO 0 Start Address
`FDCAN_RXF0C_F0S`		16:22	Number of Rx FIFO 0 elements
`FDCAN_RXF0C_F0WM`		24:30	FIFO 0 Watermark
`FDCAN_RXF0C_F0OM`		31	FIFO 0 Operation Mode
`RXF0S`	`0xA4`	32	FDCAN Rx FIFO 0 Status register
`FDCAN_RXF0S_F0FL`		0:6	Rx FIFO 0 Fill Level
`FDCAN_RXF0S_F0GI`		8:13	Rx FIFO 0 Get Index
`FDCAN_RXF0S_F0PI`		16:21	Rx FIFO 0 Put Index
`FDCAN_RXF0S_F0F`		24	Rx FIFO 0 Full
`FDCAN_RXF0S_RF0L`		25	Rx FIFO 0 Message Lost
`RXF0A`	`0xA8`	32	FDCAN Rx FIFO 0 Acknowledge register
`FDCAN_RXF0A_F0AI`		0:5	Rx FIFO 0 Acknowledge Index
`RXBC`	`0xAC`	32	FDCAN Rx Buffer Configuration register
`FDCAN_RXBC_RBSA`		2:15	Rx Buffer Start Address
`RXF1C`	`0xB0`	32	FDCAN Rx FIFO 1 Configuration register
`FDCAN_RXF1C_F1SA`		2:15	Rx FIFO 1 Start Address
`FDCAN_RXF1C_F1S`		16:22	Number of Rx FIFO 1 elements
`FDCAN_RXF1C_F1WM`		24:30	Rx FIFO 1 Watermark
`FDCAN_RXF1C_F1OM`		31	FIFO 1 Operation Mode
`RXF1S`	`0xB4`	32	FDCAN Rx FIFO 1 Status register
`FDCAN_RXF1S_F1FL`		0:6	Rx FIFO 1 Fill Level
`FDCAN_RXF1S_F1GI`		8:13	Rx FIFO 1 Get Index
`FDCAN_RXF1S_F1PI`		16:21	Rx FIFO 1 Put Index
`FDCAN_RXF1S_F1F`		24	Rx FIFO 1 Full
`FDCAN_RXF1S_RF1L`		25	Rx FIFO 1 Message Lost
`RXF1A`	`0xB8`	32	FDCAN Rx FIFO 1 Acknowledge register
`FDCAN_RXF1A_F1AI`		0:5	Rx FIFO 1 Acknowledge Index
`RXESC`	`0xBC`	32	FDCAN Rx Buffer/FIFO Element Size Configuration register
`FDCAN_RXESC_F0DS`		0:2	Rx FIFO 1 Data Field Size
`FDCAN_RXESC_F1DS`		4:6	Rx FIFO 0 Data Field Size
`FDCAN_RXESC_RBDS`		8:10	Rx Buffer Data Field Size
`TXBC`	`0xC0`	32	FDCAN Tx Buffer Configuration register
`FDCAN_TXBC_TBSA`		2:15	Tx Buffers Start Address
`FDCAN_TXBC_NDTB`		16:21	Number of Dedicated Transmit Buffers
`FDCAN_TXBC_TFQS`		24:29	Transmit FIFO/Queue Size
`FDCAN_TXBC_TFQM`		30	Tx FIFO/Queue Mode
`TXFQS`	`0xC4`	32	FDCAN Tx FIFO/Queue Status register
`FDCAN_TXFQS_TFFL`		0:5	Tx FIFO Free Level
`FDCAN_TXFQS_TFGI`		8:12	Tx FIFO Get Index
`FDCAN_TXFQS_TFQPI`		16:20	Tx FIFO/Queue Put Index
`FDCAN_TXFQS_TFQF`		21	Tx FIFO/Queue Full
`TXESC`	`0xC8`	32	FDCAN Tx Buffer Element Size Configuration register
`FDCAN_TXESC_TBDS`		0:2	Tx Buffer Data Field Size
`TXBRP`	`0xCC`	32	FDCAN Tx Buffer Request Pending register
`FDCAN_TXBRP_TRP`		0:31	Transmission Request Pending
`TXBAR`	`0xD0`	32	FDCAN Tx Buffer Add Request register
`FDCAN_TXBAR_AR`		0:31	Add Request
`TXBCR`	`0xD4`	32	FDCAN Tx Buffer Cancellation Request register
`FDCAN_TXBCR_CR`		0:31	Cancellation Request
`TXBTO`	`0xD8`	32	FDCAN Tx Buffer Transmission Occurred register
`FDCAN_TXBTO_TO`		0:31	Transmission Occurred
`TXBCF`	`0xDC`	32	FDCAN Tx Buffer Cancellation Finished register
`FDCAN_TXBCF_CF`		0:31	Cancellation Finished
`TXBTIE`	`0xE0`	32	FDCAN Tx Buffer Transmission Interrupt Enable register
`FDCAN_TXBTIE_TIE`		0:31	Transmission Interrupt Enable
`TXBCIE`	`0xE4`	32	FDCAN Tx Buffer Cancellation Finished Interrupt Enable register
`FDCAN_TXBCIE_CFIE`		0:31	Cancellation Finished Interrupt Enable
`TXEFC`	`0xF0`	32	FDCAN Tx Event FIFO Configuration register
`FDCAN_TXEFC_EFSA`		2:15	Event FIFO Start Address
`FDCAN_TXEFC_EFS`		16:21	Event FIFO Size
`FDCAN_TXEFC_EFWM`		24:29	Event FIFO Watermark
`TXEFS`	`0xF4`	32	FDCAN Tx Event FIFO Status register
`FDCAN_TXEFS_EFFL`		0:5	Event FIFO Fill Level
`FDCAN_TXEFS_EFGI`		8:12	Event FIFO Get Index
`FDCAN_TXEFS_EFPI`		16:20	Event FIFO Put Index
`FDCAN_TXEFS_EFF`		24	Event FIFO Full
`FDCAN_TXEFS_TEFL`		25	Tx Event FIFO Element Lost
`TXEFA`	`0xF8`	32	FDCAN Tx Event FIFO Acknowledge register
`FDCAN_TXEFA_EFAI`		0:4	Event FIFO Acknowledge Index

USB_OTG — USB OTG: глобальные регистры (раздел 20)

Регистр	Смещение	Бит	Назначение
`GOTGCTL`	`0x00`	32	USB_OTG Control and Status Register 000h
`USB_OTG_GOTGCTL_SRQSCS`		0	Session request success
`USB_OTG_GOTGCTL_SRQ`		1	Session request
`USB_OTG_GOTGCTL_VBVALOEN`		2	VBUS valid override enable
`USB_OTG_GOTGCTL_VBVALOVAL`		3	VBUS valid override value
`USB_OTG_GOTGCTL_AVALOEN`		4	A-peripheral session valid override enable
`USB_OTG_GOTGCTL_AVALOVAL`		5	A-peripheral session valid override value
`USB_OTG_GOTGCTL_BVALOEN`		6	B-peripheral session valid override enable
`USB_OTG_GOTGCTL_BVALOVAL`		7	B-peripheral session valid override value
`USB_OTG_GOTGCTL_HNGSCS`		8	Host set HNP enable
`USB_OTG_GOTGCTL_HNPRQ`		9	HNP request
`USB_OTG_GOTGCTL_HSHNPEN`		10	Host set HNP enable
`USB_OTG_GOTGCTL_DHNPEN`		11	Device HNP enabled
`USB_OTG_GOTGCTL_EHEN`		12	Embedded host enable
`USB_OTG_GOTGCTL_CIDSTS`		16	Connector ID status
`USB_OTG_GOTGCTL_DBCT`		17	Long/short debounce time
`USB_OTG_GOTGCTL_ASVLD`		18	A-session valid
`USB_OTG_GOTGCTL_BSESVLD`		19	B-session valid
`USB_OTG_GOTGCTL_OTGVER`		20	OTG version
`GOTGINT`	`0x04`	32	USB_OTG Interrupt Register 004h
`USB_OTG_GOTGINT_SEDET`		2	Session end detected
`USB_OTG_GOTGINT_SRSSCHG`		8	Session request success status change
`USB_OTG_GOTGINT_HNSSCHG`		9	Host negotiation success status change
`USB_OTG_GOTGINT_HNGDET`		17	Host negotiation detected
`USB_OTG_GOTGINT_ADTOCHG`		18	A-device timeout change
`USB_OTG_GOTGINT_DBCDNE`		19	Debounce done
`GAHBCFG`	`0x08`	32	Core AHB Configuration Register 008h
`USB_OTG_GAHBCFG_GINT`		0	Global interrupt mask
`USB_OTG_GAHBCFG_HBSTLEN`		1:4	Burst length/type
`USB_OTG_GAHBCFG_DMAEN`		5	DMA enable
`USB_OTG_GAHBCFG_TXFELVL`		7	TxFIFO empty level
`USB_OTG_GAHBCFG_PTXFELVL`		8	Periodic TxFIFO empty level
`GUSBCFG`	`0x0C`	32	Core USB Configuration Register 00Ch
`USB_OTG_GUSBCFG_TOCAL`		0:2	FS timeout calibration
`USB_OTG_GUSBCFG_PHYSEL`		6	USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
`USB_OTG_GUSBCFG_SRPCAP`		8	SRP-capable
`USB_OTG_GUSBCFG_HNPCAP`		9	HNP-capable
`USB_OTG_GUSBCFG_TRDT`		10:13	USB turnaround time
`USB_OTG_GUSBCFG_PHYLPCS`		15	PHY Low-power clock select
`USB_OTG_GUSBCFG_ULPIFSLS`		17	ULPI FS/LS select
`USB_OTG_GUSBCFG_ULPIAR`		18	ULPI Auto-resume
`USB_OTG_GUSBCFG_ULPICSM`		19	ULPI Clock SuspendM
`USB_OTG_GUSBCFG_ULPIEVBUSD`		20	ULPI External VBUS Drive
`USB_OTG_GUSBCFG_ULPIEVBUSI`		21	ULPI external VBUS indicator
`USB_OTG_GUSBCFG_TSDPS`		22	TermSel DLine pulsing selection
`USB_OTG_GUSBCFG_PCCI`		23	Indicator complement
`USB_OTG_GUSBCFG_PTCI`		24	Indicator pass through
`USB_OTG_GUSBCFG_ULPIIPD`		25	ULPI interface protect disable
`USB_OTG_GUSBCFG_FHMOD`		29	Forced host mode
`USB_OTG_GUSBCFG_FDMOD`		30	Forced peripheral mode
`USB_OTG_GUSBCFG_CTXPKT`		31	Corrupt Tx packet
`GRSTCTL`	`0x10`	32	Core Reset Register 010h
`USB_OTG_GRSTCTL_CSRST`		0	Core soft reset
`USB_OTG_GRSTCTL_HSRST`		1	HCLK soft reset
`USB_OTG_GRSTCTL_FCRST`		2	Host frame counter reset
`USB_OTG_GRSTCTL_RXFFLSH`		4	RxFIFO flush
`USB_OTG_GRSTCTL_TXFFLSH`		5	TxFIFO flush
`USB_OTG_GRSTCTL_TXFNUM`		6:10	TxFIFO number
`USB_OTG_GRSTCTL_DMAREQ`		30	DMA request signal
`USB_OTG_GRSTCTL_AHBIDL`		31	AHB master idle
`GINTSTS`	`0x14`	32	Core Interrupt Register 014h
`USB_OTG_GINTSTS_CMOD`		0	Current mode of operation
`USB_OTG_GINTSTS_MMIS`		1	Mode mismatch interrupt
`USB_OTG_GINTSTS_OTGINT`		2	OTG interrupt
`USB_OTG_GINTSTS_SOF`		3	Start of frame
`USB_OTG_GINTSTS_RXFLVL`		4	RxFIFO nonempty
`USB_OTG_GINTSTS_NPTXFE`		5	Nonperiodic TxFIFO empty
`USB_OTG_GINTSTS_GINAKEFF`		6	Global IN nonperiodic NAK effective
`USB_OTG_GINTSTS_BOUTNAKEFF`		7	Global OUT NAK effective
`USB_OTG_GINTSTS_ESUSP`		10	Early suspend
`USB_OTG_GINTSTS_USBSUSP`		11	USB suspend
`USB_OTG_GINTSTS_USBRST`		12	USB reset
`USB_OTG_GINTSTS_ENUMDNE`		13	Enumeration done
`USB_OTG_GINTSTS_ISOODRP`		14	Isochronous OUT packet dropped interrupt
`USB_OTG_GINTSTS_EOPF`		15	End of periodic frame interrupt
`USB_OTG_GINTSTS_IEPINT`		18	IN endpoint interrupt
`USB_OTG_GINTSTS_OEPINT`		19	OUT endpoint interrupt
`USB_OTG_GINTSTS_IISOIXFR`		20	Incomplete isochronous IN transfer
`USB_OTG_GINTSTS_PXFR_INCOMPISOOUT`		21	Incomplete periodic transfer
`USB_OTG_GINTSTS_DATAFSUSP`		22	Data fetch suspended
`USB_OTG_GINTSTS_RSTDET`		23	Reset detected interrupt
`USB_OTG_GINTSTS_HPRTINT`		24	Host port interrupt
`USB_OTG_GINTSTS_HCINT`		25	Host channels interrupt
`USB_OTG_GINTSTS_PTXFE`		26	Periodic TxFIFO empty
`USB_OTG_GINTSTS_LPMINT`		27	LPM interrupt
`USB_OTG_GINTSTS_CIDSCHG`		28	Connector ID status change
`USB_OTG_GINTSTS_DISCINT`		29	Disconnect detected interrupt
`USB_OTG_GINTSTS_SRQINT`		30	Session request/new session detected interrupt
`USB_OTG_GINTSTS_WKUINT`		31	Resume/remote wakeup detected interrupt
`GINTMSK`	`0x18`	32	Core Interrupt Mask Register 018h
`USB_OTG_GINTMSK_MMISM`		1	Mode mismatch interrupt mask
`USB_OTG_GINTMSK_OTGINT`		2	OTG interrupt mask
`USB_OTG_GINTMSK_SOFM`		3	Start of frame mask
`USB_OTG_GINTMSK_RXFLVLM`		4	Receive FIFO nonempty mask
`USB_OTG_GINTMSK_NPTXFEM`		5	Nonperiodic TxFIFO empty mask
`USB_OTG_GINTMSK_GINAKEFFM`		6	Global nonperiodic IN NAK effective mask
`USB_OTG_GINTMSK_GONAKEFFM`		7	Global OUT NAK effective mask
`USB_OTG_GINTMSK_ESUSPM`		10	Early suspend mask
`USB_OTG_GINTMSK_USBSUSPM`		11	USB suspend mask
`USB_OTG_GINTMSK_USBRST`		12	USB reset mask
`USB_OTG_GINTMSK_ENUMDNEM`		13	Enumeration done mask
`USB_OTG_GINTMSK_ISOODRPM`		14	Isochronous OUT packet dropped interrupt mask
`USB_OTG_GINTMSK_EOPFM`		15	End of periodic frame interrupt mask
`USB_OTG_GINTMSK_EPMISM`		17	Endpoint mismatch interrupt mask
`USB_OTG_GINTMSK_IEPINT`		18	IN endpoints interrupt mask
`USB_OTG_GINTMSK_OEPINT`		19	OUT endpoints interrupt mask
`USB_OTG_GINTMSK_IISOIXFRM`		20	Incomplete isochronous IN transfer mask
`USB_OTG_GINTMSK_PXFRM_IISOOXFRM`		21	Incomplete periodic transfer mask
`USB_OTG_GINTMSK_FSUSPM`		22	Data fetch suspended mask
`USB_OTG_GINTMSK_RSTDEM`		23	Reset detected interrupt mask
`USB_OTG_GINTMSK_PRTIM`		24	Host port interrupt mask
`USB_OTG_GINTMSK_HCIM`		25	Host channels interrupt mask
`USB_OTG_GINTMSK_PTXFEM`		26	Periodic TxFIFO empty mask
`USB_OTG_GINTMSK_LPMINTM`		27	LPM interrupt Mask
`USB_OTG_GINTMSK_CIDSCHGM`		28	Connector ID status change mask
`USB_OTG_GINTMSK_DISCINT`		29	Disconnect detected interrupt mask
`USB_OTG_GINTMSK_SRQIM`		30	Session request/new session detected interrupt mask
`USB_OTG_GINTMSK_WUIM`		31	Resume/remote wakeup detected interrupt mask
`GRXSTSR`	`0x1C`	32	Receive Sts Q Read Register 01Ch
`GRXSTSP`	`0x20`	32	Receive Sts Q Read & POP Register 020h
`USB_OTG_GRXSTSP_EPNUM`		0:3	IN EP interrupt mask bits
`USB_OTG_GRXSTSP_BCNT`		4:14	OUT EP interrupt mask bits
`USB_OTG_GRXSTSP_DPID`		15:16	OUT EP interrupt mask bits
`USB_OTG_GRXSTSP_PKTSTS`		17:20	OUT EP interrupt mask bits
`GRXFSIZ`	`0x24`	32	Receive FIFO Size Register 024h
`USB_OTG_GRXFSIZ_RXFD`		0:15	RxFIFO depth
`DIEPTXF0_HNPTXFSIZ`	`0x28`	32	EP0 / Non Periodic Tx FIFO Size Register 028h
`HNPTXSTS`	`0x2C`	32	Non Periodic Tx FIFO/Queue Sts reg 02Ch
`GCCFG`	`0x38`	32	General Purpose IO Register 038h
`USB_OTG_GCCFG_DCDET`		0	Data contact detection (DCD) status
`USB_OTG_GCCFG_PDET`		1	Primary detection (PD) status
`USB_OTG_GCCFG_SDET`		2	Secondary detection (SD) status
`USB_OTG_GCCFG_PS2DET`		3	DM pull-up detection status
`USB_OTG_GCCFG_PWRDWN`		16	Power down
`USB_OTG_GCCFG_BCDEN`		17	Battery charging detector (BCD) enable
`USB_OTG_GCCFG_DCDEN`		18	Data contact detection (DCD) mode enable
`USB_OTG_GCCFG_PDEN`		19	Primary detection (PD) mode enable
`USB_OTG_GCCFG_SDEN`		20	Secondary detection (SD) mode enable
`USB_OTG_GCCFG_VBDEN`		21	Secondary detection (SD) mode enable
`CID`	`0x3C`	32	User ID Register 03Ch
`USB_OTG_CID_PRODUCT_ID`		0:31	Product ID field
`GSNPSID`	`0x40`	32
`GHWCFG1`	`0x44`	32
`GHWCFG2`	`0x48`	32
`GHWCFG3`	`0x4C`	32	User HW config3 04Ch
`GLPMCFG`	`0x54`	32	LPM Register 054h
`USB_OTG_GLPMCFG_LPMEN`		0	LPM support enable
`USB_OTG_GLPMCFG_LPMACK`		1	LPM Token acknowledge enable
`USB_OTG_GLPMCFG_BESL`		2:5	BESL value received with last ACKed LPM Token
`USB_OTG_GLPMCFG_REMWAKE`		6	bRemoteWake value received with last ACKed LPM Token
`USB_OTG_GLPMCFG_L1SSEN`		7	L1 shallow sleep enable
`USB_OTG_GLPMCFG_BESLTHRS`		8:11	BESL threshold
`USB_OTG_GLPMCFG_L1DSEN`		12	L1 deep sleep enable
`USB_OTG_GLPMCFG_LPMRSP`		13:14	LPM response
`USB_OTG_GLPMCFG_SLPSTS`		15	Port sleep status
`USB_OTG_GLPMCFG_L1RSMOK`		16	Sleep State Resume OK
`USB_OTG_GLPMCFG_LPMCHIDX`		17:20	LPM Channel Index
`USB_OTG_GLPMCFG_LPMRCNT`		21:23	LPM retry count
`USB_OTG_GLPMCFG_SNDLPM`		24	Send LPM transaction
`USB_OTG_GLPMCFG_LPMRCNTSTS`		25:27	LPM retry count status
`USB_OTG_GLPMCFG_ENBESL`		28	Enable best effort service latency
`GPWRDN`	`0x58`	32	Power Down Register 058h
`USB_OTG_GPWRDN_ADPMEN`		0	ADP module enable
`USB_OTG_GPWRDN_ADPIF`		23	ADP Interrupt flag
`GDFIFOCFG`	`0x5C`	32	DFIFO Software Config Register 05Ch
`GADPCTL`	`0x60`	32	ADP Timer, Control and Status Register 60Ch
`HPTXFSIZ`	`0x100`	32	Host Periodic Tx FIFO Size Reg 100h
`USB_OTG_HPTXFSIZ_PTXSA`		0:15	Host periodic TxFIFO start address
`USB_OTG_HPTXFSIZ_PTXFD`		16:31	Host periodic TxFIFO depth

Открыть в интерактивном справочнике