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STM32G474 · уровень справочник · 107 мин чтения
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Приложение A10. Карты регистров STM32G4

Серия STM32G4: Cortex-M4 до 170 МГц для силовой электроники: HRTIM, CORDIC, FDCAN. Регистры и биты основных блоков — из заголовка STM32G474, тем же генератором, что карты F1 и F4: смещения — по структурам *_TypeDef, назначение регистра и описание бита — из комментариев заголовка. Блоки, которых в серии нет, опущены. Разделы справочника написаны для F103 и F407; имена регистров и битов у серий в основном те же — карта помогает перенести код и увидеть, что устроено иначе.

Как читать: смещение — от базового адреса блока; 31:16 — поле битов с 16 по 31; одно число — отдельный бит. Цифра в скобках у заголовка блока — раздел, где блок разобран.

Периферия STM32G474 по шинам: базы шин и смещения блоков приложения, как в окне отладчика

RCC — Тактирование (раздел 6)

Регистр Смещение Бит Назначение
CR 0x00 32 RCC clock control register
RCC_CR_HSION 8 Internal High Speed oscillator (HSI16) clock enable
RCC_CR_HSIKERON 9 Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel
RCC_CR_HSIRDY 10 Internal High Speed oscillator (HSI16) clock ready flag
RCC_CR_HSEON 16 External High Speed oscillator (HSE) clock enable
RCC_CR_HSERDY 17 External High Speed oscillator (HSE) clock ready
RCC_CR_HSEBYP 18 External High Speed oscillator (HSE) clock bypass
RCC_CR_CSSON 19 HSE Clock Security System enable
RCC_CR_PLLON 24 System PLL clock enable
RCC_CR_PLLRDY 25 System PLL clock ready
ICSCR 0x04 32 RCC internal clock sources calibration register
RCC_ICSCR_HSICAL 16:23 HSICAL[7:0] bits
RCC_ICSCR_HSITRIM 24:30 HSITRIM[6:0] bits
CFGR 0x08 32 RCC clock configuration register
RCC_CFGR_SW 0:1 SW[1:0] bits (System clock Switch)
RCC_CFGR_SWS 2:3 SWS[1:0] bits (System Clock Switch Status)
RCC_CFGR_HPRE 4:7 HPRE[3:0] bits (AHB prescaler)
RCC_CFGR_PPRE1 8:10 PRE1[2:0] bits (APB2 prescaler)
RCC_CFGR_PPRE2 11:13 PRE2[2:0] bits (APB2 prescaler)
RCC_CFGR_MCOSEL 24:27 MCOSEL [3:0] bits (Clock output selection)
RCC_CFGR_MCOPRE 28:30 MCO prescaler
PLLCFGR 0x0C 32 RCC system PLL configuration register
RCC_PLLCFGR_PLLSRC 0:1
RCC_PLLCFGR_PLLSRC_HSE 0:1 HSE oscillator source clock selected
RCC_PLLCFGR_PLLSRC_HSI 1 HSI16 oscillator source clock selected
RCC_PLLCFGR_PLLM 4:7
RCC_PLLCFGR_PLLN 8:14
RCC_PLLCFGR_PLLPEN 16
RCC_PLLCFGR_PLLP 17
RCC_PLLCFGR_PLLQEN 20
RCC_PLLCFGR_PLLQ 21:22
RCC_PLLCFGR_PLLREN 24
RCC_PLLCFGR_PLLR 25:26
RCC_PLLCFGR_PLLPDIV 27:31
CIER 0x18 32 RCC clock interrupt enable register
RCC_CIER_LSIRDYIE 0
RCC_CIER_LSERDYIE 1
RCC_CIER_HSIRDYIE 3
RCC_CIER_HSERDYIE 4
RCC_CIER_PLLRDYIE 5
RCC_CIER_LSECSSIE 9
RCC_CIER_HSI48RDYIE 10
CIFR 0x1C 32 RCC clock interrupt flag register
RCC_CIFR_LSIRDYF 0
RCC_CIFR_LSERDYF 1
RCC_CIFR_HSIRDYF 3
RCC_CIFR_HSERDYF 4
RCC_CIFR_PLLRDYF 5
RCC_CIFR_CSSF 8
RCC_CIFR_LSECSSF 9
RCC_CIFR_HSI48RDYF 10
CICR 0x20 32 RCC clock interrupt clear register
RCC_CICR_LSIRDYC 0
RCC_CICR_LSERDYC 1
RCC_CICR_HSIRDYC 3
RCC_CICR_HSERDYC 4
RCC_CICR_PLLRDYC 5
RCC_CICR_CSSC 8
RCC_CICR_LSECSSC 9
RCC_CICR_HSI48RDYC 10
AHB1RSTR 0x28 32 RCC AHB1 peripheral reset register
RCC_AHB1RSTR_DMA1RST 0
RCC_AHB1RSTR_DMA2RST 1
RCC_AHB1RSTR_DMAMUX1RST 2
RCC_AHB1RSTR_CORDICRST 3
RCC_AHB1RSTR_FMACRST 4
RCC_AHB1RSTR_FLASHRST 8
RCC_AHB1RSTR_CRCRST 12
AHB2RSTR 0x2C 32 RCC AHB2 peripheral reset register
RCC_AHB2RSTR_GPIOARST 0
RCC_AHB2RSTR_GPIOBRST 1
RCC_AHB2RSTR_GPIOCRST 2
RCC_AHB2RSTR_GPIODRST 3
RCC_AHB2RSTR_GPIOERST 4
RCC_AHB2RSTR_GPIOFRST 5
RCC_AHB2RSTR_GPIOGRST 6
RCC_AHB2RSTR_ADC12RST 13
RCC_AHB2RSTR_ADC345RST 14
RCC_AHB2RSTR_DAC1RST 16
RCC_AHB2RSTR_DAC2RST 17
RCC_AHB2RSTR_DAC3RST 18
RCC_AHB2RSTR_DAC4RST 19
RCC_AHB2RSTR_RNGRST 26
AHB3RSTR 0x30 32 RCC AHB3 peripheral reset register
RCC_AHB3RSTR_FMCRST 0
RCC_AHB3RSTR_QSPIRST 8
APB1RSTR1 0x38 32 RCC APB1 peripheral reset register 1
RCC_APB1RSTR1_TIM2RST 0
RCC_APB1RSTR1_TIM3RST 1
RCC_APB1RSTR1_TIM4RST 2
RCC_APB1RSTR1_TIM5RST 3
RCC_APB1RSTR1_TIM6RST 4
RCC_APB1RSTR1_TIM7RST 5
RCC_APB1RSTR1_CRSRST 8
RCC_APB1RSTR1_SPI2RST 14
RCC_APB1RSTR1_SPI3RST 15
RCC_APB1RSTR1_USART2RST 17
RCC_APB1RSTR1_USART3RST 18
RCC_APB1RSTR1_UART4RST 19
RCC_APB1RSTR1_UART5RST 20
RCC_APB1RSTR1_I2C1RST 21
RCC_APB1RSTR1_I2C2RST 22
RCC_APB1RSTR1_USBRST 23
RCC_APB1RSTR1_FDCANRST 25
RCC_APB1RSTR1_PWRRST 28
RCC_APB1RSTR1_I2C3RST 30
RCC_APB1RSTR1_LPTIM1RST 31
APB1RSTR2 0x3C 32 RCC APB1 peripheral reset register 2
RCC_APB1RSTR2_LPUART1RST 0
RCC_APB1RSTR2_I2C4RST 1
RCC_APB1RSTR2_UCPD1RST 8
APB2RSTR 0x40 32 RCC APB2 peripheral reset register
RCC_APB2RSTR_SYSCFGRST 0
RCC_APB2RSTR_TIM1RST 11
RCC_APB2RSTR_SPI1RST 12
RCC_APB2RSTR_TIM8RST 13
RCC_APB2RSTR_USART1RST 14
RCC_APB2RSTR_SPI4RST 15
RCC_APB2RSTR_TIM15RST 16
RCC_APB2RSTR_TIM16RST 17
RCC_APB2RSTR_TIM17RST 18
RCC_APB2RSTR_TIM20RST 20
RCC_APB2RSTR_SAI1RST 21
RCC_APB2RSTR_HRTIM1RST 26
AHB1ENR 0x48 32 RCC AHB1 peripheral clocks enable register
RCC_AHB1ENR_DMA1EN 0
RCC_AHB1ENR_DMA2EN 1
RCC_AHB1ENR_DMAMUX1EN 2
RCC_AHB1ENR_CORDICEN 3
RCC_AHB1ENR_FMACEN 4
RCC_AHB1ENR_FLASHEN 8
RCC_AHB1ENR_CRCEN 12
AHB2ENR 0x4C 32 RCC AHB2 peripheral clocks enable register
RCC_AHB2ENR_GPIOAEN 0
RCC_AHB2ENR_GPIOBEN 1
RCC_AHB2ENR_GPIOCEN 2
RCC_AHB2ENR_GPIODEN 3
RCC_AHB2ENR_GPIOEEN 4
RCC_AHB2ENR_GPIOFEN 5
RCC_AHB2ENR_GPIOGEN 6
RCC_AHB2ENR_ADC12EN 13
RCC_AHB2ENR_ADC345EN 14
RCC_AHB2ENR_DAC1EN 16
RCC_AHB2ENR_DAC2EN 17
RCC_AHB2ENR_DAC3EN 18
RCC_AHB2ENR_DAC4EN 19
RCC_AHB2ENR_RNGEN 26
AHB3ENR 0x50 32 RCC AHB3 peripheral clocks enable register
RCC_AHB3ENR_FMCEN 0
RCC_AHB3ENR_QSPIEN 8
APB1ENR1 0x58 32 RCC APB1 peripheral clocks enable register 1
RCC_APB1ENR1_TIM2EN 0
RCC_APB1ENR1_TIM3EN 1
RCC_APB1ENR1_TIM4EN 2
RCC_APB1ENR1_TIM5EN 3
RCC_APB1ENR1_TIM6EN 4
RCC_APB1ENR1_TIM7EN 5
RCC_APB1ENR1_CRSEN 8
RCC_APB1ENR1_RTCAPBEN 10
RCC_APB1ENR1_WWDGEN 11
RCC_APB1ENR1_SPI2EN 14
RCC_APB1ENR1_SPI3EN 15
RCC_APB1ENR1_USART2EN 17
RCC_APB1ENR1_USART3EN 18
RCC_APB1ENR1_UART4EN 19
RCC_APB1ENR1_UART5EN 20
RCC_APB1ENR1_I2C1EN 21
RCC_APB1ENR1_I2C2EN 22
RCC_APB1ENR1_USBEN 23
RCC_APB1ENR1_FDCANEN 25
RCC_APB1ENR1_PWREN 28
RCC_APB1ENR1_I2C3EN 30
RCC_APB1ENR1_LPTIM1EN 31
APB1ENR2 0x5C 32 RCC APB1 peripheral clocks enable register 2
RCC_APB1ENR2_LPUART1EN 0
RCC_APB1ENR2_I2C4EN 1
RCC_APB1ENR2_UCPD1EN 8
APB2ENR 0x60 32 RCC APB2 peripheral clocks enable register
RCC_APB2ENR_SYSCFGEN 0
RCC_APB2ENR_TIM1EN 11
RCC_APB2ENR_SPI1EN 12
RCC_APB2ENR_TIM8EN 13
RCC_APB2ENR_USART1EN 14
RCC_APB2ENR_SPI4EN 15
RCC_APB2ENR_TIM15EN 16
RCC_APB2ENR_TIM16EN 17
RCC_APB2ENR_TIM17EN 18
RCC_APB2ENR_TIM20EN 20
RCC_APB2ENR_SAI1EN 21
RCC_APB2ENR_HRTIM1EN 26
AHB1SMENR 0x68 32 RCC AHB1 peripheral clocks enable in sleep and stop modes register
RCC_AHB1SMENR_DMA1SMEN 0
RCC_AHB1SMENR_DMA2SMEN 1
RCC_AHB1SMENR_DMAMUX1SMEN 2
RCC_AHB1SMENR_CORDICSMEN 3
RCC_AHB1SMENR_FMACSMEN 4
RCC_AHB1SMENR_FLASHSMEN 8
RCC_AHB1SMENR_SRAM1SMEN 9
RCC_AHB1SMENR_CRCSMEN 12
AHB2SMENR 0x6C 32 RCC AHB2 peripheral clocks enable in sleep and stop modes register
RCC_AHB2SMENR_GPIOASMEN 0
RCC_AHB2SMENR_GPIOBSMEN 1
RCC_AHB2SMENR_GPIOCSMEN 2
RCC_AHB2SMENR_GPIODSMEN 3
RCC_AHB2SMENR_GPIOESMEN 4
RCC_AHB2SMENR_GPIOFSMEN 5
RCC_AHB2SMENR_GPIOGSMEN 6
RCC_AHB2SMENR_CCMSRAMSMEN 9
RCC_AHB2SMENR_SRAM2SMEN 10
RCC_AHB2SMENR_ADC12SMEN 13
RCC_AHB2SMENR_ADC345SMEN 14
RCC_AHB2SMENR_DAC1SMEN 16
RCC_AHB2SMENR_DAC2SMEN 17
RCC_AHB2SMENR_DAC3SMEN 18
RCC_AHB2SMENR_DAC4SMEN 19
RCC_AHB2SMENR_RNGSMEN 26
AHB3SMENR 0x70 32 RCC AHB3 peripheral clocks enable in sleep and stop modes register
RCC_AHB3SMENR_FMCSMEN 0
RCC_AHB3SMENR_QSPISMEN 8
APB1SMENR1 0x78 32 RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1
RCC_APB1SMENR1_TIM2SMEN 0
RCC_APB1SMENR1_TIM3SMEN 1
RCC_APB1SMENR1_TIM4SMEN 2
RCC_APB1SMENR1_TIM5SMEN 3
RCC_APB1SMENR1_TIM6SMEN 4
RCC_APB1SMENR1_TIM7SMEN 5
RCC_APB1SMENR1_CRSSMEN 8
RCC_APB1SMENR1_RTCAPBSMEN 10
RCC_APB1SMENR1_WWDGSMEN 11
RCC_APB1SMENR1_SPI2SMEN 14
RCC_APB1SMENR1_SPI3SMEN 15
RCC_APB1SMENR1_USART2SMEN 17
RCC_APB1SMENR1_USART3SMEN 18
RCC_APB1SMENR1_UART4SMEN 19
RCC_APB1SMENR1_UART5SMEN 20
RCC_APB1SMENR1_I2C1SMEN 21
RCC_APB1SMENR1_I2C2SMEN 22
RCC_APB1SMENR1_USBSMEN 23
RCC_APB1SMENR1_FDCANSMEN 25
RCC_APB1SMENR1_PWRSMEN 28
RCC_APB1SMENR1_I2C3SMEN 30
RCC_APB1SMENR1_LPTIM1SMEN 31
APB1SMENR2 0x7C 32 RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2
RCC_APB1SMENR2_LPUART1SMEN 0
RCC_APB1SMENR2_I2C4SMEN 1
RCC_APB1SMENR2_UCPD1SMEN 8
APB2SMENR 0x80 32 RCC APB2 peripheral clocks enable in sleep mode and stop modes register
RCC_APB2SMENR_SYSCFGSMEN 0
RCC_APB2SMENR_TIM1SMEN 11
RCC_APB2SMENR_SPI1SMEN 12
RCC_APB2SMENR_TIM8SMEN 13
RCC_APB2SMENR_USART1SMEN 14
RCC_APB2SMENR_SPI4SMEN 15
RCC_APB2SMENR_TIM15SMEN 16
RCC_APB2SMENR_TIM16SMEN 17
RCC_APB2SMENR_TIM17SMEN 18
RCC_APB2SMENR_TIM20SMEN 20
RCC_APB2SMENR_SAI1SMEN 21
RCC_APB2SMENR_HRTIM1SMEN 26
CCIPR 0x88 32 RCC peripherals independent clock configuration register
RCC_CCIPR_USART1SEL 0:1
RCC_CCIPR_USART2SEL 2:3
RCC_CCIPR_USART3SEL 4:5
RCC_CCIPR_UART4SEL 6:7
RCC_CCIPR_UART5SEL 8:9
RCC_CCIPR_LPUART1SEL 10:11
RCC_CCIPR_I2C1SEL 12:13
RCC_CCIPR_I2C2SEL 14:15
RCC_CCIPR_I2C3SEL 16:17
RCC_CCIPR_LPTIM1SEL 18:19
RCC_CCIPR_SAI1SEL 20:21
RCC_CCIPR_I2S23SEL 22:23
RCC_CCIPR_FDCANSEL 24:25
RCC_CCIPR_CLK48SEL 26:27
RCC_CCIPR_ADC12SEL 28:29
RCC_CCIPR_ADC345SEL 31
BDCR 0x90 32 RCC backup domain control register
RCC_BDCR_LSEON 0
RCC_BDCR_LSERDY 1
RCC_BDCR_LSEBYP 2
RCC_BDCR_LSEDRV 3:4
RCC_BDCR_LSECSSON 5
RCC_BDCR_LSECSSD 6
RCC_BDCR_RTCSEL 8:9
RCC_BDCR_RTCEN 15
RCC_BDCR_BDRST 16
RCC_BDCR_LSCOEN 24
RCC_BDCR_LSCOSEL 25
CSR 0x94 32 RCC clock control & status register
RCC_CSR_LSION 0
RCC_CSR_LSIRDY 1
RCC_CSR_RMVF 23
RCC_CSR_OBLRSTF 25
RCC_CSR_PINRSTF 26
RCC_CSR_BORRSTF 27
RCC_CSR_SFTRSTF 28
RCC_CSR_IWDGRSTF 29
RCC_CSR_WWDGRSTF 30
RCC_CSR_LPWRRSTF 31
CRRCR 0x98 32 RCC clock recovery RC register
RCC_CRRCR_HSI48ON 0
RCC_CRRCR_HSI48RDY 1 HSI48CAL configuration
RCC_CRRCR_HSI48CAL 7:15 HSI48CAL[8:0] bits
CCIPR2 0x9C 32 RCC peripherals independent clock configuration register 2
RCC_CCIPR2_I2C4SEL 0:1
RCC_CCIPR2_QSPISEL 16:17

GPIO — Порты ввода-вывода (раздел 8)

Регистр Смещение Бит Назначение
MODER 0x00 32 GPIO port mode register
GPIO_MODER_MODE0 0:1
GPIO_MODER_MODE1 2:3
GPIO_MODER_MODE2 4:5
GPIO_MODER_MODE3 6:7
GPIO_MODER_MODE4 8:9
GPIO_MODER_MODE5 10:11
GPIO_MODER_MODE6 12:13
GPIO_MODER_MODE7 14:15
GPIO_MODER_MODE8 16:17
GPIO_MODER_MODE9 18:19
GPIO_MODER_MODE10 20:21
GPIO_MODER_MODE11 22:23
GPIO_MODER_MODE12 24:25
GPIO_MODER_MODE13 26:27
GPIO_MODER_MODE14 28:29
GPIO_MODER_MODE15 30:31
OTYPER 0x04 32 GPIO port output type register
GPIO_OTYPER_OT0 0
GPIO_OTYPER_OT1 1
GPIO_OTYPER_OT2 2
GPIO_OTYPER_OT3 3
GPIO_OTYPER_OT4 4
GPIO_OTYPER_OT5 5
GPIO_OTYPER_OT6 6
GPIO_OTYPER_OT7 7
GPIO_OTYPER_OT8 8
GPIO_OTYPER_OT9 9
GPIO_OTYPER_OT10 10
GPIO_OTYPER_OT11 11
GPIO_OTYPER_OT12 12
GPIO_OTYPER_OT13 13
GPIO_OTYPER_OT14 14
GPIO_OTYPER_OT15 15
OSPEEDR 0x08 32 GPIO port output speed register
GPIO_OSPEEDR_OSPEED0 0:1
GPIO_OSPEEDR_OSPEED1 2:3
GPIO_OSPEEDR_OSPEED2 4:5
GPIO_OSPEEDR_OSPEED3 6:7
GPIO_OSPEEDR_OSPEED4 8:9
GPIO_OSPEEDR_OSPEED5 10:11
GPIO_OSPEEDR_OSPEED6 12:13
GPIO_OSPEEDR_OSPEED7 14:15
GPIO_OSPEEDR_OSPEED8 16:17
GPIO_OSPEEDR_OSPEED9 18:19
GPIO_OSPEEDR_OSPEED10 20:21
GPIO_OSPEEDR_OSPEED11 22:23
GPIO_OSPEEDR_OSPEED12 24:25
GPIO_OSPEEDR_OSPEED13 26:27
GPIO_OSPEEDR_OSPEED14 28:29
GPIO_OSPEEDR_OSPEED15 30:31
PUPDR 0x0C 32 GPIO port pull-up/pull-down register
GPIO_PUPDR_PUPD0 0:1
GPIO_PUPDR_PUPD1 2:3
GPIO_PUPDR_PUPD2 4:5
GPIO_PUPDR_PUPD3 6:7
GPIO_PUPDR_PUPD4 8:9
GPIO_PUPDR_PUPD5 10:11
GPIO_PUPDR_PUPD6 12:13
GPIO_PUPDR_PUPD7 14:15
GPIO_PUPDR_PUPD8 16:17
GPIO_PUPDR_PUPD9 18:19
GPIO_PUPDR_PUPD10 20:21
GPIO_PUPDR_PUPD11 22:23
GPIO_PUPDR_PUPD12 24:25
GPIO_PUPDR_PUPD13 26:27
GPIO_PUPDR_PUPD14 28:29
GPIO_PUPDR_PUPD15 30:31
IDR 0x10 32 GPIO port input data register
GPIO_IDR_ID0 0
GPIO_IDR_ID1 1
GPIO_IDR_ID2 2
GPIO_IDR_ID3 3
GPIO_IDR_ID4 4
GPIO_IDR_ID5 5
GPIO_IDR_ID6 6
GPIO_IDR_ID7 7
GPIO_IDR_ID8 8
GPIO_IDR_ID9 9
GPIO_IDR_ID10 10
GPIO_IDR_ID11 11
GPIO_IDR_ID12 12
GPIO_IDR_ID13 13
GPIO_IDR_ID14 14
GPIO_IDR_ID15 15
ODR 0x14 32 GPIO port output data register
GPIO_ODR_OD0 0
GPIO_ODR_OD1 1
GPIO_ODR_OD2 2
GPIO_ODR_OD3 3
GPIO_ODR_OD4 4
GPIO_ODR_OD5 5
GPIO_ODR_OD6 6
GPIO_ODR_OD7 7
GPIO_ODR_OD8 8
GPIO_ODR_OD9 9
GPIO_ODR_OD10 10
GPIO_ODR_OD11 11
GPIO_ODR_OD12 12
GPIO_ODR_OD13 13
GPIO_ODR_OD14 14
GPIO_ODR_OD15 15
BSRR 0x18 32 GPIO port bit set/reset register
GPIO_BSRR_BS0 0
GPIO_BSRR_BS1 1
GPIO_BSRR_BS2 2
GPIO_BSRR_BS3 3
GPIO_BSRR_BS4 4
GPIO_BSRR_BS5 5
GPIO_BSRR_BS6 6
GPIO_BSRR_BS7 7
GPIO_BSRR_BS8 8
GPIO_BSRR_BS9 9
GPIO_BSRR_BS10 10
GPIO_BSRR_BS11 11
GPIO_BSRR_BS12 12
GPIO_BSRR_BS13 13
GPIO_BSRR_BS14 14
GPIO_BSRR_BS15 15
GPIO_BSRR_BR0 16
GPIO_BSRR_BR1 17
GPIO_BSRR_BR2 18
GPIO_BSRR_BR3 19
GPIO_BSRR_BR4 20
GPIO_BSRR_BR5 21
GPIO_BSRR_BR6 22
GPIO_BSRR_BR7 23
GPIO_BSRR_BR8 24
GPIO_BSRR_BR9 25
GPIO_BSRR_BR10 26
GPIO_BSRR_BR11 27
GPIO_BSRR_BR12 28
GPIO_BSRR_BR13 29
GPIO_BSRR_BR14 30
GPIO_BSRR_BR15 31
LCKR 0x1C 32 GPIO port configuration lock register
GPIO_LCKR_LCK0 0
GPIO_LCKR_LCK1 1
GPIO_LCKR_LCK2 2
GPIO_LCKR_LCK3 3
GPIO_LCKR_LCK4 4
GPIO_LCKR_LCK5 5
GPIO_LCKR_LCK6 6
GPIO_LCKR_LCK7 7
GPIO_LCKR_LCK8 8
GPIO_LCKR_LCK9 9
GPIO_LCKR_LCK10 10
GPIO_LCKR_LCK11 11
GPIO_LCKR_LCK12 12
GPIO_LCKR_LCK13 13
GPIO_LCKR_LCK14 14
GPIO_LCKR_LCK15 15
GPIO_LCKR_LCKK 16
AFR+2×4 0x20 32 GPIO alternate function registers
BRR 0x28 32 GPIO Bit Reset register
GPIO_BRR_BR0 0
GPIO_BRR_BR1 1
GPIO_BRR_BR2 2
GPIO_BRR_BR3 3
GPIO_BRR_BR4 4
GPIO_BRR_BR5 5
GPIO_BRR_BR6 6
GPIO_BRR_BR7 7
GPIO_BRR_BR8 8
GPIO_BRR_BR9 9
GPIO_BRR_BR10 10
GPIO_BRR_BR11 11
GPIO_BRR_BR12 12
GPIO_BRR_BR13 13
GPIO_BRR_BR14 14
GPIO_BRR_BR15 15

SYSCFG — Системная конфигурация (раздел 8)

Регистр Смещение Бит Назначение
MEMRMP 0x00 32 SYSCFG memory remap register
SYSCFG_MEMRMP_MEM_MODE 0:2 SYSCFG_Memory Remap Config
SYSCFG_MEMRMP_FB_MODE 8 User Flash Bank mode selection
CFGR1 0x04 32 SYSCFG configuration register 1
SYSCFG_CFGR1_BOOSTEN 8 I/O analog switch voltage booster enable
SYSCFG_CFGR1_ANASWVDD 9 GPIO analog switch control voltage selection
SYSCFG_CFGR1_I2C_PB6_FMP 16 I2C PB6 Fast mode plus
SYSCFG_CFGR1_I2C_PB7_FMP 17 I2C PB7 Fast mode plus
SYSCFG_CFGR1_I2C_PB8_FMP 18 I2C PB8 Fast mode plus
SYSCFG_CFGR1_I2C_PB9_FMP 19 I2C PB9 Fast mode plus
SYSCFG_CFGR1_I2C1_FMP 20 I2C1 Fast mode plus
SYSCFG_CFGR1_I2C2_FMP 21 I2C2 Fast mode plus
SYSCFG_CFGR1_I2C3_FMP 22 I2C3 Fast mode plus
SYSCFG_CFGR1_I2C4_FMP 23 I2C4 Fast mode plus
EXTICR+4×4 0x08 32 SYSCFG external interrupt configuration registers
SCSR 0x18 32 SYSCFG CCMSRAM control and status register
SYSCFG_SCSR_CCMER 0 CCMSRAM Erase Request
SYSCFG_SCSR_CCMBSY 1 CCMSRAM Erase Ongoing
CFGR2 0x1C 32 SYSCFG configuration register 2
SYSCFG_CFGR2_CLL 0 Core Lockup Lock
SYSCFG_CFGR2_SPL 1 SRAM Parity Lock
SYSCFG_CFGR2_PVDL 2 PVD Lock
SYSCFG_CFGR2_ECCL 3 ECC Lock
SYSCFG_CFGR2_SPF 8 SRAM Parity Flag
SWPR 0x20 32 SYSCFG CCMSRAM write protection register
SYSCFG_SWPR_PAGE0 0
SYSCFG_SWPR_PAGE1 1
SYSCFG_SWPR_PAGE2 2
SYSCFG_SWPR_PAGE3 3
SYSCFG_SWPR_PAGE4 4
SYSCFG_SWPR_PAGE5 5
SYSCFG_SWPR_PAGE6 6
SYSCFG_SWPR_PAGE7 7
SYSCFG_SWPR_PAGE8 8
SYSCFG_SWPR_PAGE9 9
SYSCFG_SWPR_PAGE10 10
SYSCFG_SWPR_PAGE11 11
SYSCFG_SWPR_PAGE12 12
SYSCFG_SWPR_PAGE13 13
SYSCFG_SWPR_PAGE14 14
SYSCFG_SWPR_PAGE15 15
SYSCFG_SWPR_PAGE16 16
SYSCFG_SWPR_PAGE17 17
SYSCFG_SWPR_PAGE18 18
SYSCFG_SWPR_PAGE19 19
SYSCFG_SWPR_PAGE20 20
SYSCFG_SWPR_PAGE21 21
SYSCFG_SWPR_PAGE22 22
SYSCFG_SWPR_PAGE23 23
SYSCFG_SWPR_PAGE24 24
SYSCFG_SWPR_PAGE25 25
SYSCFG_SWPR_PAGE26 26
SYSCFG_SWPR_PAGE27 27
SYSCFG_SWPR_PAGE28 28
SYSCFG_SWPR_PAGE29 29
SYSCFG_SWPR_PAGE30 30
SYSCFG_SWPR_PAGE31 31
SKR 0x24 32 SYSCFG CCMSRAM Key Register
SYSCFG_SKR_KEY 0:7 CCMSRAM write protection key for software erase

EXTI — Внешние прерывания (раздел 7)

Регистр Смещение Бит Назначение
IMR1 0x00 32 EXTI Interrupt mask register 1
EXTI_IMR1_IM0 0 Interrupt Mask on line 0
EXTI_IMR1_IM 0:31 Interrupt Mask All
EXTI_IMR1_IM1 1 Interrupt Mask on line 1
EXTI_IMR1_IM2 2 Interrupt Mask on line 2
EXTI_IMR1_IM3 3 Interrupt Mask on line 3
EXTI_IMR1_IM4 4 Interrupt Mask on line 4
EXTI_IMR1_IM5 5 Interrupt Mask on line 5
EXTI_IMR1_IM6 6 Interrupt Mask on line 6
EXTI_IMR1_IM7 7 Interrupt Mask on line 7
EXTI_IMR1_IM8 8 Interrupt Mask on line 8
EXTI_IMR1_IM9 9 Interrupt Mask on line 9
EXTI_IMR1_IM10 10 Interrupt Mask on line 10
EXTI_IMR1_IM11 11 Interrupt Mask on line 11
EXTI_IMR1_IM12 12 Interrupt Mask on line 12
EXTI_IMR1_IM13 13 Interrupt Mask on line 13
EXTI_IMR1_IM14 14 Interrupt Mask on line 14
EXTI_IMR1_IM15 15 Interrupt Mask on line 15
EXTI_IMR1_IM16 16 Interrupt Mask on line 16
EXTI_IMR1_IM17 17 Interrupt Mask on line 17
EXTI_IMR1_IM18 18 Interrupt Mask on line 18
EXTI_IMR1_IM19 19 Interrupt Mask on line 19
EXTI_IMR1_IM20 20 Interrupt Mask on line 20
EXTI_IMR1_IM21 21 Interrupt Mask on line 21
EXTI_IMR1_IM22 22 Interrupt Mask on line 22
EXTI_IMR1_IM23 23 Interrupt Mask on line 23
EXTI_IMR1_IM24 24 Interrupt Mask on line 24
EXTI_IMR1_IM25 25 Interrupt Mask on line 25
EXTI_IMR1_IM26 26 Interrupt Mask on line 26
EXTI_IMR1_IM27 27 Interrupt Mask on line 27
EXTI_IMR1_IM28 28 Interrupt Mask on line 28
EXTI_IMR1_IM29 29 Interrupt Mask on line 29
EXTI_IMR1_IM30 30 Interrupt Mask on line 30
EXTI_IMR1_IM31 31 Interrupt Mask on line 31
EMR1 0x04 32 EXTI Event mask register 1
EXTI_EMR1_EM0 0 Event Mask on line 0
EXTI_EMR1_EM1 1 Event Mask on line 1
EXTI_EMR1_EM2 2 Event Mask on line 2
EXTI_EMR1_EM3 3 Event Mask on line 3
EXTI_EMR1_EM4 4 Event Mask on line 4
EXTI_EMR1_EM5 5 Event Mask on line 5
EXTI_EMR1_EM6 6 Event Mask on line 6
EXTI_EMR1_EM7 7 Event Mask on line 7
EXTI_EMR1_EM8 8 Event Mask on line 8
EXTI_EMR1_EM9 9 Event Mask on line 9
EXTI_EMR1_EM10 10 Event Mask on line 10
EXTI_EMR1_EM11 11 Event Mask on line 11
EXTI_EMR1_EM12 12 Event Mask on line 12
EXTI_EMR1_EM13 13 Event Mask on line 13
EXTI_EMR1_EM14 14 Event Mask on line 14
EXTI_EMR1_EM15 15 Event Mask on line 15
EXTI_EMR1_EM16 16 Event Mask on line 16
EXTI_EMR1_EM17 17 Event Mask on line 17
EXTI_EMR1_EM18 18 Event Mask on line 18
EXTI_EMR1_EM19 19 Event Mask on line 19
EXTI_EMR1_EM20 20 Event Mask on line 20
EXTI_EMR1_EM21 21 Event Mask on line 21
EXTI_EMR1_EM22 22 Event Mask on line 22
EXTI_EMR1_EM23 23 Event Mask on line 23
EXTI_EMR1_EM24 24 Event Mask on line 24
EXTI_EMR1_EM25 25 Event Mask on line 25
EXTI_EMR1_EM26 26 Event Mask on line 26
EXTI_EMR1_EM27 27 Event Mask on line 27
EXTI_EMR1_EM28 28 Event Mask on line 28
EXTI_EMR1_EM29 29 Event Mask on line 29
EXTI_EMR1_EM30 30 Event Mask on line 30
EXTI_EMR1_EM31 31 Event Mask on line 31
RTSR1 0x08 32 EXTI Rising trigger selection register 1
EXTI_RTSR1_RT0 0 Rising trigger event configuration bit of line 0
EXTI_RTSR1_RT1 1 Rising trigger event configuration bit of line 1
EXTI_RTSR1_RT2 2 Rising trigger event configuration bit of line 2
EXTI_RTSR1_RT3 3 Rising trigger event configuration bit of line 3
EXTI_RTSR1_RT4 4 Rising trigger event configuration bit of line 4
EXTI_RTSR1_RT5 5 Rising trigger event configuration bit of line 5
EXTI_RTSR1_RT6 6 Rising trigger event configuration bit of line 6
EXTI_RTSR1_RT7 7 Rising trigger event configuration bit of line 7
EXTI_RTSR1_RT8 8 Rising trigger event configuration bit of line 8
EXTI_RTSR1_RT9 9 Rising trigger event configuration bit of line 9
EXTI_RTSR1_RT10 10 Rising trigger event configuration bit of line 10
EXTI_RTSR1_RT11 11 Rising trigger event configuration bit of line 11
EXTI_RTSR1_RT12 12 Rising trigger event configuration bit of line 12
EXTI_RTSR1_RT13 13 Rising trigger event configuration bit of line 13
EXTI_RTSR1_RT14 14 Rising trigger event configuration bit of line 14
EXTI_RTSR1_RT15 15 Rising trigger event configuration bit of line 15
EXTI_RTSR1_RT16 16 Rising trigger event configuration bit of line 16
EXTI_RTSR1_RT17 17 Rising trigger event configuration bit of line 17
EXTI_RTSR1_RT19 19 Rising trigger event configuration bit of line 19
EXTI_RTSR1_RT20 20 Rising trigger event configuration bit of line 20
EXTI_RTSR1_RT21 21 Rising trigger event configuration bit of line 21
EXTI_RTSR1_RT22 22 Rising trigger event configuration bit of line 22
EXTI_RTSR1_RT29 29 Rising trigger event configuration bit of line 29
EXTI_RTSR1_RT30 30 Rising trigger event configuration bit of line 30
EXTI_RTSR1_RT31 31 Rising trigger event configuration bit of line 31
FTSR1 0x0C 32 EXTI Falling trigger selection register 1
EXTI_FTSR1_FT0 0 Falling trigger event configuration bit of line 0
EXTI_FTSR1_FT1 1 Falling trigger event configuration bit of line 1
EXTI_FTSR1_FT2 2 Falling trigger event configuration bit of line 2
EXTI_FTSR1_FT3 3 Falling trigger event configuration bit of line 3
EXTI_FTSR1_FT4 4 Falling trigger event configuration bit of line 4
EXTI_FTSR1_FT5 5 Falling trigger event configuration bit of line 5
EXTI_FTSR1_FT6 6 Falling trigger event configuration bit of line 6
EXTI_FTSR1_FT7 7 Falling trigger event configuration bit of line 7
EXTI_FTSR1_FT8 8 Falling trigger event configuration bit of line 8
EXTI_FTSR1_FT9 9 Falling trigger event configuration bit of line 9
EXTI_FTSR1_FT10 10 Falling trigger event configuration bit of line 10
EXTI_FTSR1_FT11 11 Falling trigger event configuration bit of line 11
EXTI_FTSR1_FT12 12 Falling trigger event configuration bit of line 12
EXTI_FTSR1_FT13 13 Falling trigger event configuration bit of line 13
EXTI_FTSR1_FT14 14 Falling trigger event configuration bit of line 14
EXTI_FTSR1_FT15 15 Falling trigger event configuration bit of line 15
EXTI_FTSR1_FT16 16 Falling trigger event configuration bit of line 16
EXTI_FTSR1_FT17 17 Falling trigger event configuration bit of line 17
EXTI_FTSR1_FT19 19 Falling trigger event configuration bit of line 19
EXTI_FTSR1_FT20 20 Falling trigger event configuration bit of line 20
EXTI_FTSR1_FT21 21 Falling trigger event configuration bit of line 21
EXTI_FTSR1_FT22 22 Falling trigger event configuration bit of line 22
EXTI_FTSR1_FT29 29 Falling trigger event configuration bit of line 29
EXTI_FTSR1_FT30 30 Falling trigger event configuration bit of line 30
EXTI_FTSR1_FT31 31 Falling trigger event configuration bit of line 31
SWIER1 0x10 32 EXTI Software interrupt event register 1
EXTI_SWIER1_SWI0 0 Software Interrupt on line 0
EXTI_SWIER1_SWI1 1 Software Interrupt on line 1
EXTI_SWIER1_SWI2 2 Software Interrupt on line 2
EXTI_SWIER1_SWI3 3 Software Interrupt on line 3
EXTI_SWIER1_SWI4 4 Software Interrupt on line 4
EXTI_SWIER1_SWI5 5 Software Interrupt on line 5
EXTI_SWIER1_SWI6 6 Software Interrupt on line 6
EXTI_SWIER1_SWI7 7 Software Interrupt on line 7
EXTI_SWIER1_SWI8 8 Software Interrupt on line 8
EXTI_SWIER1_SWI9 9 Software Interrupt on line 9
EXTI_SWIER1_SWI10 10 Software Interrupt on line 10
EXTI_SWIER1_SWI11 11 Software Interrupt on line 11
EXTI_SWIER1_SWI12 12 Software Interrupt on line 12
EXTI_SWIER1_SWI13 13 Software Interrupt on line 13
EXTI_SWIER1_SWI14 14 Software Interrupt on line 14
EXTI_SWIER1_SWI15 15 Software Interrupt on line 15
EXTI_SWIER1_SWI16 16 Software Interrupt on line 16
EXTI_SWIER1_SWI17 17 Software Interrupt on line 17
EXTI_SWIER1_SWI19 19 Software Interrupt on line 19
EXTI_SWIER1_SWI20 20 Software Interrupt on line 20
EXTI_SWIER1_SWI21 21 Software Interrupt on line 21
EXTI_SWIER1_SWI22 22 Software Interrupt on line 22
EXTI_SWIER1_SWI29 29 Software Interrupt on line 29
EXTI_SWIER1_SWI30 30 Software Interrupt on line 30
EXTI_SWIER1_SWI31 31 Software Interrupt on line 31
PR1 0x14 32 EXTI Pending register 1
EXTI_PR1_PIF0 0 Pending bit for line 0
EXTI_PR1_PIF1 1 Pending bit for line 1
EXTI_PR1_PIF2 2 Pending bit for line 2
EXTI_PR1_PIF3 3 Pending bit for line 3
EXTI_PR1_PIF4 4 Pending bit for line 4
EXTI_PR1_PIF5 5 Pending bit for line 5
EXTI_PR1_PIF6 6 Pending bit for line 6
EXTI_PR1_PIF7 7 Pending bit for line 7
EXTI_PR1_PIF8 8 Pending bit for line 8
EXTI_PR1_PIF9 9 Pending bit for line 9
EXTI_PR1_PIF10 10 Pending bit for line 10
EXTI_PR1_PIF11 11 Pending bit for line 11
EXTI_PR1_PIF12 12 Pending bit for line 12
EXTI_PR1_PIF13 13 Pending bit for line 13
EXTI_PR1_PIF14 14 Pending bit for line 14
EXTI_PR1_PIF15 15 Pending bit for line 15
EXTI_PR1_PIF16 16 Pending bit for line 16
EXTI_PR1_PIF17 17 Pending bit for line 17
EXTI_PR1_PIF19 19 Pending bit for line 19
EXTI_PR1_PIF20 20 Pending bit for line 20
EXTI_PR1_PIF21 21 Pending bit for line 21
EXTI_PR1_PIF22 22 Pending bit for line 22
EXTI_PR1_PIF29 29 Pending bit for line 29
EXTI_PR1_PIF30 30 Pending bit for line 30
EXTI_PR1_PIF31 31 Pending bit for line 31
IMR2 0x20 32 EXTI Interrupt mask register 2
EXTI_IMR2_IM32 0 Interrupt Mask on line 32
EXTI_IMR2_IM 0:10 Interrupt Mask all
EXTI_IMR2_IM33 1 Interrupt Mask on line 33
EXTI_IMR2_IM34 2 Interrupt Mask on line 34
EXTI_IMR2_IM35 3 Interrupt Mask on line 35
EXTI_IMR2_IM36 4 Interrupt Mask on line 36
EXTI_IMR2_IM37 5 Interrupt Mask on line 37
EXTI_IMR2_IM38 6 Interrupt Mask on line 38
EXTI_IMR2_IM39 7 Interrupt Mask on line 39
EXTI_IMR2_IM40 8 Interrupt Mask on line 40
EXTI_IMR2_IM41 9 Interrupt Mask on line 41
EXTI_IMR2_IM42 10 Interrupt Mask on line 42
EMR2 0x24 32 EXTI Event mask register 2
EXTI_EMR2_EM32 0 Event Mask on line 32
EXTI_EMR2_EM 0:10 Interrupt Mask all
EXTI_EMR2_EM33 1 Event Mask on line 33
EXTI_EMR2_EM34 2 Event Mask on line 34
EXTI_EMR2_EM35 3 Event Mask on line 35
EXTI_EMR2_EM36 4 Event Mask on line 36
EXTI_EMR2_EM37 5 Event Mask on line 37
EXTI_EMR2_EM38 6 Event Mask on line 38
EXTI_EMR2_EM39 7 Event Mask on line 39
EXTI_EMR2_EM40 8 Event Mask on line 40
EXTI_EMR2_EM41 9 Event Mask on line 41
EXTI_EMR2_EM42 10 Event Mask on line 42
RTSR2 0x28 32 EXTI Rising trigger selection register 2
EXTI_RTSR2_RT32 0 Rising trigger event configuration bit of line 32
EXTI_RTSR2_RT33 1 Rising trigger event configuration bit of line 33
EXTI_RTSR2_RT38 6 Rising trigger event configuration bit of line 38
EXTI_RTSR2_RT39 7 Rising trigger event configuration bit of line 39
EXTI_RTSR2_RT40 8 Rising trigger event configuration bit of line 40
EXTI_RTSR2_RT41 9 Rising trigger event configuration bit of line 41
FTSR2 0x2C 32 EXTI Falling trigger selection register 2
EXTI_FTSR2_FT32 0 Falling trigger event configuration bit of line 32
EXTI_FTSR2_FT33 1 Falling trigger event configuration bit of line 33
EXTI_FTSR2_FT38 6 Falling trigger event configuration bit of line 37
EXTI_FTSR2_FT39 7 Falling trigger event configuration bit of line 39
EXTI_FTSR2_FT40 8 Falling trigger event configuration bit of line 40
EXTI_FTSR2_FT41 9 Falling trigger event configuration bit of line 41
SWIER2 0x30 32 EXTI Software interrupt event register 2
EXTI_SWIER2_SWI32 0 Software Interrupt on line 32
EXTI_SWIER2_SWI33 1 Software Interrupt on line 33
EXTI_SWIER2_SWI38 6 Software Interrupt on line 38
EXTI_SWIER2_SWI39 7 Software Interrupt on line 39
EXTI_SWIER2_SWI40 8 Software Interrupt on line 40
EXTI_SWIER2_SWI41 9 Software Interrupt on line 41
PR2 0x34 32 EXTI Pending register 2
EXTI_PR2_PIF32 0 Pending bit for line 32
EXTI_PR2_PIF33 1 Pending bit for line 33
EXTI_PR2_PIF38 6 Pending bit for line 38
EXTI_PR2_PIF39 7 Pending bit for line 39
EXTI_PR2_PIF40 8 Pending bit for line 40
EXTI_PR2_PIF41 9 Pending bit for line 41

DMA — Канал DMA (раздел 9)

Регистр Смещение Бит Назначение
CCR 0x00 32 DMA channel x configuration register
DMA_CCR_EN 0 Channel enable
DMA_CCR_TCIE 1 Transfer complete interrupt enable
DMA_CCR_HTIE 2 Half Transfer interrupt enable
DMA_CCR_TEIE 3 Transfer error interrupt enable
DMA_CCR_DIR 4 Data transfer direction
DMA_CCR_CIRC 5 Circular mode
DMA_CCR_PINC 6 Peripheral increment mode
DMA_CCR_MINC 7 Memory increment mode
DMA_CCR_PSIZE 8:9 PSIZE[1:0] bits (Peripheral size)
DMA_CCR_MSIZE 10:11 MSIZE[1:0] bits (Memory size)
DMA_CCR_PL 12:13 PL[1:0] bits(Channel Priority level)
DMA_CCR_MEM2MEM 14 Memory to memory mode
CNDTR 0x04 32 DMA channel x number of data register
DMA_CNDTR_NDT 0:15 Number of data to Transfer
CPAR 0x08 32 DMA channel x peripheral address register
DMA_CPAR_PA 0:31 Peripheral Address
CMAR 0x0C 32 DMA channel x memory address register
DMA_CMAR_MA 0:31 Memory Address

PWR — Питание и режимы сна (раздел 10)

Регистр Смещение Бит Назначение
CR1 0x00 32 PWR power control register 1
PWR_CR1_LPMS 0:2 Low-power mode selection field
PWR_CR1_LPMS_STOP1 0 Stop 1 mode
PWR_CR1_LPMS_STANDBY 0:1 Stand-by mode
PWR_CR1_LPMS_SHUTDOWN 2 Shut-down mode
PWR_CR1_DBP 8 Disable Back-up domain Protection
PWR_CR1_VOS 9:10 VOS[1:0] bits (Regulator voltage scaling output selection)
PWR_CR1_LPR 14 Regulator low-power mode
CR2 0x04 32 PWR power control register 2
PWR_CR2_PVDE 0 Power Voltage Detector Enable
PWR_CR2_PLS 1:3 PVD level selection
PWR_CR2_PLS_LEV1 1 PVD level 1
PWR_CR2_PLS_LEV3 1:2 PVD level 3
PWR_CR2_PLS_LEV5 1:3 PVD level 5
PWR_CR2_PLS_LEV7 1:3 PVD level 7
PWR_CR2_PLS_LEV2 2 PVD level 2
PWR_CR2_PLS_LEV6 2:3 PVD level 6
PWR_CR2_PLS_LEV4 3 PVD level 4
PWR_CR2_PVME 4:7 PVM bits field
PWR_CR2_PVME1 4 PVM 1 Enable
PWR_CR2_PVME2 5 PVM 2 Enable
PWR_CR2_PVME3 6 PVM 3 Enable
PWR_CR2_PVME4 7 PVM 4 Enable
CR3 0x08 32 PWR power control register 3
PWR_CR3_EWUP1 0 Enable Wake-Up Pin 1
PWR_CR3_EWUP 0:4 Enable Wake-Up Pins
PWR_CR3_EWUP2 1 Enable Wake-Up Pin 2
PWR_CR3_EWUP3 2 Enable Wake-Up Pin 3
PWR_CR3_EWUP4 3 Enable Wake-Up Pin 4
PWR_CR3_EWUP5 4 Enable Wake-Up Pin 5
PWR_CR3_RRS 8 SRAM2 Retention in Stand-by mode
PWR_CR3_APC 10 Apply pull-up and pull-down configuration
PWR_CR3_UCPD_STDBY 13 USB Type-C and Power Delivery standby mode.
PWR_CR3_UCPD_DBDIS 14 USB Type-C and Power Delivery Dead Battery disable.
PWR_CR3_EIWF 15 Enable Internal Wake-up line
CR4 0x0C 32 PWR power control register 4
PWR_CR4_WP1 0 Wake-Up Pin 1 polarity
PWR_CR4_WP2 1 Wake-Up Pin 2 polarity
PWR_CR4_WP3 2 Wake-Up Pin 3 polarity
PWR_CR4_WP4 3 Wake-Up Pin 4 polarity
PWR_CR4_WP5 4 Wake-Up Pin 5 polarity
PWR_CR4_VBE 8 VBAT Battery charging Enable
PWR_CR4_VBRS 9 VBAT Battery charging Resistor Selection
SR1 0x10 32 PWR power status register 1
PWR_SR1_WUF 0:4 Wake-up Flags
PWR_SR1_WUF1 0 Wake-up Flag 1
PWR_SR1_WUF2 1 Wake-up Flag 2
PWR_SR1_WUF3 2 Wake-up Flag 3
PWR_SR1_WUF4 3 Wake-up Flag 4
PWR_SR1_WUF5 4 Wake-up Flag 5
PWR_SR1_SBF 8 Stand-By Flag
PWR_SR1_WUFI 15 Wake-Up Flag Internal
SR2 0x14 32 PWR power status register 2
PWR_SR2_REGLPS 8 Low-power Regulator Started
PWR_SR2_REGLPF 9 Low-power Regulator Flag
PWR_SR2_VOSF 10 Voltage Scaling Flag
PWR_SR2_PVDO 11 Power Voltage Detector Output
PWR_SR2_PVMO1 12 Peripheral Voltage Monitoring Output 1
PWR_SR2_PVMO2 13 Peripheral Voltage Monitoring Output 2
PWR_SR2_PVMO3 14 Peripheral Voltage Monitoring Output 3
PWR_SR2_PVMO4 15 Peripheral Voltage Monitoring Output 4
SCR 0x18 32 PWR power status reset register
PWR_SCR_CWUF 0:4 Clear Wake-up Flags
PWR_SCR_CWUF1 0 Clear Wake-up Flag 1
PWR_SCR_CWUF2 1 Clear Wake-up Flag 2
PWR_SCR_CWUF3 2 Clear Wake-up Flag 3
PWR_SCR_CWUF4 3 Clear Wake-up Flag 4
PWR_SCR_CWUF5 4 Clear Wake-up Flag 5
PWR_SCR_CSBF 8 Clear Stand-By Flag
PUCRA 0x20 32 Pull_up control register of portA
PWR_PUCRA_PA0 0 Port PA0 Pull-Up set
PWR_PUCRA_PA1 1 Port PA1 Pull-Up set
PWR_PUCRA_PA2 2 Port PA2 Pull-Up set
PWR_PUCRA_PA3 3 Port PA3 Pull-Up set
PWR_PUCRA_PA4 4 Port PA4 Pull-Up set
PWR_PUCRA_PA5 5 Port PA5 Pull-Up set
PWR_PUCRA_PA6 6 Port PA6 Pull-Up set
PWR_PUCRA_PA7 7 Port PA7 Pull-Up set
PWR_PUCRA_PA8 8 Port PA8 Pull-Up set
PWR_PUCRA_PA9 9 Port PA9 Pull-Up set
PWR_PUCRA_PA10 10 Port PA10 Pull-Up set
PWR_PUCRA_PA11 11 Port PA11 Pull-Up set
PWR_PUCRA_PA12 12 Port PA12 Pull-Up set
PWR_PUCRA_PA13 13 Port PA13 Pull-Up set
PWR_PUCRA_PA15 15 Port PA15 Pull-Up set
PDCRA 0x24 32 Pull_Down control register of portA
PWR_PDCRA_PA0 0 Port PA0 Pull-Down set
PWR_PDCRA_PA1 1 Port PA1 Pull-Down set
PWR_PDCRA_PA2 2 Port PA2 Pull-Down set
PWR_PDCRA_PA3 3 Port PA3 Pull-Down set
PWR_PDCRA_PA4 4 Port PA4 Pull-Down set
PWR_PDCRA_PA5 5 Port PA5 Pull-Down set
PWR_PDCRA_PA6 6 Port PA6 Pull-Down set
PWR_PDCRA_PA7 7 Port PA7 Pull-Down set
PWR_PDCRA_PA8 8 Port PA8 Pull-Down set
PWR_PDCRA_PA9 9 Port PA9 Pull-Down set
PWR_PDCRA_PA10 10 Port PA10 Pull-Down set
PWR_PDCRA_PA11 11 Port PA11 Pull-Down set
PWR_PDCRA_PA12 12 Port PA12 Pull-Down set
PWR_PDCRA_PA14 14 Port PA14 Pull-Down set
PUCRB 0x28 32 Pull_up control register of portB
PWR_PUCRB_PB0 0 Port PB0 Pull-Up set
PWR_PUCRB_PB1 1 Port PB1 Pull-Up set
PWR_PUCRB_PB2 2 Port PB2 Pull-Up set
PWR_PUCRB_PB3 3 Port PB3 Pull-Up set
PWR_PUCRB_PB4 4 Port PB4 Pull-Up set
PWR_PUCRB_PB5 5 Port PB5 Pull-Up set
PWR_PUCRB_PB6 6 Port PB6 Pull-Up set
PWR_PUCRB_PB7 7 Port PB7 Pull-Up set
PWR_PUCRB_PB8 8 Port PB8 Pull-Up set
PWR_PUCRB_PB9 9 Port PB9 Pull-Up set
PWR_PUCRB_PB10 10 Port PB10 Pull-Up set
PWR_PUCRB_PB11 11 Port PB11 Pull-Up set
PWR_PUCRB_PB12 12 Port PB12 Pull-Up set
PWR_PUCRB_PB13 13 Port PB13 Pull-Up set
PWR_PUCRB_PB14 14 Port PB14 Pull-Up set
PWR_PUCRB_PB15 15 Port PB15 Pull-Up set
PDCRB 0x2C 32 Pull_Down control register of portB
PWR_PDCRB_PB0 0 Port PB0 Pull-Down set
PWR_PDCRB_PB1 1 Port PB1 Pull-Down set
PWR_PDCRB_PB2 2 Port PB2 Pull-Down set
PWR_PDCRB_PB3 3 Port PB3 Pull-Down set
PWR_PDCRB_PB5 5 Port PB5 Pull-Down set
PWR_PDCRB_PB6 6 Port PB6 Pull-Down set
PWR_PDCRB_PB7 7 Port PB7 Pull-Down set
PWR_PDCRB_PB8 8 Port PB8 Pull-Down set
PWR_PDCRB_PB9 9 Port PB9 Pull-Down set
PWR_PDCRB_PB10 10 Port PB10 Pull-Down set
PWR_PDCRB_PB11 11 Port PB11 Pull-Down set
PWR_PDCRB_PB12 12 Port PB12 Pull-Down set
PWR_PDCRB_PB13 13 Port PB13 Pull-Down set
PWR_PDCRB_PB14 14 Port PB14 Pull-Down set
PWR_PDCRB_PB15 15 Port PB15 Pull-Down set
PUCRC 0x30 32 Pull_up control register of portC
PWR_PUCRC_PC0 0 Port PC0 Pull-Up set
PWR_PUCRC_PC1 1 Port PC1 Pull-Up set
PWR_PUCRC_PC2 2 Port PC2 Pull-Up set
PWR_PUCRC_PC3 3 Port PC3 Pull-Up set
PWR_PUCRC_PC4 4 Port PC4 Pull-Up set
PWR_PUCRC_PC5 5 Port PC5 Pull-Up set
PWR_PUCRC_PC6 6 Port PC6 Pull-Up set
PWR_PUCRC_PC7 7 Port PC7 Pull-Up set
PWR_PUCRC_PC8 8 Port PC8 Pull-Up set
PWR_PUCRC_PC9 9 Port PC9 Pull-Up set
PWR_PUCRC_PC10 10 Port PC10 Pull-Up set
PWR_PUCRC_PC11 11 Port PC11 Pull-Up set
PWR_PUCRC_PC12 12 Port PC12 Pull-Up set
PWR_PUCRC_PC13 13 Port PC13 Pull-Up set
PWR_PUCRC_PC14 14 Port PC14 Pull-Up set
PWR_PUCRC_PC15 15 Port PC15 Pull-Up set
PDCRC 0x34 32 Pull_Down control register of portC
PWR_PDCRC_PC0 0 Port PC0 Pull-Down set
PWR_PDCRC_PC1 1 Port PC1 Pull-Down set
PWR_PDCRC_PC2 2 Port PC2 Pull-Down set
PWR_PDCRC_PC3 3 Port PC3 Pull-Down set
PWR_PDCRC_PC4 4 Port PC4 Pull-Down set
PWR_PDCRC_PC5 5 Port PC5 Pull-Down set
PWR_PDCRC_PC6 6 Port PC6 Pull-Down set
PWR_PDCRC_PC7 7 Port PC7 Pull-Down set
PWR_PDCRC_PC8 8 Port PC8 Pull-Down set
PWR_PDCRC_PC9 9 Port PC9 Pull-Down set
PWR_PDCRC_PC10 10 Port PC10 Pull-Down set
PWR_PDCRC_PC11 11 Port PC11 Pull-Down set
PWR_PDCRC_PC12 12 Port PC12 Pull-Down set
PWR_PDCRC_PC13 13 Port PC13 Pull-Down set
PWR_PDCRC_PC14 14 Port PC14 Pull-Down set
PWR_PDCRC_PC15 15 Port PC15 Pull-Down set
PUCRD 0x38 32 Pull_up control register of portD
PWR_PUCRD_PD0 0 Port PD0 Pull-Up set
PWR_PUCRD_PD1 1 Port PD1 Pull-Up set
PWR_PUCRD_PD2 2 Port PD2 Pull-Up set
PWR_PUCRD_PD3 3 Port PD3 Pull-Up set
PWR_PUCRD_PD4 4 Port PD4 Pull-Up set
PWR_PUCRD_PD5 5 Port PD5 Pull-Up set
PWR_PUCRD_PD6 6 Port PD6 Pull-Up set
PWR_PUCRD_PD7 7 Port PD7 Pull-Up set
PWR_PUCRD_PD8 8 Port PD8 Pull-Up set
PWR_PUCRD_PD9 9 Port PD9 Pull-Up set
PWR_PUCRD_PD10 10 Port PD10 Pull-Up set
PWR_PUCRD_PD11 11 Port PD11 Pull-Up set
PWR_PUCRD_PD12 12 Port PD12 Pull-Up set
PWR_PUCRD_PD13 13 Port PD13 Pull-Up set
PWR_PUCRD_PD14 14 Port PD14 Pull-Up set
PWR_PUCRD_PD15 15 Port PD15 Pull-Up set
PDCRD 0x3C 32 Pull_Down control register of portD
PWR_PDCRD_PD0 0 Port PD0 Pull-Down set
PWR_PDCRD_PD1 1 Port PD1 Pull-Down set
PWR_PDCRD_PD2 2 Port PD2 Pull-Down set
PWR_PDCRD_PD3 3 Port PD3 Pull-Down set
PWR_PDCRD_PD4 4 Port PD4 Pull-Down set
PWR_PDCRD_PD5 5 Port PD5 Pull-Down set
PWR_PDCRD_PD6 6 Port PD6 Pull-Down set
PWR_PDCRD_PD7 7 Port PD7 Pull-Down set
PWR_PDCRD_PD8 8 Port PD8 Pull-Down set
PWR_PDCRD_PD9 9 Port PD9 Pull-Down set
PWR_PDCRD_PD10 10 Port PD10 Pull-Down set
PWR_PDCRD_PD11 11 Port PD11 Pull-Down set
PWR_PDCRD_PD12 12 Port PD12 Pull-Down set
PWR_PDCRD_PD13 13 Port PD13 Pull-Down set
PWR_PDCRD_PD14 14 Port PD14 Pull-Down set
PWR_PDCRD_PD15 15 Port PD15 Pull-Down set
PUCRE 0x40 32 Pull_up control register of portE
PWR_PUCRE_PE0 0 Port PE0 Pull-Up set
PWR_PUCRE_PE1 1 Port PE1 Pull-Up set
PWR_PUCRE_PE2 2 Port PE2 Pull-Up set
PWR_PUCRE_PE3 3 Port PE3 Pull-Up set
PWR_PUCRE_PE4 4 Port PE4 Pull-Up set
PWR_PUCRE_PE5 5 Port PE5 Pull-Up set
PWR_PUCRE_PE6 6 Port PE6 Pull-Up set
PWR_PUCRE_PE7 7 Port PE7 Pull-Up set
PWR_PUCRE_PE8 8 Port PE8 Pull-Up set
PWR_PUCRE_PE9 9 Port PE9 Pull-Up set
PWR_PUCRE_PE10 10 Port PE10 Pull-Up set
PWR_PUCRE_PE11 11 Port PE11 Pull-Up set
PWR_PUCRE_PE12 12 Port PE12 Pull-Up set
PWR_PUCRE_PE13 13 Port PE13 Pull-Up set
PWR_PUCRE_PE14 14 Port PE14 Pull-Up set
PWR_PUCRE_PE15 15 Port PE15 Pull-Up set
PDCRE 0x44 32 Pull_Down control register of portE
PWR_PDCRE_PE0 0 Port PE0 Pull-Down set
PWR_PDCRE_PE1 1 Port PE1 Pull-Down set
PWR_PDCRE_PE2 2 Port PE2 Pull-Down set
PWR_PDCRE_PE3 3 Port PE3 Pull-Down set
PWR_PDCRE_PE4 4 Port PE4 Pull-Down set
PWR_PDCRE_PE5 5 Port PE5 Pull-Down set
PWR_PDCRE_PE6 6 Port PE6 Pull-Down set
PWR_PDCRE_PE7 7 Port PE7 Pull-Down set
PWR_PDCRE_PE8 8 Port PE8 Pull-Down set
PWR_PDCRE_PE9 9 Port PE9 Pull-Down set
PWR_PDCRE_PE10 10 Port PE10 Pull-Down set
PWR_PDCRE_PE11 11 Port PE11 Pull-Down set
PWR_PDCRE_PE12 12 Port PE12 Pull-Down set
PWR_PDCRE_PE13 13 Port PE13 Pull-Down set
PWR_PDCRE_PE14 14 Port PE14 Pull-Down set
PWR_PDCRE_PE15 15 Port PE15 Pull-Down set
PUCRF 0x48 32 Pull_up control register of portF
PWR_PUCRF_PF0 0 Port PF0 Pull-Up set
PWR_PUCRF_PF1 1 Port PF1 Pull-Up set
PWR_PUCRF_PF2 2 Port PF2 Pull-Up set
PWR_PUCRF_PF3 3 Port PF3 Pull-Up set
PWR_PUCRF_PF4 4 Port PF4 Pull-Up set
PWR_PUCRF_PF5 5 Port PF5 Pull-Up set
PWR_PUCRF_PF6 6 Port PF6 Pull-Up set
PWR_PUCRF_PF7 7 Port PF7 Pull-Up set
PWR_PUCRF_PF8 8 Port PF8 Pull-Up set
PWR_PUCRF_PF9 9 Port PF9 Pull-Up set
PWR_PUCRF_PF10 10 Port PF10 Pull-Up set
PWR_PUCRF_PF11 11 Port PF11 Pull-Up set
PWR_PUCRF_PF12 12 Port PF12 Pull-Up set
PWR_PUCRF_PF13 13 Port PF13 Pull-Up set
PWR_PUCRF_PF14 14 Port PF14 Pull-Up set
PWR_PUCRF_PF15 15 Port PF15 Pull-Up set
PDCRF 0x4C 32 Pull_Down control register of portF
PWR_PDCRF_PF0 0 Port PF0 Pull-Down set
PWR_PDCRF_PF1 1 Port PF1 Pull-Down set
PWR_PDCRF_PF2 2 Port PF2 Pull-Down set
PWR_PDCRF_PF3 3 Port PF3 Pull-Down set
PWR_PDCRF_PF4 4 Port PF4 Pull-Down set
PWR_PDCRF_PF5 5 Port PF5 Pull-Down set
PWR_PDCRF_PF6 6 Port PF6 Pull-Down set
PWR_PDCRF_PF7 7 Port PF7 Pull-Down set
PWR_PDCRF_PF8 8 Port PF8 Pull-Down set
PWR_PDCRF_PF9 9 Port PF9 Pull-Down set
PWR_PDCRF_PF10 10 Port PF10 Pull-Down set
PWR_PDCRF_PF11 11 Port PF11 Pull-Down set
PWR_PDCRF_PF12 12 Port PF12 Pull-Down set
PWR_PDCRF_PF13 13 Port PF13 Pull-Down set
PWR_PDCRF_PF14 14 Port PF14 Pull-Down set
PWR_PDCRF_PF15 15 Port PF15 Pull-Down set
PUCRG 0x50 32 Pull_up control register of portG
PWR_PUCRG_PG0 0 Port PG0 Pull-Up set
PWR_PUCRG_PG1 1 Port PG1 Pull-Up set
PWR_PUCRG_PG2 2 Port PG2 Pull-Up set
PWR_PUCRG_PG3 3 Port PG3 Pull-Up set
PWR_PUCRG_PG4 4 Port PG4 Pull-Up set
PWR_PUCRG_PG5 5 Port PG5 Pull-Up set
PWR_PUCRG_PG6 6 Port PG6 Pull-Up set
PWR_PUCRG_PG7 7 Port PG7 Pull-Up set
PWR_PUCRG_PG8 8 Port PG8 Pull-Up set
PWR_PUCRG_PG9 9 Port PG9 Pull-Up set
PWR_PUCRG_PG10 10 Port PG10 Pull-Up set
PWR_PUCRG_PG11 11 Port PG11 Pull-Up set
PWR_PUCRG_PG12 12 Port PG12 Pull-Up set
PWR_PUCRG_PG13 13 Port PG13 Pull-Up set
PWR_PUCRG_PG14 14 Port PG14 Pull-Up set
PWR_PUCRG_PG15 15 Port PG15 Pull-Up set
PDCRG 0x54 32 Pull_Down control register of portG
PWR_PDCRG_PG0 0 Port PG0 Pull-Down set
PWR_PDCRG_PG1 1 Port PG1 Pull-Down set
PWR_PDCRG_PG2 2 Port PG2 Pull-Down set
PWR_PDCRG_PG3 3 Port PG3 Pull-Down set
PWR_PDCRG_PG4 4 Port PG4 Pull-Down set
PWR_PDCRG_PG5 5 Port PG5 Pull-Down set
PWR_PDCRG_PG6 6 Port PG6 Pull-Down set
PWR_PDCRG_PG7 7 Port PG7 Pull-Down set
PWR_PDCRG_PG8 8 Port PG8 Pull-Down set
PWR_PDCRG_PG9 9 Port PG9 Pull-Down set
PWR_PDCRG_PG10 10 Port PG10 Pull-Down set
CR5 0x80 32 PWR power control register 5
PWR_CR5_R1MODE 8 selection for Main Regulator in Range1

FLASH — Контроллер флеш-памяти (раздел 11)

Регистр Смещение Бит Назначение
ACR 0x00 32 FLASH access control register
FLASH_ACR_LATENCY 0:3
FLASH_ACR_PRFTEN 8
FLASH_ACR_ICEN 9
FLASH_ACR_DCEN 10
FLASH_ACR_ICRST 11
FLASH_ACR_DCRST 12
FLASH_ACR_RUN_PD 13 Flash power down mode during run
FLASH_ACR_SLEEP_PD 14 Flash power down mode during sleep
FLASH_ACR_DBG_SWEN 18 Software disable for debugger
PDKEYR 0x04 32 FLASH power down key register
KEYR 0x08 32 FLASH key register
OPTKEYR 0x0C 32 FLASH option key register
SR 0x10 32 FLASH status register
FLASH_SR_EOP 0
FLASH_SR_OPERR 1
FLASH_SR_PROGERR 3
FLASH_SR_WRPERR 4
FLASH_SR_PGAERR 5
FLASH_SR_SIZERR 6
FLASH_SR_PGSERR 7
FLASH_SR_MISERR 8
FLASH_SR_FASTERR 9
FLASH_SR_RDERR 14
FLASH_SR_OPTVERR 15
FLASH_SR_BSY 16
CR 0x14 32 FLASH control register
FLASH_CR_PG 0
FLASH_CR_PER 1
FLASH_CR_MER1 2
FLASH_CR_PNB 3:9
FLASH_CR_BKER 11
FLASH_CR_MER2 15
FLASH_CR_STRT 16
FLASH_CR_OPTSTRT 17
FLASH_CR_FSTPG 18
FLASH_CR_EOPIE 24
FLASH_CR_ERRIE 25
FLASH_CR_RDERRIE 26
FLASH_CR_OBL_LAUNCH 27
FLASH_CR_SEC_PROT1 28
FLASH_CR_SEC_PROT2 29
FLASH_CR_OPTLOCK 30
FLASH_CR_LOCK 31
ECCR 0x18 32 FLASH ECC register
FLASH_ECCR_ADDR_ECC 0:18
FLASH_ECCR_BK_ECC 21
FLASH_ECCR_SYSF_ECC 22
FLASH_ECCR_ECCIE 24
FLASH_ECCR_ECCC2 28
FLASH_ECCR_ECCD2 29
FLASH_ECCR_ECCC 30
FLASH_ECCR_ECCD 31
OPTR 0x20 32 FLASH option register
FLASH_OPTR_RDP 0:7
FLASH_OPTR_BOR_LEV 8:10
FLASH_OPTR_nRST_STOP 12
FLASH_OPTR_nRST_STDBY 13
FLASH_OPTR_nRST_SHDW 14
FLASH_OPTR_IWDG_SW 16
FLASH_OPTR_IWDG_STOP 17
FLASH_OPTR_IWDG_STDBY 18
FLASH_OPTR_WWDG_SW 19
FLASH_OPTR_BFB2 20
FLASH_OPTR_DBANK 22
FLASH_OPTR_nBOOT1 23
FLASH_OPTR_SRAM_PE 24
FLASH_OPTR_CCMSRAM_RST 25
FLASH_OPTR_nSWBOOT0 26
FLASH_OPTR_nBOOT0 27
FLASH_OPTR_NRST_MODE 28:29
FLASH_OPTR_IRHEN 30
PCROP1SR 0x24 32 FLASH bank1 PCROP start address register
FLASH_PCROP1SR_PCROP1_STRT 0:14
PCROP1ER 0x28 32 FLASH bank1 PCROP end address register
FLASH_PCROP1ER_PCROP1_END 0:14
FLASH_PCROP1ER_PCROP_RDP 31
WRP1AR 0x2C 32 FLASH bank1 WRP area A address register
FLASH_WRP1AR_WRP1A_STRT 0:6
FLASH_WRP1AR_WRP1A_END 16:22
WRP1BR 0x30 32 FLASH bank1 WRP area B address register
FLASH_WRP1BR_WRP1B_STRT 0:6
FLASH_WRP1BR_WRP1B_END 16:22
PCROP2SR 0x44 32 FLASH bank2 PCROP start address register
FLASH_PCROP2SR_PCROP2_STRT 0:14
PCROP2ER 0x48 32 FLASH bank2 PCROP end address register
FLASH_PCROP2ER_PCROP2_END 0:14
WRP2AR 0x4C 32 FLASH bank2 WRP area A address register
FLASH_WRP2AR_WRP2A_STRT 0:7
FLASH_WRP2AR_WRP2A_END 16:23
WRP2BR 0x50 32 FLASH bank2 WRP area B address register
FLASH_WRP2BR_WRP2B_STRT 0:6
FLASH_WRP2BR_WRP2B_END 16:22
SEC1R 0x70 32 FLASH Securable memory register bank1
FLASH_SEC1R_SEC_SIZE1 0:7
FLASH_SEC1R_BOOT_LOCK 16
SEC2R 0x74 32 FLASH Securable memory register bank2
FLASH_SEC2R_SEC_SIZE2 0:7

IWDG — Независимый сторож (раздел 12)

Регистр Смещение Бит Назначение
KR 0x00 32 IWDG Key register
IWDG_KR_KEY 0:15 Key value (write only, read 0000h)
PR 0x04 32 IWDG Prescaler register
IWDG_PR_PR 0:2 PR[2:0] (Prescaler divider)
RLR 0x08 32 IWDG Reload register
IWDG_RLR_RL 0:11 Watchdog counter reload value
SR 0x0C 32 IWDG Status register
IWDG_SR_PVU 0 Watchdog prescaler value update
IWDG_SR_RVU 1 Watchdog counter reload value update
IWDG_SR_WVU 2 Watchdog counter window value update
WINR 0x10 32 IWDG Window register
IWDG_WINR_WIN 0:11 Watchdog counter window value

WWDG — Оконный сторож (раздел 12)

Регистр Смещение Бит Назначение
CR 0x00 32 WWDG Control register
WWDG_CR_T 0:6 T[6:0] bits (7-Bit counter (MSB to LSB))
WWDG_CR_WDGA 7 Activation bit
CFR 0x04 32 WWDG Configuration register
WWDG_CFR_W 0:6 W[6:0] bits (7-bit window value)
WWDG_CFR_EWI 9 Early Wakeup Interrupt
WWDG_CFR_WDGTB 11:13 WDGTB[2:0] bits (Timer Base)
SR 0x08 32 WWDG Status register
WWDG_SR_EWIF 0 Early Wakeup Interrupt Flag

CRC — Контрольная сумма (раздел 12)

Регистр Смещение Бит Назначение
DR 0x00 32 CRC Data register
CRC_DR_DR 0:31 Data register bits
IDR 0x04 32 CRC Independent data register
CRC_IDR_IDR 0:31 General-purpose 32-bit data register bits
CR 0x08 32 CRC Control register
CRC_CR_RESET 0 RESET the CRC computation unit bit
CRC_CR_POLYSIZE 3:4 Polynomial size bits
CRC_CR_REV_IN 5:6 REV_IN Reverse Input Data bits
CRC_CR_REV_OUT 7 REV_OUT Reverse Output Data bits
INIT 0x10 32 Initial CRC value register
CRC_INIT_INIT 0:31 Initial CRC value bits
POL 0x14 32 CRC polynomial register
CRC_POL_POL 0:31 Coefficients of the polynomial

RTC — Часы реального времени (раздел 12)

Регистр Смещение Бит Назначение
TR 0x00 32 RTC time register
RTC_TR_SU 0:3
RTC_TR_ST 4:6
RTC_TR_MNU 8:11
RTC_TR_MNT 12:14
RTC_TR_HU 16:19
RTC_TR_HT 20:21
RTC_TR_PM 22
DR 0x04 32 RTC date register
RTC_DR_DU 0:3
RTC_DR_DT 4:5
RTC_DR_MU 8:11
RTC_DR_MT 12
RTC_DR_WDU 13:15
RTC_DR_YU 16:19
RTC_DR_YT 20:23
SSR 0x08 32 RTC sub second register
RTC_SSR_SS 0:15
ICSR 0x0C 32 RTC initialization control and status register
RTC_ICSR_ALRAWF 0
RTC_ICSR_ALRBWF 1
RTC_ICSR_WUTWF 2
RTC_ICSR_SHPF 3
RTC_ICSR_INITS 4
RTC_ICSR_RSF 5
RTC_ICSR_INITF 6
RTC_ICSR_INIT 7
RTC_ICSR_RECALPF 16
PRER 0x10 32 RTC prescaler register
RTC_PRER_PREDIV_S 0:14
RTC_PRER_PREDIV_A 16:22
WUTR 0x14 32 RTC wakeup timer register
RTC_WUTR_WUT 0:15
CR 0x18 32 RTC control register
RTC_CR_WUCKSEL 0:2
RTC_CR_TSEDGE 3
RTC_CR_REFCKON 4
RTC_CR_BYPSHAD 5
RTC_CR_FMT 6
RTC_CR_ALRAE 8
RTC_CR_ALRBE 9
RTC_CR_WUTE 10
RTC_CR_TSE 11
RTC_CR_ALRAIE 12
RTC_CR_ALRBIE 13
RTC_CR_WUTIE 14
RTC_CR_TSIE 15
RTC_CR_ADD1H 16
RTC_CR_SUB1H 17
RTC_CR_BKP 18
RTC_CR_COSEL 19
RTC_CR_POL 20
RTC_CR_OSEL 21:22
RTC_CR_COE 23
RTC_CR_ITSE 24 Timestamp on internal event enable
RTC_CR_TAMPTS 25 Activate timestamp on tamper detection event
RTC_CR_TAMPOE 26 Tamper detection output enable on TAMPALARM
RTC_CR_TAMPALRM_PU 29 TAMPALARM output pull-up config
RTC_CR_TAMPALRM_TYPE 30 TAMPALARM output type
RTC_CR_OUT2EN 31 RTC_OUT2 output enable
WPR 0x24 32 RTC write protection register
RTC_WPR_KEY 0:7
CALR 0x28 32 RTC calibration register
RTC_CALR_CALM 0:8
RTC_CALR_CALW16 13
RTC_CALR_CALW8 14
RTC_CALR_CALP 15
SHIFTR 0x2C 32 RTC shift control register
RTC_SHIFTR_SUBFS 0:14
RTC_SHIFTR_ADD1S 31
TSTR 0x30 32 RTC time stamp time register
RTC_TSTR_SU 0:3
RTC_TSTR_ST 4:6
RTC_TSTR_MNU 8:11
RTC_TSTR_MNT 12:14
RTC_TSTR_HU 16:19
RTC_TSTR_HT 20:21
RTC_TSTR_PM 22
TSDR 0x34 32 RTC time stamp date register
RTC_TSDR_DU 0:3
RTC_TSDR_DT 4:5
RTC_TSDR_MU 8:11
RTC_TSDR_MT 12
RTC_TSDR_WDU 13:15
TSSSR 0x38 32 RTC time-stamp sub second register
RTC_TSSSR_SS 0:15
ALRMAR 0x40 32 RTC alarm A register
RTC_ALRMAR_SU 0:3
RTC_ALRMAR_ST 4:6
RTC_ALRMAR_MSK1 7
RTC_ALRMAR_MNU 8:11
RTC_ALRMAR_MNT 12:14
RTC_ALRMAR_MSK2 15
RTC_ALRMAR_HU 16:19
RTC_ALRMAR_HT 20:21
RTC_ALRMAR_PM 22
RTC_ALRMAR_MSK3 23
RTC_ALRMAR_DU 24:27
RTC_ALRMAR_DT 28:29
RTC_ALRMAR_WDSEL 30
RTC_ALRMAR_MSK4 31
ALRMASSR 0x44 32 RTC alarm A sub second register
RTC_ALRMASSR_SS 0:14
RTC_ALRMASSR_MASKSS 24:27
ALRMBR 0x48 32 RTC alarm B register
RTC_ALRMBR_SU 0:3
RTC_ALRMBR_ST 4:6
RTC_ALRMBR_MSK1 7
RTC_ALRMBR_MNU 8:11
RTC_ALRMBR_MNT 12:14
RTC_ALRMBR_MSK2 15
RTC_ALRMBR_HU 16:19
RTC_ALRMBR_HT 20:21
RTC_ALRMBR_PM 22
RTC_ALRMBR_MSK3 23
RTC_ALRMBR_DU 24:27
RTC_ALRMBR_DT 28:29
RTC_ALRMBR_WDSEL 30
RTC_ALRMBR_MSK4 31
ALRMBSSR 0x4C 32 RTC alarm B sub second register
RTC_ALRMBSSR_SS 0:14
RTC_ALRMBSSR_MASKSS 24:27
SR 0x50 32 RTC Status register
RTC_SR_ALRAF 0
RTC_SR_ALRBF 1
RTC_SR_WUTF 2
RTC_SR_TSF 3
RTC_SR_TSOVF 4
RTC_SR_ITSF 5
MISR 0x54 32 RTC Masked Interrupt Status register
RTC_MISR_ALRAMF 0
RTC_MISR_ALRBMF 1
RTC_MISR_WUTMF 2
RTC_MISR_TSMF 3
RTC_MISR_TSOVMF 4
RTC_MISR_ITSMF 5
SCR 0x5C 32 RTC Status Clear register
RTC_SCR_CALRAF 0
RTC_SCR_CALRBF 1
RTC_SCR_CWUTF 2
RTC_SCR_CTSF 3
RTC_SCR_CTSOVF 4
RTC_SCR_CITSF 5

TAMP — Вскрытие корпуса и резервные регистры (раздел 12)

Регистр Смещение Бит Назначение
CR1 0x00 32 TAMP configuration register 1
TAMP_CR1_TAMP1E 0
TAMP_CR1_TAMP2E 1
TAMP_CR1_TAMP3E 2
TAMP_CR1_ITAMP3E 18
TAMP_CR1_ITAMP4E 19
TAMP_CR1_ITAMP5E 20
TAMP_CR1_ITAMP6E 21
CR2 0x04 32 TAMP configuration register 2
TAMP_CR2_TAMP1NOERASE 0
TAMP_CR2_TAMP2NOERASE 1
TAMP_CR2_TAMP3NOERASE 2
TAMP_CR2_TAMP1MF 16
TAMP_CR2_TAMP2MF 17
TAMP_CR2_TAMP3MF 18
TAMP_CR2_TAMP1TRG 24
TAMP_CR2_TAMP2TRG 25
TAMP_CR2_TAMP3TRG 26
FLTCR 0x0C 32 TAMP filter control register
TAMP_FLTCR_TAMPFREQ 0:2
TAMP_FLTCR_TAMPFLT 3:4
TAMP_FLTCR_TAMPPRCH 5:6
TAMP_FLTCR_TAMPPUDIS 7
IER 0x2C 32 TAMP Interrupt enable register
TAMP_IER_TAMP1IE 0
TAMP_IER_TAMP2IE 1
TAMP_IER_TAMP3IE 2
TAMP_IER_ITAMP3IE 18
TAMP_IER_ITAMP4IE 19
TAMP_IER_ITAMP5IE 20
TAMP_IER_ITAMP6IE 21
SR 0x30 32 TAMP Status register
TAMP_SR_TAMP1F 0
TAMP_SR_TAMP2F 1
TAMP_SR_TAMP3F 2
TAMP_SR_ITAMP3F 18
TAMP_SR_ITAMP4F 19
TAMP_SR_ITAMP5F 20
TAMP_SR_ITAMP6F 21
MISR 0x34 32 TAMP Masked Interrupt Status register
TAMP_MISR_TAMP1MF 0
TAMP_MISR_TAMP2MF 1
TAMP_MISR_TAMP3MF 2
TAMP_MISR_ITAMP3MF 18
TAMP_MISR_ITAMP4MF 19
TAMP_MISR_ITAMP5MF 20
TAMP_MISR_ITAMP6MF 21
SCR 0x3C 32 TAMP Status clear register
TAMP_SCR_CTAMP1F 0
TAMP_SCR_CTAMP2F 1
TAMP_SCR_CTAMP3F 2
TAMP_SCR_CITAMP3F 18
TAMP_SCR_CITAMP4F 19
TAMP_SCR_CITAMP5F 20
TAMP_SCR_CITAMP6F 21
BKP0R 0x100 32 TAMP backup register 0
BKP1R 0x104 32 TAMP backup register 1
BKP2R 0x108 32 TAMP backup register 2
BKP3R 0x10C 32 TAMP backup register 3
BKP4R 0x110 32 TAMP backup register 4
BKP5R 0x114 32 TAMP backup register 5
BKP6R 0x118 32 TAMP backup register 6
BKP7R 0x11C 32 TAMP backup register 7
BKP8R 0x120 32 TAMP backup register 8
BKP9R 0x124 32 TAMP backup register 9
BKP10R 0x128 32 TAMP backup register 10
BKP11R 0x12C 32 TAMP backup register 11
BKP12R 0x130 32 TAMP backup register 12
BKP13R 0x134 32 TAMP backup register 13
BKP14R 0x138 32 TAMP backup register 14
BKP15R 0x13C 32 TAMP backup register 15
BKP16R 0x140 32 TAMP backup register 16
BKP17R 0x144 32 TAMP backup register 17
BKP18R 0x148 32 TAMP backup register 18
BKP19R 0x14C 32 TAMP backup register 19
BKP20R 0x150 32 TAMP backup register 20
BKP21R 0x154 32 TAMP backup register 21
BKP22R 0x158 32 TAMP backup register 22
BKP23R 0x15C 32 TAMP backup register 23
BKP24R 0x160 32 TAMP backup register 24
BKP25R 0x164 32 TAMP backup register 25
BKP26R 0x168 32 TAMP backup register 26
BKP27R 0x16C 32 TAMP backup register 27
BKP28R 0x170 32 TAMP backup register 28
BKP29R 0x174 32 TAMP backup register 29
BKP30R 0x178 32 TAMP backup register 30
BKP31R 0x17C 32 TAMP backup register 31

TIM — Таймеры (раздел 13)

Регистр Смещение Бит Назначение
CR1 0x00 32 TIM control register 1
TIM_CR1_CEN 0 Counter enable
TIM_CR1_UDIS 1 Update disable
TIM_CR1_URS 2 Update request source
TIM_CR1_OPM 3 One pulse mode
TIM_CR1_DIR 4 Direction
TIM_CR1_CMS 5:6 CMS[1:0] bits (Center-aligned mode selection)
TIM_CR1_ARPE 7 Auto-reload preload enable
TIM_CR1_CKD 8:9 CKD[1:0] bits (clock division)
TIM_CR1_UIFREMAP 11 Update interrupt flag remap
TIM_CR1_DITHEN 12 Dithering enable
CR2 0x04 32 TIM control register 2
TIM_CR2_CCPC 0 Capture/Compare Preloaded Control
TIM_CR2_CCUS 2 Capture/Compare Control Update Selection
TIM_CR2_CCDS 3 Capture/Compare DMA Selection
TIM_CR2_MMS 4:25 MMS[3:0] bits (Master Mode Selection)
TIM_CR2_TI1S 7 TI1 Selection
TIM_CR2_OIS1 8 Output Idle state 1 (OC1 output)
TIM_CR2_OIS1N 9 Output Idle state 1 (OC1N output)
TIM_CR2_OIS2 10 Output Idle state 2 (OC2 output)
TIM_CR2_OIS2N 11 Output Idle state 2 (OC2N output)
TIM_CR2_OIS3 12 Output Idle state 3 (OC3 output)
TIM_CR2_OIS3N 13 Output Idle state 3 (OC3N output)
TIM_CR2_OIS4 14 Output Idle state 4 (OC4 output)
TIM_CR2_OIS4N 15 Output Idle state 4 (OC4N output)
TIM_CR2_OIS5 16 Output Idle state 5 (OC5 output)
TIM_CR2_OIS6 18 Output Idle state 6 (OC6 output)
TIM_CR2_MMS2 20:23 MMS[2:0] bits (Master Mode Selection)
SMCR 0x08 32 TIM slave mode control register
TIM_SMCR_SMS 0:16 SMS[2:0] bits (Slave mode selection)
TIM_SMCR_OCCS 3 OCREF clear selection
TIM_SMCR_TS 4:21 TS[2:0] bits (Trigger selection)
TIM_SMCR_MSM 7 Master/slave mode
TIM_SMCR_ETF 8:11 ETF[3:0] bits (External trigger filter)
TIM_SMCR_ETPS 12:13 ETPS[1:0] bits (External trigger prescaler)
TIM_SMCR_ECE 14 External clock enable
TIM_SMCR_ETP 15 External trigger polarity
TIM_SMCR_SMSPE 25 SMS preload enable
TIM_SMCR_SMSPS 26 SMS preload source
DIER 0x0C 32 TIM DMA/interrupt enable register
TIM_DIER_UIE 0 Update interrupt enable
TIM_DIER_CC1IE 1 Capture/Compare 1 interrupt enable
TIM_DIER_CC2IE 2 Capture/Compare 2 interrupt enable
TIM_DIER_CC3IE 3 Capture/Compare 3 interrupt enable
TIM_DIER_CC4IE 4 Capture/Compare 4 interrupt enable
TIM_DIER_COMIE 5 COM interrupt enable
TIM_DIER_TIE 6 Trigger interrupt enable
TIM_DIER_BIE 7 Break interrupt enable
TIM_DIER_UDE 8 Update DMA request enable
TIM_DIER_CC1DE 9 Capture/Compare 1 DMA request enable
TIM_DIER_CC2DE 10 Capture/Compare 2 DMA request enable
TIM_DIER_CC3DE 11 Capture/Compare 3 DMA request enable
TIM_DIER_CC4DE 12 Capture/Compare 4 DMA request enable
TIM_DIER_COMDE 13 COM DMA request enable
TIM_DIER_TDE 14 Trigger DMA request enable
TIM_DIER_IDXIE 20 Encoder index interrupt enable
TIM_DIER_DIRIE 21 Encoder direction change interrupt enable
TIM_DIER_IERRIE 22 Encoder index error enable
TIM_DIER_TERRIE 23 Encoder transition error enable
SR 0x10 32 TIM status register
TIM_SR_UIF 0 Update interrupt Flag
TIM_SR_CC1IF 1 Capture/Compare 1 interrupt Flag
TIM_SR_CC2IF 2 Capture/Compare 2 interrupt Flag
TIM_SR_CC3IF 3 Capture/Compare 3 interrupt Flag
TIM_SR_CC4IF 4 Capture/Compare 4 interrupt Flag
TIM_SR_COMIF 5 COM interrupt Flag
TIM_SR_TIF 6 Trigger interrupt Flag
TIM_SR_BIF 7 Break interrupt Flag
TIM_SR_B2IF 8 Break 2 interrupt Flag
TIM_SR_CC1OF 9 Capture/Compare 1 Overcapture Flag
TIM_SR_CC2OF 10 Capture/Compare 2 Overcapture Flag
TIM_SR_CC3OF 11 Capture/Compare 3 Overcapture Flag
TIM_SR_CC4OF 12 Capture/Compare 4 Overcapture Flag
TIM_SR_SBIF 13 System Break interrupt Flag
TIM_SR_CC5IF 16 Capture/Compare 5 interrupt Flag
TIM_SR_CC6IF 17 Capture/Compare 6 interrupt Flag
TIM_SR_IDXF 20 Encoder index interrupt flag
TIM_SR_DIRF 21 Encoder direction change interrupt flag
TIM_SR_IERRF 22 Encoder index error flag
TIM_SR_TERRF 23 Encoder transition error flag
EGR 0x14 32 TIM event generation register
TIM_EGR_UG 0 Update Generation
TIM_EGR_CC1G 1 Capture/Compare 1 Generation
TIM_EGR_CC2G 2 Capture/Compare 2 Generation
TIM_EGR_CC3G 3 Capture/Compare 3 Generation
TIM_EGR_CC4G 4 Capture/Compare 4 Generation
TIM_EGR_COMG 5 Capture/Compare Control Update Generation
TIM_EGR_TG 6 Trigger Generation
TIM_EGR_BG 7 Break Generation
TIM_EGR_B2G 8 Break 2 Generation
CCMR1 0x18 32 TIM capture/compare mode register 1
TIM_CCMR1_CC1S 0:1 CC1S[1:0] bits (Capture/Compare 1 Selection)
TIM_CCMR1_OC1FE 2 Output Compare 1 Fast enable
TIM_CCMR1_IC1PSC 2:3 IC1PSC[1:0] bits (Input Capture 1 Prescaler)
TIM_CCMR1_OC1PE 3 Output Compare 1 Preload enable
TIM_CCMR1_OC1M 4:16 OC1M[2:0] bits (Output Compare 1 Mode)
TIM_CCMR1_IC1F 4:7 IC1F[3:0] bits (Input Capture 1 Filter)
TIM_CCMR1_OC1CE 7 Output Compare 1 Clear Enable
TIM_CCMR1_CC2S 8:9 CC2S[1:0] bits (Capture/Compare 2 Selection)
TIM_CCMR1_OC2FE 10 Output Compare 2 Fast enable
TIM_CCMR1_IC2PSC 10:11 IC2PSC[1:0] bits (Input Capture 2 Prescaler)
TIM_CCMR1_OC2PE 11 Output Compare 2 Preload enable
TIM_CCMR1_OC2M 12:24 OC2M[2:0] bits (Output Compare 2 Mode)
TIM_CCMR1_IC2F 12:15 IC2F[3:0] bits (Input Capture 2 Filter)
TIM_CCMR1_OC2CE 15 Output Compare 2 Clear Enable
CCMR2 0x1C 32 TIM capture/compare mode register 2
TIM_CCMR2_CC3S 0:1 CC3S[1:0] bits (Capture/Compare 3 Selection)
TIM_CCMR2_OC3FE 2 Output Compare 3 Fast enable
TIM_CCMR2_IC3PSC 2:3 IC3PSC[1:0] bits (Input Capture 3 Prescaler)
TIM_CCMR2_OC3PE 3 Output Compare 3 Preload enable
TIM_CCMR2_OC3M 4:16 OC3M[2:0] bits (Output Compare 3 Mode)
TIM_CCMR2_IC3F 4:7 IC3F[3:0] bits (Input Capture 3 Filter)
TIM_CCMR2_OC3CE 7 Output Compare 3 Clear Enable
TIM_CCMR2_CC4S 8:9 CC4S[1:0] bits (Capture/Compare 4 Selection)
TIM_CCMR2_OC4FE 10 Output Compare 4 Fast enable
TIM_CCMR2_IC4PSC 10:11 IC4PSC[1:0] bits (Input Capture 4 Prescaler)
TIM_CCMR2_OC4PE 11 Output Compare 4 Preload enable
TIM_CCMR2_OC4M 12:24 OC4M[2:0] bits (Output Compare 4 Mode)
TIM_CCMR2_IC4F 12:15 IC4F[3:0] bits (Input Capture 4 Filter)
TIM_CCMR2_OC4CE 15 Output Compare 4 Clear Enable
CCER 0x20 32 TIM capture/compare enable register
TIM_CCER_CC1E 0 Capture/Compare 1 output enable
TIM_CCER_CC1P 1 Capture/Compare 1 output Polarity
TIM_CCER_CC1NE 2 Capture/Compare 1 Complementary output enable
TIM_CCER_CC1NP 3 Capture/Compare 1 Complementary output Polarity
TIM_CCER_CC2E 4 Capture/Compare 2 output enable
TIM_CCER_CC2P 5 Capture/Compare 2 output Polarity
TIM_CCER_CC2NE 6 Capture/Compare 2 Complementary output enable
TIM_CCER_CC2NP 7 Capture/Compare 2 Complementary output Polarity
TIM_CCER_CC3E 8 Capture/Compare 3 output enable
TIM_CCER_CC3P 9 Capture/Compare 3 output Polarity
TIM_CCER_CC3NE 10 Capture/Compare 3 Complementary output enable
TIM_CCER_CC3NP 11 Capture/Compare 3 Complementary output Polarity
TIM_CCER_CC4E 12 Capture/Compare 4 output enable
TIM_CCER_CC4P 13 Capture/Compare 4 output Polarity
TIM_CCER_CC4NE 14 Capture/Compare 4 Complementary output enable
TIM_CCER_CC4NP 15 Capture/Compare 4 Complementary output Polarity
TIM_CCER_CC5E 16 Capture/Compare 5 output enable
TIM_CCER_CC5P 17 Capture/Compare 5 output Polarity
TIM_CCER_CC6E 20 Capture/Compare 6 output enable
TIM_CCER_CC6P 21 Capture/Compare 6 output Polarity
CNT 0x24 32 TIM counter register
TIM_CNT_CNT 0:31 Counter Value
TIM_CNT_UIFCPY 31 Update interrupt flag copy (if UIFREMAP=1)
PSC 0x28 32 TIM prescaler
TIM_PSC_PSC 0:15 Prescaler Value
ARR 0x2C 32 TIM auto-reload register
TIM_ARR_ARR 0:31 Actual auto-reload Value
RCR 0x30 32 TIM repetition counter register
TIM_RCR_REP 0:15 Repetition Counter Value
CCR1 0x34 32 TIM capture/compare register 1
TIM_CCR1_CCR1 0:15 Capture/Compare 1 Value
CCR2 0x38 32 TIM capture/compare register 2
TIM_CCR2_CCR2 0:15 Capture/Compare 2 Value
CCR3 0x3C 32 TIM capture/compare register 3
TIM_CCR3_CCR3 0:15 Capture/Compare 3 Value
CCR4 0x40 32 TIM capture/compare register 4
TIM_CCR4_CCR4 0:15 Capture/Compare 4 Value
BDTR 0x44 32 TIM break and dead-time register
TIM_BDTR_DTG 0:7 DTG[0:7] bits (Dead-Time Generator set-up)
TIM_BDTR_LOCK 8:9 LOCK[1:0] bits (Lock Configuration)
TIM_BDTR_OSSI 10 Off-State Selection for Idle mode
TIM_BDTR_OSSR 11 Off-State Selection for Run mode
TIM_BDTR_BKE 12 Break enable for Break 1
TIM_BDTR_BKP 13 Break Polarity for Break 1
TIM_BDTR_AOE 14 Automatic Output enable
TIM_BDTR_MOE 15 Main Output enable
TIM_BDTR_BKF 16:19 Break Filter for Break 1
TIM_BDTR_BK2F 20:23 Break Filter for Break 2
TIM_BDTR_BK2E 24 Break enable for Break 2
TIM_BDTR_BK2P 25 Break Polarity for Break 2
TIM_BDTR_BKDSRM 26 Break disarming/re-arming
TIM_BDTR_BK2DSRM 27 Break2 disarming/re-arming
TIM_BDTR_BKBID 28 Break BIDirectional
TIM_BDTR_BK2BID 29 Break2 BIDirectional
CCR5 0x48 32 TIM capture/compare register 5
TIM_CCR5_CCR5 0:31 Capture/Compare 5 Value
TIM_CCR5_GC5C1 29 Group Channel 5 and Channel 1
TIM_CCR5_GC5C2 30 Group Channel 5 and Channel 2
TIM_CCR5_GC5C3 31 Group Channel 5 and Channel 3
CCR6 0x4C 32 TIM capture/compare register 6
TIM_CCR6_CCR6 0:15 Capture/Compare 6 Value
CCMR3 0x50 32 TIM capture/compare mode register 3
TIM_CCMR3_OC5FE 2 Output Compare 5 Fast enable
TIM_CCMR3_OC5PE 3 Output Compare 5 Preload enable
TIM_CCMR3_OC5M 4:16 OC5M[3:0] bits (Output Compare 5 Mode)
TIM_CCMR3_OC5CE 7 Output Compare 5 Clear Enable
TIM_CCMR3_OC6FE 10 Output Compare 6 Fast enable
TIM_CCMR3_OC6PE 11 Output Compare 6 Preload enable
TIM_CCMR3_OC6M 12:24 OC6M[3:0] bits (Output Compare 6 Mode)
TIM_CCMR3_OC6CE 15 Output Compare 6 Clear Enable
DTR2 0x54 32 TIM deadtime register 2
TIM_DTR2_DTGF 0:3 DTGF[7:0] bits (Deadtime falling edge generator setup)
TIM_DTR2_DTAE 14 Deadtime asymmetric enable
TIM_DTR2_DTPE 15 Deadtime prelaod enable
ECR 0x58 32 TIM encoder control register
TIM_ECR_IE 0 Index enable
TIM_ECR_IDIR 1:2 IDIR[1:0] bits (Index direction)
TIM_ECR_FIDX 5 First index enable
TIM_ECR_IPOS 6:7 IPOS[1:0] bits (Index positioning)
TIM_ECR_PW 16:23 PW[7:0] bits (Pulse width)
TIM_ECR_PWPRSC 24:26 PWPRSC[2:0] bits (Pulse width prescaler)
TISEL 0x5C 32 TIM Input Selection register
TIM_TISEL_TI1SEL 0:3 TI1SEL[3:0] bits (TIM1 TI1 SEL)
TIM_TISEL_TI2SEL 8:11 TI2SEL[3:0] bits (TIM1 TI2 SEL)
TIM_TISEL_TI3SEL 16:19 TI3SEL[3:0] bits (TIM1 TI3 SEL)
TIM_TISEL_TI4SEL 24:27 TI4SEL[3:0] bits (TIM1 TI4 SEL)
AF1 0x60 32 TIM alternate function option register 1
AF2 0x64 32 TIM alternate function option register 2
OR 0x68 32 TIM option register
TIM_OR_HSE32EN 0 HSE/32 clock enable
DCR 0x3DC 32 TIM DMA control register
TIM_DCR_DBA 0:4 DBA[4:0] bits (DMA Base Address)
TIM_DCR_DBL 8:12 DBL[4:0] bits (DMA Burst Length)
DMAR 0x3E0 32 TIM DMA address for full transfer
TIM_DMAR_DMAB 0:31 DMA register for burst accesses

LPTIM — Таймер с малым потреблением (раздел 46)

Регистр Смещение Бит Назначение
ISR 0x00 32 LPTIM Interrupt and Status register
LPTIM_ISR_CMPM 0 Compare match
LPTIM_ISR_ARRM 1 Autoreload match
LPTIM_ISR_EXTTRIG 2 External trigger edge event
LPTIM_ISR_CMPOK 3 Compare register update OK
LPTIM_ISR_ARROK 4 Autoreload register update OK
LPTIM_ISR_UP 5 Counter direction change down to up
LPTIM_ISR_DOWN 6 Counter direction change up to down
ICR 0x04 32 LPTIM Interrupt Clear register
LPTIM_ICR_CMPMCF 0 Compare match Clear Flag
LPTIM_ICR_ARRMCF 1 Autoreload match Clear Flag
LPTIM_ICR_EXTTRIGCF 2 External trigger edge event Clear Flag
LPTIM_ICR_CMPOKCF 3 Compare register update OK Clear Flag
LPTIM_ICR_ARROKCF 4 Autoreload register update OK Clear Flag
LPTIM_ICR_UPCF 5 Counter direction change down to up Clear Flag
LPTIM_ICR_DOWNCF 6 Counter direction change up to down Clear Flag
IER 0x08 32 LPTIM Interrupt Enable register
LPTIM_IER_CMPMIE 0 Compare match Interrupt Enable
LPTIM_IER_ARRMIE 1 Autoreload match Interrupt Enable
LPTIM_IER_EXTTRIGIE 2 External trigger edge event Interrupt Enable
LPTIM_IER_CMPOKIE 3 Compare register update OK Interrupt Enable
LPTIM_IER_ARROKIE 4 Autoreload register update OK Interrupt Enable
LPTIM_IER_UPIE 5 Counter direction change down to up Interrupt Enable
LPTIM_IER_DOWNIE 6 Counter direction change up to down Interrupt Enable
CFGR 0x0C 32 LPTIM Configuration register
LPTIM_CFGR_CKSEL 0 Clock selector
LPTIM_CFGR_CKPOL 1:2 CKPOL[1:0] bits (Clock polarity)
LPTIM_CFGR_CKFLT 3:4 CKFLT[1:0] bits (Configurable digital filter for external clock)
LPTIM_CFGR_TRGFLT 6:7 TRGFLT[1:0] bits (Configurable digital filter for trigger)
LPTIM_CFGR_PRESC 9:11 PRESC[2:0] bits (Clock prescaler)
LPTIM_CFGR_TRIGSEL 13:25 TRIGSEL[2:0]] bits (Trigger selector)
LPTIM_CFGR_TRIGEN 17:18 TRIGEN[1:0] bits (Trigger enable and polarity)
LPTIM_CFGR_TIMOUT 19 Timout enable
LPTIM_CFGR_WAVE 20 Waveform shape
LPTIM_CFGR_WAVPOL 21 Waveform shape polarity
LPTIM_CFGR_PRELOAD 22 Reg update mode
LPTIM_CFGR_COUNTMODE 23 Counter mode enable
LPTIM_CFGR_ENC 24 Encoder mode enable
CR 0x10 32 LPTIM Control register
LPTIM_CR_ENABLE 0 LPTIMer enable
LPTIM_CR_SNGSTRT 1 Timer start in single mode
LPTIM_CR_CNTSTRT 2 Timer start in continuous mode
LPTIM_CR_COUNTRST 3 Counter reset
LPTIM_CR_RSTARE 4 Reset after read enable
CMP 0x14 32 LPTIM Compare register
LPTIM_CMP_CMP 0:15 Compare register
ARR 0x18 32 LPTIM Autoreload register
LPTIM_ARR_ARR 0:15 Auto reload register
CNT 0x1C 32 LPTIM Counter register
LPTIM_CNT_CNT 0:15 Counter register
OR 0x20 32 LPTIM Option register
LPTIM_OR_IN1 0:3 IN1[2:0] bits (Remap selection)
LPTIM_OR_IN2 1:5 IN2[2:0] bits (Remap selection)

ADC — АЦП (раздел 14)

Регистр Смещение Бит Назначение
ISR 0x00 32 ADC interrupt and status register
ADC_ISR_ADRDY 0 ADC ready flag
ADC_ISR_EOSMP 1 ADC group regular end of sampling flag
ADC_ISR_EOC 2 ADC group regular end of unitary conversion flag
ADC_ISR_EOS 3 ADC group regular end of sequence conversions flag
ADC_ISR_OVR 4 ADC group regular overrun flag
ADC_ISR_JEOC 5 ADC group injected end of unitary conversion flag
ADC_ISR_JEOS 6 ADC group injected end of sequence conversions flag
ADC_ISR_AWD1 7 ADC analog watchdog 1 flag
ADC_ISR_AWD2 8 ADC analog watchdog 2 flag
ADC_ISR_AWD3 9 ADC analog watchdog 3 flag
ADC_ISR_JQOVF 10 ADC group injected contexts queue overflow flag
IER 0x04 32 ADC interrupt enable register
ADC_IER_ADRDYIE 0 ADC ready interrupt
ADC_IER_EOSMPIE 1 ADC group regular end of sampling interrupt
ADC_IER_EOCIE 2 ADC group regular end of unitary conversion interrupt
ADC_IER_EOSIE 3 ADC group regular end of sequence conversions interrupt
ADC_IER_OVRIE 4 ADC group regular overrun interrupt
ADC_IER_JEOCIE 5 ADC group injected end of unitary conversion interrupt
ADC_IER_JEOSIE 6 ADC group injected end of sequence conversions interrupt
ADC_IER_AWD1IE 7 ADC analog watchdog 1 interrupt
ADC_IER_AWD2IE 8 ADC analog watchdog 2 interrupt
ADC_IER_AWD3IE 9 ADC analog watchdog 3 interrupt
ADC_IER_JQOVFIE 10 ADC group injected contexts queue overflow interrupt
CR 0x08 32 ADC control register
ADC_CR_ADEN 0 ADC enable
ADC_CR_ADDIS 1 ADC disable
ADC_CR_ADSTART 2 ADC group regular conversion start
ADC_CR_JADSTART 3 ADC group injected conversion start
ADC_CR_ADSTP 4 ADC group regular conversion stop
ADC_CR_JADSTP 5 ADC group injected conversion stop
ADC_CR_ADVREGEN 28 ADC voltage regulator enable
ADC_CR_DEEPPWD 29 ADC deep power down enable
ADC_CR_ADCALDIF 30 ADC differential mode for calibration
ADC_CR_ADCAL 31 ADC calibration
CFGR 0x0C 32 ADC configuration register 1
ADC_CFGR_DMAEN 0 ADC DMA transfer enable
ADC_CFGR_DMACFG 1 ADC DMA transfer configuration
ADC_CFGR_RES 3:4 ADC data resolution
ADC_CFGR_EXTSEL 5:9 ADC group regular external trigger source
ADC_CFGR_EXTEN 10:11 ADC group regular external trigger polarity
ADC_CFGR_OVRMOD 12 ADC group regular overrun configuration
ADC_CFGR_CONT 13 ADC group regular continuous conversion mode
ADC_CFGR_AUTDLY 14 ADC low power auto wait
ADC_CFGR_ALIGN 15 ADC data alignment
ADC_CFGR_DISCEN 16 ADC group regular sequencer discontinuous mode
ADC_CFGR_DISCNUM 17:19 ADC group regular sequencer discontinuous number of ranks
ADC_CFGR_JDISCEN 20 ADC group injected sequencer discontinuous mode
ADC_CFGR_JQM 21 ADC group injected contexts queue mode
ADC_CFGR_AWD1SGL 22 ADC analog watchdog 1 monitoring a single channel or all channels
ADC_CFGR_AWD1EN 23 ADC analog watchdog 1 enable on scope ADC group regular
ADC_CFGR_JAWD1EN 24 ADC analog watchdog 1 enable on scope ADC group injected
ADC_CFGR_JAUTO 25 ADC group injected automatic trigger mode
ADC_CFGR_AWD1CH 26:30 ADC analog watchdog 1 monitored channel selection
ADC_CFGR_JQDIS 31 ADC group injected contexts queue disable
CFGR2 0x10 32 ADC configuration register 2
ADC_CFGR2_ROVSE 0 ADC oversampler enable on scope ADC group regular
ADC_CFGR2_JOVSE 1 ADC oversampler enable on scope ADC group injected
ADC_CFGR2_OVSR 2:4 ADC oversampling ratio
ADC_CFGR2_OVSS 5:8 ADC oversampling shift
ADC_CFGR2_TROVS 9 ADC oversampling discontinuous mode (triggered mode) for ADC group regular
ADC_CFGR2_ROVSM 10 ADC oversampling mode managing interlaced conversions of ADC group regular and group injected
ADC_CFGR2_GCOMP 16 ADC Gain Compensation mode
ADC_CFGR2_SWTRIG 25 ADC Software Trigger Bit for Sample time control trigger mode
ADC_CFGR2_BULB 26 ADC Bulb sampling mode
ADC_CFGR2_SMPTRIG 27 ADC Sample Time Control Trigger mode
SMPR1 0x14 32 ADC sampling time register 1
ADC_SMPR1_SMP0 0:2 ADC channel 0 sampling time selection
ADC_SMPR1_SMP1 3:5 ADC channel 1 sampling time selection
ADC_SMPR1_SMP2 6:8 ADC channel 2 sampling time selection
ADC_SMPR1_SMP3 9:11 ADC channel 3 sampling time selection
ADC_SMPR1_SMP4 12:14 ADC channel 4 sampling time selection
ADC_SMPR1_SMP5 15:17 ADC channel 5 sampling time selection
ADC_SMPR1_SMP6 18:20 ADC channel 6 sampling time selection
ADC_SMPR1_SMP7 21:23 ADC channel 7 sampling time selection
ADC_SMPR1_SMP8 24:26 ADC channel 8 sampling time selection
ADC_SMPR1_SMP9 27:29 ADC channel 9 sampling time selection
ADC_SMPR1_SMPPLUS 31 ADC channels sampling time additional setting
SMPR2 0x18 32 ADC sampling time register 2
ADC_SMPR2_SMP10 0:2 ADC channel 10 sampling time selection
ADC_SMPR2_SMP11 3:5 ADC channel 11 sampling time selection
ADC_SMPR2_SMP12 6:8 ADC channel 12 sampling time selection
ADC_SMPR2_SMP13 9:11 ADC channel 13 sampling time selection
ADC_SMPR2_SMP14 12:14 ADC channel 14 sampling time selection
ADC_SMPR2_SMP15 15:17 ADC channel 15 sampling time selection
ADC_SMPR2_SMP16 18:20 ADC channel 16 sampling time selection
ADC_SMPR2_SMP17 21:23 ADC channel 17 sampling time selection
ADC_SMPR2_SMP18 24:26 ADC channel 18 sampling time selection
TR1 0x20 32 ADC analog watchdog 1 threshold register
ADC_TR1_LT1 0:11 ADC analog watchdog 1 threshold low
ADC_TR1_AWDFILT 12:14 ADC analog watchdog filtering parameter
ADC_TR1_HT1 16:27 ADC analog watchdog 1 threshold high
TR2 0x24 32 ADC analog watchdog 2 threshold register
ADC_TR2_LT2 0:7 ADC analog watchdog 2 threshold low
ADC_TR2_HT2 16:23 ADC analog watchdog 2 threshold high
TR3 0x28 32 ADC analog watchdog 3 threshold register
ADC_TR3_LT3 0:7 ADC analog watchdog 3 threshold low
ADC_TR3_HT3 16:23 ADC analog watchdog 3 threshold high
SQR1 0x30 32 ADC group regular sequencer register 1
ADC_SQR1_L 0:3 ADC group regular sequencer scan length
ADC_SQR1_SQ1 6:10 ADC group regular sequencer rank 1
ADC_SQR1_SQ2 12:16 ADC group regular sequencer rank 2
ADC_SQR1_SQ3 18:22 ADC group regular sequencer rank 3
ADC_SQR1_SQ4 24:28 ADC group regular sequencer rank 4
SQR2 0x34 32 ADC group regular sequencer register 2
ADC_SQR2_SQ5 0:4 ADC group regular sequencer rank 5
ADC_SQR2_SQ6 6:10 ADC group regular sequencer rank 6
ADC_SQR2_SQ7 12:16 ADC group regular sequencer rank 7
ADC_SQR2_SQ8 18:22 ADC group regular sequencer rank 8
ADC_SQR2_SQ9 24:28 ADC group regular sequencer rank 9
SQR3 0x38 32 ADC group regular sequencer register 3
ADC_SQR3_SQ10 0:4 ADC group regular sequencer rank 10
ADC_SQR3_SQ11 6:10 ADC group regular sequencer rank 11
ADC_SQR3_SQ12 12:16 ADC group regular sequencer rank 12
ADC_SQR3_SQ13 18:22 ADC group regular sequencer rank 13
ADC_SQR3_SQ14 24:28 ADC group regular sequencer rank 14
SQR4 0x3C 32 ADC group regular sequencer register 4
ADC_SQR4_SQ15 0:4 ADC group regular sequencer rank 15
ADC_SQR4_SQ16 6:10 ADC group regular sequencer rank 16
DR 0x40 32 ADC group regular data register
ADC_DR_RDATA 0:15 ADC group regular conversion data
JSQR 0x4C 32 ADC group injected sequencer register
ADC_JSQR_JL 0:1 ADC group injected sequencer scan length
ADC_JSQR_JEXTSEL 2:6 ADC group injected external trigger source
ADC_JSQR_JEXTEN 7:8 ADC group injected external trigger polarity
ADC_JSQR_JSQ1 9:13 ADC group injected sequencer rank 1
ADC_JSQR_JSQ2 14:18 ADC group injected sequencer rank 2
ADC_JSQR_JSQ3 21:25 ADC group injected sequencer rank 3
ADC_JSQR_JSQ4 27:31 ADC group injected sequencer rank 4
OFR1 0x60 32 ADC offset register 1
ADC_OFR1_OFFSET1 0:11 ADC offset number 1 offset level
ADC_OFR1_OFFSETPOS 24 ADC offset number 1 positive
ADC_OFR1_SATEN 25 ADC offset number 1 saturation enable
ADC_OFR1_OFFSET1_CH 26:30 ADC offset number 1 channel selection
ADC_OFR1_OFFSET1_EN 31 ADC offset number 1 enable
OFR2 0x64 32 ADC offset register 2
ADC_OFR2_OFFSET2 0:11 ADC offset number 2 offset level
ADC_OFR2_OFFSETPOS 24 ADC offset number 2 positive
ADC_OFR2_SATEN 25 ADC offset number 2 saturation enable
ADC_OFR2_OFFSET2_CH 26:30 ADC offset number 2 channel selection
ADC_OFR2_OFFSET2_EN 31 ADC offset number 2 enable
OFR3 0x68 32 ADC offset register 3
ADC_OFR3_OFFSET3 0:11 ADC offset number 3 offset level
ADC_OFR3_OFFSETPOS 24 ADC offset number 3 positive
ADC_OFR3_SATEN 25 ADC offset number 3 saturation enable
ADC_OFR3_OFFSET3_CH 26:30 ADC offset number 3 channel selection
ADC_OFR3_OFFSET3_EN 31 ADC offset number 3 enable
OFR4 0x6C 32 ADC offset register 4
ADC_OFR4_OFFSET4 0:11 ADC offset number 4 offset level
ADC_OFR4_OFFSETPOS 24 ADC offset number 4 positive
ADC_OFR4_SATEN 25 ADC offset number 4 saturation enable
ADC_OFR4_OFFSET4_CH 26:30 ADC offset number 4 channel selection
ADC_OFR4_OFFSET4_EN 31 ADC offset number 4 enable
JDR1 0x80 32 ADC group injected rank 1 data register
ADC_JDR1_JDATA 0:15 ADC group injected sequencer rank 1 conversion data
JDR2 0x84 32 ADC group injected rank 2 data register
ADC_JDR2_JDATA 0:15 ADC group injected sequencer rank 2 conversion data
JDR3 0x88 32 ADC group injected rank 3 data register
ADC_JDR3_JDATA 0:15 ADC group injected sequencer rank 3 conversion data
JDR4 0x8C 32 ADC group injected rank 4 data register
ADC_JDR4_JDATA 0:15 ADC group injected sequencer rank 4 conversion data
AWD2CR 0xA0 32 ADC analog watchdog 2 configuration register
ADC_AWD2CR_AWD2CH 0:18 ADC analog watchdog 2 monitored channel selection
AWD3CR 0xA4 32 ADC analog watchdog 3 Configuration Register
ADC_AWD3CR_AWD3CH 0:18 ADC analog watchdog 3 monitored channel selection
DIFSEL 0xB0 32 ADC differential mode selection register
ADC_DIFSEL_DIFSEL 0:18 ADC channel differential or single-ended mode
CALFACT 0xB4 32 ADC calibration factors
ADC_CALFACT_CALFACT_S 0:6 ADC calibration factor in single-ended mode
ADC_CALFACT_CALFACT_D 16:22 ADC calibration factor in differential mode
GCOMP 0xC0 32 ADC calibration factors
ADC_GCOMP_GCOMPCOEFF 0:13 ADC Gain Compensation Coefficient

ADC_Common — АЦП: общие регистры (раздел 14)

Регистр Смещение Бит Назначение
CSR 0x00 32 ADC common status register
ADC_CSR_ADRDY_MST 0 ADC multimode master ready flag
ADC_CSR_EOSMP_MST 1 ADC multimode master group regular end of sampling flag
ADC_CSR_EOC_MST 2 ADC multimode master group regular end of unitary conversion flag
ADC_CSR_EOS_MST 3 ADC multimode master group regular end of sequence conversions flag
ADC_CSR_OVR_MST 4 ADC multimode master group regular overrun flag
ADC_CSR_JEOC_MST 5 ADC multimode master group injected end of unitary conversion flag
ADC_CSR_JEOS_MST 6 ADC multimode master group injected end of sequence conversions flag
ADC_CSR_AWD1_MST 7 ADC multimode master analog watchdog 1 flag
ADC_CSR_AWD2_MST 8 ADC multimode master analog watchdog 2 flag
ADC_CSR_AWD3_MST 9 ADC multimode master analog watchdog 3 flag
ADC_CSR_JQOVF_MST 10 ADC multimode master group injected contexts queue overflow flag
ADC_CSR_ADRDY_SLV 16 ADC multimode slave ready flag
ADC_CSR_EOSMP_SLV 17 ADC multimode slave group regular end of sampling flag
ADC_CSR_EOC_SLV 18 ADC multimode slave group regular end of unitary conversion flag
ADC_CSR_EOS_SLV 19 ADC multimode slave group regular end of sequence conversions flag
ADC_CSR_OVR_SLV 20 ADC multimode slave group regular overrun flag
ADC_CSR_JEOC_SLV 21 ADC multimode slave group injected end of unitary conversion flag
ADC_CSR_JEOS_SLV 22 ADC multimode slave group injected end of sequence conversions flag
ADC_CSR_AWD1_SLV 23 ADC multimode slave analog watchdog 1 flag
ADC_CSR_AWD2_SLV 24 ADC multimode slave analog watchdog 2 flag
ADC_CSR_AWD3_SLV 25 ADC multimode slave analog watchdog 3 flag
ADC_CSR_JQOVF_SLV 26 ADC multimode slave group injected contexts queue overflow flag
CCR 0x08 32 ADC common configuration register
ADC_CCR_DUAL 0:4 ADC multimode mode selection
ADC_CCR_DELAY 8:11 ADC multimode delay between 2 sampling phases
ADC_CCR_DMACFG 13 ADC multimode DMA transfer configuration
ADC_CCR_MDMA 14:15 ADC multimode DMA transfer enable
ADC_CCR_CKMODE 16:17 ADC common clock source and prescaler (prescaler only for clock source synchronous)
ADC_CCR_PRESC 18:21 ADC common clock prescaler, only for clock source asynchronous
ADC_CCR_VREFEN 22 ADC internal path to VrefInt enable
ADC_CCR_VSENSESEL 23 ADC internal path to temperature sensor enable
ADC_CCR_VBATSEL 24 ADC internal path to battery voltage enable
CDR 0x0C 32 ADC common group regular data register
ADC_CDR_RDATA_MST 0:15 ADC multimode master group regular conversion data
ADC_CDR_RDATA_SLV 16:31 ADC multimode slave group regular conversion data

DAC — ЦАП (раздел 15)

Регистр Смещение Бит Назначение
CR 0x00 32 DAC control register
DAC_CR_EN1 0 DAC channel1 enable
DAC_CR_TEN1 1 DAC channel1 Trigger enable
DAC_CR_TSEL1 2:5 TSEL1[3:0] (DAC channel1 Trigger selection)
DAC_CR_WAVE1 6:7 WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
DAC_CR_MAMP1 8:11 MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
DAC_CR_DMAEN1 12 DAC channel1 DMA enable
DAC_CR_DMAUDRIE1 13 DAC channel 1 DMA underrun interrupt enable >
DAC_CR_CEN1 14 DAC channel 1 calibration enable >
DAC_CR_HFSEL 15 DAC channel 1 and 2 high frequency mode enable >
DAC_CR_EN2 16 DAC channel2 enable
DAC_CR_TEN2 17 DAC channel2 Trigger enable
DAC_CR_TSEL2 18:21 TSEL2[3:0] (DAC channel2 Trigger selection)
DAC_CR_WAVE2 22:23 WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)
DAC_CR_MAMP2 24:27 MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)
DAC_CR_DMAEN2 28 DAC channel2 DMA enabled
DAC_CR_DMAUDRIE2 29 DAC channel2 DMA underrun interrupt enable >
DAC_CR_CEN2 30 DAC channel2 calibration enable >
SWTRIGR 0x04 32 DAC software trigger register
DAC_SWTRIGR_SWTRIG1 0 DAC channel1 software trigger
DAC_SWTRIGR_SWTRIG2 1 DAC channel2 software trigger
DAC_SWTRIGR_SWTRIGB1 16 DAC channel1 software trigger B
DAC_SWTRIGR_SWTRIGB2 17 DAC channel2 software trigger B
DHR12R1 0x08 32 DAC channel1 12-bit right-aligned data holding register
DAC_DHR12R1_DACC1DHR 0:11 DAC channel1 12-bit Right aligned data
DAC_DHR12R1_DACC1DHRB 16:27 DAC channel1 12-bit Right-aligned data B
DHR12L1 0x0C 32 DAC channel1 12-bit left aligned data holding register
DAC_DHR12L1_DACC1DHR 4:15 DAC channel1 12-bit Left aligned data
DAC_DHR12L1_DACC1DHRB 20:31 DAC channel1 12-bit Left aligned data B
DHR8R1 0x10 32 DAC channel1 8-bit right aligned data holding register
DAC_DHR8R1_DACC1DHR 0:7 DAC channel1 8-bit Right aligned data
DAC_DHR8R1_DACC1DHRB 8:15 DAC channel1 8-bit Right aligned data B
DHR12R2 0x14 32 DAC channel2 12-bit right aligned data holding register
DAC_DHR12R2_DACC2DHR 0:11 DAC channel2 12-bit Right aligned data
DAC_DHR12R2_DACC2DHRB 16:27 DAC channel2 12-bit Right-aligned data B
DHR12L2 0x18 32 DAC channel2 12-bit left aligned data holding register
DAC_DHR12L2_DACC2DHR 4:15 DAC channel2 12-bit Left aligned data
DAC_DHR12L2_DACC2DHRB 20:31 DAC channel2 12-bit Left aligned data B
DHR8R2 0x1C 32 DAC channel2 8-bit right-aligned data holding register
DAC_DHR8R2_DACC2DHR 0:7 DAC channel2 8-bit Right aligned data
DAC_DHR8R2_DACC2DHRB 8:15 DAC channel2 8-bit Right aligned data B
DHR12RD 0x20 32 Dual DAC 12-bit right-aligned data holding register
DAC_DHR12RD_DACC1DHR 0:11 DAC channel1 12-bit Right aligned data
DAC_DHR12RD_DACC2DHR 16:27 DAC channel2 12-bit Right aligned data
DHR12LD 0x24 32 DUAL DAC 12-bit left aligned data holding register
DAC_DHR12LD_DACC1DHR 4:15 DAC channel1 12-bit Left aligned data
DAC_DHR12LD_DACC2DHR 20:31 DAC channel2 12-bit Left aligned data
DHR8RD 0x28 32 DUAL DAC 8-bit right aligned data holding register
DAC_DHR8RD_DACC1DHR 0:7 DAC channel1 8-bit Right aligned data
DAC_DHR8RD_DACC2DHR 8:15 DAC channel2 8-bit Right aligned data
DOR1 0x2C 32 DAC channel1 data output register
DAC_DOR1_DACC1DOR 0:11 DAC channel1 data output
DAC_DOR1_DACC1DORB 16:27 DAC channel1 data output B
DOR2 0x30 32 DAC channel2 data output register
DAC_DOR2_DACC2DOR 0:11 DAC channel2 data output
DAC_DOR2_DACC2DORB 16:27 DAC channel2 data output B
SR 0x34 32 DAC status register
DAC_SR_DAC1RDY 11 DAC channel 1 ready status bit
DAC_SR_DORSTAT1 12 DAC channel 1 output register status bit
DAC_SR_DMAUDR1 13 DAC channel1 DMA underrun flag
DAC_SR_CAL_FLAG1 14 DAC channel1 calibration offset status
DAC_SR_BWST1 15 DAC channel1 busy writing sample time flag
DAC_SR_DAC2RDY 27 DAC channel 2 ready status bit
DAC_SR_DORSTAT2 28 DAC channel 2 output register status bit
DAC_SR_DMAUDR2 29 DAC channel2 DMA underrun flag
DAC_SR_CAL_FLAG2 30 DAC channel2 calibration offset status
DAC_SR_BWST2 31 DAC channel2 busy writing sample time flag
CCR 0x38 32 DAC calibration control register
DAC_CCR_OTRIM1 0:4 DAC channel1 offset trimming value
DAC_CCR_OTRIM2 16:20 DAC channel2 offset trimming value
MCR 0x3C 32 DAC mode control register
DAC_MCR_MODE1 0:2 MODE1[2:0] (DAC channel1 mode)
DAC_MCR_DMADOUBLE1 8 DAC Channel 1 DMA double data mode
DAC_MCR_SINFORMAT1 9 DAC Channel 1 enable signed format
DAC_MCR_HFSEL 14:15 HFSEL[1:0] (High Frequency interface mode selection)
DAC_MCR_MODE2 16:18 MODE2[2:0] (DAC channel2 mode)
DAC_MCR_DMADOUBLE2 24 DAC Channel 2 DMA double data mode
DAC_MCR_SINFORMAT2 25 DAC Channel 2 enable signed format
SHSR1 0x40 32 DAC Sample and Hold sample time register 1
DAC_SHSR1_TSAMPLE1 0:9 DAC channel1 sample time
SHSR2 0x44 32 DAC Sample and Hold sample time register 2
DAC_SHSR2_TSAMPLE2 0:9 DAC channel2 sample time
SHHR 0x48 32 DAC Sample and Hold hold time register
DAC_SHHR_THOLD1 0:9 DAC channel1 hold time
DAC_SHHR_THOLD2 16:25 DAC channel2 hold time
SHRR 0x4C 32 DAC Sample and Hold refresh time register
DAC_SHRR_TREFRESH1 0:7 DAC channel1 refresh time
DAC_SHRR_TREFRESH2 16:23 DAC channel2 refresh time
STR1 0x58 32 DAC Sawtooth register
DAC_STR1_STRSTDATA1 0:11 DAC Channel 1 Sawtooth starting value
DAC_STR1_STDIR1 12 DAC Channel 1 Sawtooth direction setting
DAC_STR1_STINCDATA1 16:31 DAC Channel 1 Sawtooth increment value (12.4 bit format)
STR2 0x5C 32 DAC Sawtooth register
DAC_STR2_STRSTDATA2 0:11 DAC Channel 2 Sawtooth starting value
DAC_STR2_STDIR2 12 DAC Channel 2 Sawtooth direction setting
DAC_STR2_STINCDATA2 16:31 DAC Channel 2 Sawtooth increment value (12.4 bit format)
STMODR 0x60 32 DAC Sawtooth Mode register
DAC_STMODR_STRSTTRIGSEL1 0:3 STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection)
DAC_STMODR_STINCTRIGSEL1 0:3 STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection)
DAC_STMODR_STRSTTRIGSEL2 0:3 STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection)
DAC_STMODR_STINCTRIGSEL2 0:3 STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection)

COMP — Компаратор (раздел 44)

Регистр Смещение Бит Назначение
CSR 0x00 32 COMP control and status register
COMP_CSR_EN 0 Comparator enable
COMP_CSR_INMSEL 4:6 Comparator input minus selection
COMP_CSR_INPSEL 8 Comparator input plus selection
COMP_CSR_POLARITY 15 Comparator output polarity
COMP_CSR_HYST 16:18 Comparator hysteresis
COMP_CSR_BLANKING 19:21 Comparator blanking source
COMP_CSR_BRGEN 22 Comparator scaler bridge enable
COMP_CSR_SCALEN 23 Comparator voltage scaler enable
COMP_CSR_VALUE 30 Comparator output level
COMP_CSR_LOCK 31 Comparator lock

OPAMP — Операционный усилитель (раздел 44)

Регистр Смещение Бит Назначение
CSR 0x00 32 OPAMP control/status register
OPAMP_CSR_OPAMPxEN 0 OPAMP enable
OPAMP_CSR_FORCEVP 1 Connect the internal references to the plus input of the OPAMPX
OPAMP_CSR_VPSEL 2:3 Non inverting input selection
OPAMP_CSR_USERTRIM 4 User trimming enable
OPAMP_CSR_VMSEL 5:6 Inverting input selection
OPAMP_CSR_HIGHSPEEDEN 7 High speed mode enable
OPAMP_CSR_OPAMPINTEN 8 Internal output enable
OPAMP_CSR_CALON 11 Calibration mode enable
OPAMP_CSR_CALSEL 12:13 Calibration selection
OPAMP_CSR_PGGAIN 14:18 Gain in PGA mode
OPAMP_CSR_TRIMOFFSETP 19:23 Offset trimming value (PMOS)
OPAMP_CSR_TRIMOFFSETN 24:28 Offset trimming value (NMOS)
OPAMP_CSR_OUTCAL 30 OPAMP output status flag
OPAMP_CSR_LOCK 31 OPAMP control/status register lock
TCMR 0x18 32 OPAMP timer controlled mux mode register
OPAMP_TCMR_VMSSEL 0 Secondary inverting input selection
OPAMP_TCMR_VPSSEL 1:2 Secondary non inverting input selection
OPAMP_TCMR_T1CMEN 3 Timer 1 controlled mux mode enable
OPAMP_TCMR_T8CMEN 4 Timer 8 controlled mux mode enable
OPAMP_TCMR_T20CMEN 5 Timer 20 controlled mux mode enable
OPAMP_TCMR_LOCK 31 OPAMP SW control register lock

USART — UART / USART / LPUART (раздел 16)

Регистр Смещение Бит Назначение
CR1 0x00 32 USART Control register 1
USART_CR1_UE 0 USART Enable
USART_CR1_UESM 1 USART Enable in STOP Mode
USART_CR1_RE 2 Receiver Enable
USART_CR1_TE 3 Transmitter Enable
USART_CR1_IDLEIE 4 IDLE Interrupt Enable
USART_CR1_RXNEIE 5 RXNE Interrupt Enable
USART_CR1_TCIE 6 Transmission Complete Interrupt Enable
USART_CR1_TXEIE 7 TXE Interrupt Enable
USART_CR1_PEIE 8 PE Interrupt Enable
USART_CR1_PS 9 Parity Selection
USART_CR1_PCE 10 Parity Control Enable
USART_CR1_WAKE 11 Receiver Wakeup method
USART_CR1_M 12:28 Word length
USART_CR1_M0 12 Word length - Bit 0
USART_CR1_MME 13 Mute Mode Enable
USART_CR1_CMIE 14 Character match interrupt enable
USART_CR1_OVER8 15 Oversampling by 8-bit or 16-bit mode
USART_CR1_DEDT 16:20 DEDT[4:0] bits (Driver Enable Deassertion Time)
USART_CR1_DEAT 21:25 DEAT[4:0] bits (Driver Enable Assertion Time)
USART_CR1_RTOIE 26 Receive Time Out interrupt enable
USART_CR1_EOBIE 27 End of Block interrupt enable
USART_CR1_M1 28 Word length - Bit 1
USART_CR1_FIFOEN 29 FIFO mode enable
USART_CR1_TXFEIE 30 TXFIFO empty interrupt enable
USART_CR1_RXFFIE 31 RXFIFO Full interrupt enable
CR2 0x04 32 USART Control register 2
USART_CR2_SLVEN 0 Synchronous Slave mode enable
USART_CR2_DIS_NSS 3 Slave Select (NSS) pin management
USART_CR2_ADDM7 4 7-bit or 4-bit Address Detection
USART_CR2_LBDL 5 LIN Break Detection Length
USART_CR2_LBDIE 6 LIN Break Detection Interrupt Enable
USART_CR2_LBCL 8 Last Bit Clock pulse
USART_CR2_CPHA 9 Clock Phase
USART_CR2_CPOL 10 Clock Polarity
USART_CR2_CLKEN 11 Clock Enable
USART_CR2_STOP 12:13 STOP[1:0] bits (STOP bits)
USART_CR2_LINEN 14 LIN mode enable
USART_CR2_SWAP 15 SWAP TX/RX pins
USART_CR2_RXINV 16 RX pin active level inversion
USART_CR2_TXINV 17 TX pin active level inversion
USART_CR2_DATAINV 18 Binary data inversion
USART_CR2_MSBFIRST 19 Most Significant Bit First
USART_CR2_ABREN 20 Auto Baud-Rate Enable
USART_CR2_ABRMODE 21:22 ABRMOD[1:0] bits (Auto Baud-Rate Mode)
USART_CR2_RTOEN 23 Receiver Time-Out enable
USART_CR2_ADD 24:31 Address of the USART node
CR3 0x08 32 USART Control register 3
USART_CR3_EIE 0 Error Interrupt Enable
USART_CR3_IREN 1 IrDA mode Enable
USART_CR3_IRLP 2 IrDA Low-Power
USART_CR3_HDSEL 3 Half-Duplex Selection
USART_CR3_NACK 4 SmartCard NACK enable
USART_CR3_SCEN 5 SmartCard mode enable
USART_CR3_DMAR 6 DMA Enable Receiver
USART_CR3_DMAT 7 DMA Enable Transmitter
USART_CR3_RTSE 8 RTS Enable
USART_CR3_CTSE 9 CTS Enable
USART_CR3_CTSIE 10 CTS Interrupt Enable
USART_CR3_ONEBIT 11 One sample bit method enable
USART_CR3_OVRDIS 12 Overrun Disable
USART_CR3_DDRE 13 DMA Disable on Reception Error
USART_CR3_DEM 14 Driver Enable Mode
USART_CR3_DEP 15 Driver Enable Polarity Selection
USART_CR3_SCARCNT 17:19 SCARCNT[2:0] bits (SmartCard Auto-Retry Count)
USART_CR3_WUS 20:21 WUS[1:0] bits (Wake UP Interrupt Flag Selection)
USART_CR3_WUFIE 22 Wake Up Interrupt Enable
USART_CR3_TXFTIE 23 TXFIFO threshold interrupt enable
USART_CR3_TCBGTIE 24 Transmission Complete Before Guard Time Interrupt Enable
USART_CR3_RXFTCFG 25:27 RXFIFO FIFO threshold configuration
USART_CR3_RXFTIE 28 RXFIFO threshold interrupt enable
USART_CR3_TXFTCFG 29:31 TXFIFO threshold configuration
BRR 0x0C 32 USART Baud rate register
USART_BRR_LPUART 0:19 LPUART Baud rate register [19:0]
USART_BRR_BRR 0:15 USART Baud rate register [15:0]
GTPR 0x10 32 USART Guard time and prescaler register
USART_GTPR_PSC 0:7 PSC[7:0] bits (Prescaler value)
USART_GTPR_GT 8:15 GT[7:0] bits (Guard time value)
RTOR 0x14 32 USART Receiver Timeout register
USART_RTOR_RTO 0:23 Receiver Time Out Value
USART_RTOR_BLEN 24:31 Block Length
RQR 0x18 32 USART Request register
USART_RQR_ABRRQ 0 Auto-Baud Rate Request
USART_RQR_SBKRQ 1 Send Break Request
USART_RQR_MMRQ 2 Mute Mode Request
USART_RQR_RXFRQ 3 Receive Data flush Request
USART_RQR_TXFRQ 4 Transmit data flush Request
ISR 0x1C 32 USART Interrupt and status register
USART_ISR_PE 0 Parity Error
USART_ISR_FE 1 Framing Error
USART_ISR_NE 2 Noise detected Flag
USART_ISR_ORE 3 OverRun Error
USART_ISR_IDLE 4 IDLE line detected
USART_ISR_RXNE 5 Read Data Register Not Empty
USART_ISR_TC 6 Transmission Complete
USART_ISR_TXE 7 Transmit Data Register Empty
USART_ISR_LBDF 8 LIN Break Detection Flag
USART_ISR_CTSIF 9 CTS interrupt flag
USART_ISR_CTS 10 CTS flag
USART_ISR_RTOF 11 Receiver Time Out
USART_ISR_EOBF 12 End Of Block Flag
USART_ISR_UDR 13 SPI slave underrun error flag
USART_ISR_ABRE 14 Auto-Baud Rate Error
USART_ISR_ABRF 15 Auto-Baud Rate Flag
USART_ISR_BUSY 16 Busy Flag
USART_ISR_CMF 17 Character Match Flag
USART_ISR_SBKF 18 Send Break Flag
USART_ISR_RWU 19 Receive Wake Up from mute mode Flag
USART_ISR_WUF 20 Wake Up from stop mode Flag
USART_ISR_TEACK 21 Transmit Enable Acknowledge Flag
USART_ISR_REACK 22 Receive Enable Acknowledge Flag
USART_ISR_TXFE 23 TXFIFO Empty
USART_ISR_RXFF 24 RXFIFO Full
USART_ISR_TCBGT 25 Transmission Complete Before Guard Time completion
USART_ISR_RXFT 26 RXFIFO threshold flag
USART_ISR_TXFT 27 TXFIFO threshold flag
ICR 0x20 32 USART Interrupt flag Clear register
USART_ICR_PECF 0 Parity Error Clear Flag
USART_ICR_FECF 1 Framing Error Clear Flag
USART_ICR_NECF 2 Noise detected Clear Flag
USART_ICR_ORECF 3 OverRun Error Clear Flag
USART_ICR_IDLECF 4 IDLE line detected Clear Flag
USART_ICR_TXFECF 5 TXFIFO empty Clear flag
USART_ICR_TCCF 6 Transmission Complete Clear Flag
USART_ICR_TCBGTCF 7 Transmission Complete Before Guard Time Clear Flag
USART_ICR_LBDCF 8 LIN Break Detection Clear Flag
USART_ICR_CTSCF 9 CTS Interrupt Clear Flag
USART_ICR_RTOCF 11 Receiver Time Out Clear Flag
USART_ICR_EOBCF 12 End Of Block Clear Flag
USART_ICR_UDRCF 13 SPI Slave Underrun Clear Flag
USART_ICR_CMCF 17 Character Match Clear Flag
USART_ICR_WUCF 20 Wake Up from stop mode Clear Flag
RDR 0x24 32 USART Receive Data register
USART_RDR_RDR 0:8 RDR[8:0] bits (Receive Data value)
TDR 0x28 32 USART Transmit Data register
USART_TDR_TDR 0:8 TDR[8:0] bits (Transmit Data value)
PRESC 0x2C 32 USART Prescaler register
USART_PRESC_PRESCALER 0:3 PRESCALER[3:0] bits (Clock prescaler)

I2C — I²C (раздел 17)

Регистр Смещение Бит Назначение
CR1 0x00 32 I2C Control register 1
I2C_CR1_PE 0 Peripheral enable
I2C_CR1_TXIE 1 TX interrupt enable
I2C_CR1_RXIE 2 RX interrupt enable
I2C_CR1_ADDRIE 3 Address match interrupt enable
I2C_CR1_NACKIE 4 NACK received interrupt enable
I2C_CR1_STOPIE 5 STOP detection interrupt enable
I2C_CR1_TCIE 6 Transfer complete interrupt enable
I2C_CR1_ERRIE 7 Errors interrupt enable
I2C_CR1_DNF 8:11 Digital noise filter
I2C_CR1_ANFOFF 12 Analog noise filter OFF
I2C_CR1_SWRST 13 Software reset
I2C_CR1_TXDMAEN 14 DMA transmission requests enable
I2C_CR1_RXDMAEN 15 DMA reception requests enable
I2C_CR1_SBC 16 Slave byte control
I2C_CR1_NOSTRETCH 17 Clock stretching disable
I2C_CR1_WUPEN 18 Wakeup from STOP enable
I2C_CR1_GCEN 19 General call enable
I2C_CR1_SMBHEN 20 SMBus host address enable
I2C_CR1_SMBDEN 21 SMBus device default address enable
I2C_CR1_ALERTEN 22 SMBus alert enable
I2C_CR1_PECEN 23 PEC enable
CR2 0x04 32 I2C Control register 2
I2C_CR2_SADD 0:9 Slave address (master mode)
I2C_CR2_RD_WRN 10 Transfer direction (master mode)
I2C_CR2_ADD10 11 10-bit addressing mode (master mode)
I2C_CR2_HEAD10R 12 10-bit address header only read direction (master mode)
I2C_CR2_START 13 START generation
I2C_CR2_STOP 14 STOP generation (master mode)
I2C_CR2_NACK 15 NACK generation (slave mode)
I2C_CR2_NBYTES 16:23 Number of bytes
I2C_CR2_RELOAD 24 NBYTES reload mode
I2C_CR2_AUTOEND 25 Automatic end mode (master mode)
I2C_CR2_PECBYTE 26 Packet error checking byte
OAR1 0x08 32 I2C Own address 1 register
I2C_OAR1_OA1 0:9 Interface own address 1
I2C_OAR1_OA1MODE 10 Own address 1 10-bit mode
I2C_OAR1_OA1EN 15 Own address 1 enable
OAR2 0x0C 32 I2C Own address 2 register
I2C_OAR2_OA2 1:7 Interface own address 2
I2C_OAR2_OA2MSK 8:10 Own address 2 masks
I2C_OAR2_OA2MASK01 8 OA2[1] is masked, Only OA2[7:2] are compared
I2C_OAR2_OA2MASK03 8:9 OA2[3:1] is masked, Only OA2[7:4] are compared
I2C_OAR2_OA2MASK05 8:10 OA2[5:1] is masked, Only OA2[7:6] are compared
I2C_OAR2_OA2MASK07 8:10 OA2[7:1] is masked, No comparison is done
I2C_OAR2_OA2MASK02 9 OA2[2:1] is masked, Only OA2[7:3] are compared
I2C_OAR2_OA2MASK06 9:10 OA2[6:1] is masked, Only OA2[7] are compared
I2C_OAR2_OA2MASK04 10 OA2[4:1] is masked, Only OA2[7:5] are compared
I2C_OAR2_OA2EN 15 Own address 2 enable
TIMINGR 0x10 32 I2C Timing register
I2C_TIMINGR_SCLL 0:7 SCL low period (master mode)
I2C_TIMINGR_SCLH 8:15 SCL high period (master mode)
I2C_TIMINGR_SDADEL 16:19 Data hold time
I2C_TIMINGR_SCLDEL 20:23 Data setup time
I2C_TIMINGR_PRESC 28:31 Timings prescaler
TIMEOUTR 0x14 32 I2C Timeout register
I2C_TIMEOUTR_TIMEOUTA 0:11 Bus timeout A
I2C_TIMEOUTR_TIDLE 12 Idle clock timeout detection
I2C_TIMEOUTR_TIMOUTEN 15 Clock timeout enable
I2C_TIMEOUTR_TIMEOUTB 16:27 Bus timeout B
I2C_TIMEOUTR_TEXTEN 31 Extended clock timeout enable
ISR 0x18 32 I2C Interrupt and status register
I2C_ISR_TXE 0 Transmit data register empty
I2C_ISR_TXIS 1 Transmit interrupt status
I2C_ISR_RXNE 2 Receive data register not empty
I2C_ISR_ADDR 3 Address matched (slave mode)
I2C_ISR_NACKF 4 NACK received flag
I2C_ISR_STOPF 5 STOP detection flag
I2C_ISR_TC 6 Transfer complete (master mode)
I2C_ISR_TCR 7 Transfer complete reload
I2C_ISR_BERR 8 Bus error
I2C_ISR_ARLO 9 Arbitration lost
I2C_ISR_OVR 10 Overrun/Underrun
I2C_ISR_PECERR 11 PEC error in reception
I2C_ISR_TIMEOUT 12 Timeout or Tlow detection flag
I2C_ISR_ALERT 13 SMBus alert
I2C_ISR_BUSY 15 Bus busy
I2C_ISR_DIR 16 Transfer direction (slave mode)
I2C_ISR_ADDCODE 17:23 Address match code (slave mode)
ICR 0x1C 32 I2C Interrupt clear register
I2C_ICR_ADDRCF 3 Address matched clear flag
I2C_ICR_NACKCF 4 NACK clear flag
I2C_ICR_STOPCF 5 STOP detection clear flag
I2C_ICR_BERRCF 8 Bus error clear flag
I2C_ICR_ARLOCF 9 Arbitration lost clear flag
I2C_ICR_OVRCF 10 Overrun/Underrun clear flag
I2C_ICR_PECCF 11 PAC error clear flag
I2C_ICR_TIMOUTCF 12 Timeout clear flag
I2C_ICR_ALERTCF 13 Alert clear flag
PECR 0x20 32 I2C PEC register
I2C_PECR_PEC 0:7 PEC register
RXDR 0x24 32 I2C Receive data register
I2C_RXDR_RXDATA 0:7 8-bit receive data
TXDR 0x28 32 I2C Transmit data register
I2C_TXDR_TXDATA 0:7 8-bit transmit data

SPI — SPI / I²S (раздел 18)

Регистр Смещение Бит Назначение
CR1 0x00 32 SPI Control register 1
SPI_CR1_CPHA 0 Clock Phase
SPI_CR1_CPOL 1 Clock Polarity
SPI_CR1_MSTR 2 Master Selection
SPI_CR1_BR 3:5 BR[2:0] bits (Baud Rate Control)
SPI_CR1_SPE 6 SPI Enable
SPI_CR1_LSBFIRST 7 Frame Format
SPI_CR1_SSI 8 Internal slave select
SPI_CR1_SSM 9 Software slave management
SPI_CR1_RXONLY 10 Receive only
SPI_CR1_CRCL 11 CRC Length
SPI_CR1_CRCNEXT 12 Transmit CRC next
SPI_CR1_CRCEN 13 Hardware CRC calculation enable
SPI_CR1_BIDIOE 14 Output enable in bidirectional mode
SPI_CR1_BIDIMODE 15 Bidirectional data mode enable
CR2 0x04 32 SPI Control register 2
SPI_CR2_RXDMAEN 0 Rx Buffer DMA Enable
SPI_CR2_TXDMAEN 1 Tx Buffer DMA Enable
SPI_CR2_SSOE 2 SS Output Enable
SPI_CR2_NSSP 3 NSS pulse management Enable
SPI_CR2_FRF 4 Frame Format Enable
SPI_CR2_ERRIE 5 Error Interrupt Enable
SPI_CR2_RXNEIE 6 RX buffer Not Empty Interrupt Enable
SPI_CR2_TXEIE 7 Tx buffer Empty Interrupt Enable
SPI_CR2_DS 8:11 DS[3:0] Data Size
SPI_CR2_FRXTH 12 FIFO reception Threshold
SPI_CR2_LDMARX 13 Last DMA transfer for reception
SPI_CR2_LDMATX 14 Last DMA transfer for transmission
SR 0x08 32 SPI Status register
SPI_SR_RXNE 0 Receive buffer Not Empty
SPI_SR_TXE 1 Transmit buffer Empty
SPI_SR_CHSIDE 2 Channel side
SPI_SR_UDR 3 Underrun flag
SPI_SR_CRCERR 4 CRC Error flag
SPI_SR_MODF 5 Mode fault
SPI_SR_OVR 6 Overrun flag
SPI_SR_BSY 7 Busy flag
SPI_SR_FRE 8 TI frame format error
SPI_SR_FRLVL 9:10 FIFO Reception Level
SPI_SR_FTLVL 11:12 FIFO Transmission Level
DR 0x0C 32 SPI data register
SPI_DR_DR 0:15 Data Register
CRCPR 0x10 32 SPI CRC polynomial register
SPI_CRCPR_CRCPOLY 0:15 CRC polynomial register
RXCRCR 0x14 32 SPI Rx CRC register
SPI_RXCRCR_RXCRC 0:15 Rx CRC Register
TXCRCR 0x18 32 SPI Tx CRC register
SPI_TXCRCR_TXCRC 0:15 Tx CRC Register
I2SCFGR 0x1C 32 SPI_I2S configuration register
SPI_I2SCFGR_CHLEN 0 Channel length (number of bits per audio channel)
SPI_I2SCFGR_DATLEN 1:2 DATLEN[1:0] bits (Data length to be transferred)
SPI_I2SCFGR_CKPOL 3 steady state clock polarity
SPI_I2SCFGR_I2SSTD 4:5 I2SSTD[1:0] bits (I2S standard selection)
SPI_I2SCFGR_PCMSYNC 7 PCM frame synchronization
SPI_I2SCFGR_I2SCFG 8:9 I2SCFG[1:0] bits (I2S configuration mode)
SPI_I2SCFGR_I2SE 10 I2S Enable
SPI_I2SCFGR_I2SMOD 11 I2S mode selection
SPI_I2SCFGR_ASTRTEN 12 Asynchronous start enable
I2SPR 0x20 32 SPI_I2S prescaler register
SPI_I2SPR_I2SDIV 0:7 I2S Linear prescaler
SPI_I2SPR_ODD 8 Odd factor for the prescaler
SPI_I2SPR_MCKOE 9 Master Clock Output Enable

FDCAN — FDCAN (раздел 19)

Регистр Смещение Бит Назначение
CREL 0x00 32 FDCAN Core Release register
FDCAN_CREL_DAY 0:7 Timestamp Day
FDCAN_CREL_MON 8:15 Timestamp Month
FDCAN_CREL_YEAR 16:19 Timestamp Year
FDCAN_CREL_SUBSTEP 20:23 Sub-step of Core release
FDCAN_CREL_STEP 24:27 Step of Core release
FDCAN_CREL_REL 28:31 Core release
ENDN 0x04 32 FDCAN Endian register
FDCAN_ENDN_ETV 0:31 Endianness Test Value
DBTP 0x0C 32 FDCAN Data Bit Timing & Prescaler register
FDCAN_DBTP_DSJW 0:3 Synchronization Jump Width
FDCAN_DBTP_DTSEG2 4:7 Data time segment after sample point
FDCAN_DBTP_DTSEG1 8:12 Data time segment before sample point
FDCAN_DBTP_DBRP 16:20 Data BIt Rate Prescaler
FDCAN_DBTP_TDC 23 Transceiver Delay Compensation
TEST 0x10 32 FDCAN Test register
FDCAN_TEST_LBCK 4 Loop Back mode
FDCAN_TEST_TX 5:6 Control of Transmit Pin
FDCAN_TEST_RX 7 Receive Pin
RWD 0x14 32 FDCAN RAM Watchdog register
FDCAN_RWD_WDC 0:7 Watchdog configuration
FDCAN_RWD_WDV 8:15 Watchdog value
CCCR 0x18 32 FDCAN CC Control register
FDCAN_CCCR_INIT 0 Initialization
FDCAN_CCCR_CCE 1 Configuration Change Enable
FDCAN_CCCR_ASM 2 ASM Restricted Operation Mode
FDCAN_CCCR_CSA 3 Clock Stop Acknowledge
FDCAN_CCCR_CSR 4 Clock Stop Request
FDCAN_CCCR_MON 5 Bus Monitoring Mode
FDCAN_CCCR_DAR 6 Disable Automatic Retransmission
FDCAN_CCCR_TEST 7 Test Mode Enable
FDCAN_CCCR_FDOE 8 FD Operation Enable
FDCAN_CCCR_BRSE 9 FDCAN Bit Rate Switching
FDCAN_CCCR_PXHD 12 Protocol Exception Handling Disable
FDCAN_CCCR_EFBI 13 Edge Filtering during Bus Integration
FDCAN_CCCR_TXP 14 Two CAN bit times Pause
FDCAN_CCCR_NISO 15 Non ISO Operation
NBTP 0x1C 32 FDCAN Nominal Bit Timing & Prescaler register
FDCAN_NBTP_NTSEG2 0:6 Nominal Time segment after sample point
FDCAN_NBTP_NTSEG1 8:15 Nominal Time segment before sample point
FDCAN_NBTP_NBRP 16:24 Bit Rate Prescaler
FDCAN_NBTP_NSJW 25:31 Nominal (Re)Synchronization Jump Width
TSCC 0x20 32 FDCAN Timestamp Counter Configuration register
FDCAN_TSCC_TSS 0:1 Timestamp Select
FDCAN_TSCC_TCP 16:19 Timestamp Counter Prescaler
TSCV 0x24 32 FDCAN Timestamp Counter Value register
FDCAN_TSCV_TSC 0:15 Timestamp Counter
TOCC 0x28 32 FDCAN Timeout Counter Configuration register
FDCAN_TOCC_ETOC 0 Enable Timeout Counter
FDCAN_TOCC_TOS 1:2 Timeout Select
FDCAN_TOCC_TOP 16:31 Timeout Period
TOCV 0x2C 32 FDCAN Timeout Counter Value register
FDCAN_TOCV_TOC 0:15 Timeout Counter
ECR 0x40 32 FDCAN Error Counter register
FDCAN_ECR_TEC 0:7 Transmit Error Counter
FDCAN_ECR_REC 8:14 Receive Error Counter
FDCAN_ECR_RP 15 Receive Error Passive
FDCAN_ECR_CEL 16:23 CAN Error Logging
PSR 0x44 32 FDCAN Protocol Status register
FDCAN_PSR_LEC 0:2 Last Error Code
FDCAN_PSR_ACT 3:4 Activity
FDCAN_PSR_EP 5 Error Passive
FDCAN_PSR_EW 6 Warning Status
FDCAN_PSR_BO 7 Bus_Off Status
FDCAN_PSR_DLEC 8:10 Data Last Error Code
FDCAN_PSR_RESI 11 ESI flag of last received FDCAN Message
FDCAN_PSR_RBRS 12 BRS flag of last received FDCAN Message
FDCAN_PSR_REDL 13 Received FDCAN Message
FDCAN_PSR_PXE 14 Protocol Exception Event
FDCAN_PSR_TDCV 16:22 Transmitter Delay Compensation Value
TDCR 0x48 32 FDCAN Transmitter Delay Compensation register
FDCAN_TDCR_TDCF 0:6 Transmitter Delay Compensation Filter
FDCAN_TDCR_TDCO 8:14 Transmitter Delay Compensation Offset
IR 0x50 32 FDCAN Interrupt register
FDCAN_IR_RF0N 0 Rx FIFO 0 New Message
FDCAN_IR_RF0F 1 Rx FIFO 0 Full
FDCAN_IR_RF0L 2 Rx FIFO 0 Message Lost
FDCAN_IR_RF1N 3 Rx FIFO 1 New Message
FDCAN_IR_RF1F 4 Rx FIFO 1 Full
FDCAN_IR_RF1L 5 Rx FIFO 1 Message Lost
FDCAN_IR_HPM 6 High Priority Message
FDCAN_IR_TC 7 Transmission Completed
FDCAN_IR_TCF 8 Transmission Cancellation Finished
FDCAN_IR_TFE 9 Tx FIFO Empty
FDCAN_IR_TEFN 10 Tx Event FIFO New Entry
FDCAN_IR_TEFF 11 Tx Event FIFO Full
FDCAN_IR_TEFL 12 Tx Event FIFO Element Lost
FDCAN_IR_TSW 13 Timestamp Wraparound
FDCAN_IR_MRAF 14 Message RAM Access Failure
FDCAN_IR_TOO 15 Timeout Occurred
FDCAN_IR_ELO 16 Error Logging Overflow
FDCAN_IR_EP 17 Error Passive
FDCAN_IR_EW 18 Warning Status
FDCAN_IR_BO 19 Bus_Off Status
FDCAN_IR_WDI 20 Watchdog Interrupt
FDCAN_IR_PEA 21 Protocol Error in Arbitration Phase
FDCAN_IR_PED 22 Protocol Error in Data Phase
FDCAN_IR_ARA 23 Access to Reserved Address
IE 0x54 32 FDCAN Interrupt Enable register
FDCAN_IE_RF0NE 0 Rx FIFO 0 New Message Enable
FDCAN_IE_RF0FE 1 Rx FIFO 0 Full Enable
FDCAN_IE_RF0LE 2 Rx FIFO 0 Message Lost Enable
FDCAN_IE_RF1NE 3 Rx FIFO 1 New Message Enable
FDCAN_IE_RF1FE 4 Rx FIFO 1 Full Enable
FDCAN_IE_RF1LE 5 Rx FIFO 1 Message Lost Enable
FDCAN_IE_HPME 6 High Priority Message Enable
FDCAN_IE_TCE 7 Transmission Completed Enable
FDCAN_IE_TCFE 8 Transmission Cancellation Finished Enable
FDCAN_IE_TFEE 9 Tx FIFO Empty Enable
FDCAN_IE_TEFNE 10 Tx Event FIFO New Entry Enable
FDCAN_IE_TEFFE 11 Tx Event FIFO Full Enable
FDCAN_IE_TEFLE 12 Tx Event FIFO Element Lost Enable
FDCAN_IE_TSWE 13 Timestamp Wraparound Enable
FDCAN_IE_MRAFE 14 Message RAM Access Failure Enable
FDCAN_IE_TOOE 15 Timeout Occurred Enable
FDCAN_IE_ELOE 16 Error Logging Overflow Enable
FDCAN_IE_EPE 17 Error Passive Enable
FDCAN_IE_EWE 18 Warning Status Enable
FDCAN_IE_BOE 19 Bus_Off Status Enable
FDCAN_IE_WDIE 20 Watchdog Interrupt Enable
FDCAN_IE_PEAE 21 Protocol Error in Arbitration Phase Enable
FDCAN_IE_PEDE 22 Protocol Error in Data Phase Enable
FDCAN_IE_ARAE 23 Access to Reserved Address Enable
ILS 0x58 32 FDCAN Interrupt Line Select register
FDCAN_ILS_RXFIFO0 0
FDCAN_ILS_RXFIFO1 1
FDCAN_ILS_SMSG 2
FDCAN_ILS_TFERR 3
FDCAN_ILS_MISC 4
FDCAN_ILS_BERR 5
FDCAN_ILS_PERR 6
ILE 0x5C 32 FDCAN Interrupt Line Enable register
FDCAN_ILE_EINT0 0 Enable Interrupt Line 0
FDCAN_ILE_EINT1 1 Enable Interrupt Line 1
RXGFC 0x80 32 FDCAN Global Filter Configuration register
FDCAN_RXGFC_RRFE 0 Reject Remote Frames Extended
FDCAN_RXGFC_RRFS 1 Reject Remote Frames Standard
FDCAN_RXGFC_ANFE 2:3 Accept Non-matching Frames Extended
FDCAN_RXGFC_ANFS 4:5 Accept Non-matching Frames Standard
FDCAN_RXGFC_F1OM 8 FIFO 1 operation mode
FDCAN_RXGFC_F0OM 9 FIFO 0 operation mode
FDCAN_RXGFC_LSS 16:20 List Size Standard
FDCAN_RXGFC_LSE 24:27 List Size Extended
XIDAM 0x84 32 FDCAN Extended ID AND Mask register
FDCAN_XIDAM_EIDM 0:28 Extended ID Mask
HPMS 0x88 32 FDCAN High Priority Message Status register
FDCAN_HPMS_BIDX 0:2 Buffer Index
FDCAN_HPMS_MSI 6:7 Message Storage Indicator
FDCAN_HPMS_FIDX 8:12 Filter Index
FDCAN_HPMS_FLST 15 Filter List
RXF0S 0x90 32 FDCAN Rx FIFO 0 Status register
FDCAN_RXF0S_F0FL 0:3 Rx FIFO 0 Fill Level
FDCAN_RXF0S_F0GI 8:9 Rx FIFO 0 Get Index
FDCAN_RXF0S_F0PI 16:17 Rx FIFO 0 Put Index
FDCAN_RXF0S_F0F 24 Rx FIFO 0 Full
FDCAN_RXF0S_RF0L 25 Rx FIFO 0 Message Lost
RXF0A 0x94 32 FDCAN Rx FIFO 0 Acknowledge register
FDCAN_RXF0A_F0AI 0:2 Rx FIFO 0 Acknowledge Index
RXF1S 0x98 32 FDCAN Rx FIFO 1 Status register
FDCAN_RXF1S_F1FL 0:3 Rx FIFO 1 Fill Level
FDCAN_RXF1S_F1GI 8:9 Rx FIFO 1 Get Index
FDCAN_RXF1S_F1PI 16:17 Rx FIFO 1 Put Index
FDCAN_RXF1S_F1F 24 Rx FIFO 1 Full
FDCAN_RXF1S_RF1L 25 Rx FIFO 1 Message Lost
RXF1A 0x9C 32 FDCAN Rx FIFO 1 Acknowledge register
FDCAN_RXF1A_F1AI 0:2 Rx FIFO 1 Acknowledge Index
TXBC 0xC0 32 FDCAN Tx Buffer Configuration register
FDCAN_TXBC_TFQM 24 Tx FIFO/Queue Mode
TXFQS 0xC4 32 FDCAN Tx FIFO/Queue Status register
FDCAN_TXFQS_TFFL 0:2 Tx FIFO Free Level
FDCAN_TXFQS_TFGI 8:9 Tx FIFO Get Index
FDCAN_TXFQS_TFQPI 16:17 Tx FIFO/Queue Put Index
FDCAN_TXFQS_TFQF 21 Tx FIFO/Queue Full
TXBRP 0xC8 32 FDCAN Tx Buffer Request Pending register
FDCAN_TXBRP_TRP 0:2 Transmission Request Pending
TXBAR 0xCC 32 FDCAN Tx Buffer Add Request register
FDCAN_TXBAR_AR 0:2 Add Request
TXBCR 0xD0 32 FDCAN Tx Buffer Cancellation Request register
FDCAN_TXBCR_CR 0:2 Cancellation Request
TXBTO 0xD4 32 FDCAN Tx Buffer Transmission Occurred register
FDCAN_TXBTO_TO 0:2 Transmission Occurred
TXBCF 0xD8 32 FDCAN Tx Buffer Cancellation Finished register
FDCAN_TXBCF_CF 0:2 Cancellation Finished
TXBTIE 0xDC 32 FDCAN Tx Buffer Transmission Interrupt Enable register
FDCAN_TXBTIE_TIE 0:2 Transmission Interrupt Enable
TXBCIE 0xE0 32 FDCAN Tx Buffer Cancellation Finished Interrupt Enable register
FDCAN_TXBCIE_CFIE 0:2 Cancellation Finished Interrupt Enable
TXEFS 0xE4 32 FDCAN Tx Event FIFO Status register
FDCAN_TXEFS_EFFL 0:2 Event FIFO Fill Level
FDCAN_TXEFS_EFGI 8:9 Event FIFO Get Index
FDCAN_TXEFS_EFPI 16:17 Event FIFO Put Index
FDCAN_TXEFS_EFF 24 Event FIFO Full
FDCAN_TXEFS_TEFL 25 Tx Event FIFO Element Lost
TXEFA 0xE8 32 FDCAN Tx Event FIFO Acknowledge register
FDCAN_TXEFA_EFAI 0:1 Event FIFO Acknowledge Index
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