STM32F303 · уровень справочник · 72 мин чтения

Приложение A5. Карты регистров STM32F3

Серия STM32F3: Cortex-M4 до 72 МГц с богатой аналоговой частью: быстрые АЦП, компараторы, ОУ. Регистры и биты основных блоков — из заголовка STM32F303, тем же генератором, что карты F1 и F4: смещения — по структурам *_TypeDef, назначение регистра и описание бита — из комментариев заголовка. Блоки, которых в серии нет, опущены. Разделы справочника написаны для F103 и F407; имена регистров и битов у серий в основном те же — карта помогает перенести код и увидеть, что устроено иначе.

Как читать: смещение — от базового адреса блока; 31:16 — поле битов с 16 по 31; одно число — отдельный бит. Цифра в скобках у заголовка блока — раздел, где блок разобран.

Периферия STM32F303 по шинам: базы шин и смещения блоков приложения, как в окне отладчика

RCC — Тактирование (раздел 6)

Регистр	Смещение	Бит	Назначение
`CR`	`0x00`	32	RCC clock control register
`RCC_CR_HSION`		0
`RCC_CR_HSIRDY`		1
`RCC_CR_HSITRIM`		3:7
`RCC_CR_HSICAL`		8:15
`RCC_CR_HSEON`		16
`RCC_CR_HSERDY`		17
`RCC_CR_HSEBYP`		18
`RCC_CR_CSSON`		19
`RCC_CR_PLLON`		24
`RCC_CR_PLLRDY`		25
`CFGR`	`0x04`	32	RCC clock configuration register
`RCC_CFGR_SW`		0:1	SW[1:0] bits (System clock Switch)
`RCC_CFGR_SWS`		2:3	SWS[1:0] bits (System Clock Switch Status)
`RCC_CFGR_HPRE`		4:7	HPRE[3:0] bits (AHB prescaler)
`RCC_CFGR_PPRE1`		8:10	PRE1[2:0] bits (APB1 prescaler)
`RCC_CFGR_PPRE2`		11:13	PRE2[2:0] bits (APB2 prescaler)
`RCC_CFGR_PLLSRC`		16	PLL entry clock source
`RCC_CFGR_PLLXTPRE`		17	HSE divider for PLL entry
`RCC_CFGR_PLLMUL`		18:21	PLLMUL[3:0] bits (PLL multiplication factor)
`RCC_CFGR_USBPRE`		22	USB prescaler
`RCC_CFGR_I2SSRC`		23	I2S external clock source selection
`RCC_CFGR_MCO`		24:26	MCO[2:0] bits (Microcontroller Clock Output)
`RCC_CFGR_MCOF`		28	Microcontroller Clock Output Flag
`CIR`	`0x08`	32	RCC clock interrupt register
`RCC_CIR_LSIRDYF`		0	LSI Ready Interrupt flag
`RCC_CIR_LSERDYF`		1	LSE Ready Interrupt flag
`RCC_CIR_HSIRDYF`		2	HSI Ready Interrupt flag
`RCC_CIR_HSERDYF`		3	HSE Ready Interrupt flag
`RCC_CIR_PLLRDYF`		4	PLL Ready Interrupt flag
`RCC_CIR_CSSF`		7	Clock Security System Interrupt flag
`RCC_CIR_LSIRDYIE`		8	LSI Ready Interrupt Enable
`RCC_CIR_LSERDYIE`		9	LSE Ready Interrupt Enable
`RCC_CIR_HSIRDYIE`		10	HSI Ready Interrupt Enable
`RCC_CIR_HSERDYIE`		11	HSE Ready Interrupt Enable
`RCC_CIR_PLLRDYIE`		12	PLL Ready Interrupt Enable
`RCC_CIR_LSIRDYC`		16	LSI Ready Interrupt Clear
`RCC_CIR_LSERDYC`		17	LSE Ready Interrupt Clear
`RCC_CIR_HSIRDYC`		18	HSI Ready Interrupt Clear
`RCC_CIR_HSERDYC`		19	HSE Ready Interrupt Clear
`RCC_CIR_PLLRDYC`		20	PLL Ready Interrupt Clear
`RCC_CIR_CSSC`		23	Clock Security System Interrupt Clear
`APB2RSTR`	`0x0C`	32	RCC APB2 peripheral reset register
`RCC_APB2RSTR_SYSCFGRST`		0	SYSCFG reset
`RCC_APB2RSTR_TIM1RST`		11	TIM1 reset
`RCC_APB2RSTR_SPI1RST`		12	SPI1 reset
`RCC_APB2RSTR_TIM8RST`		13	TIM8 reset
`RCC_APB2RSTR_USART1RST`		14	USART1 reset
`RCC_APB2RSTR_TIM15RST`		16	TIM15 reset
`RCC_APB2RSTR_TIM16RST`		17	TIM16 reset
`RCC_APB2RSTR_TIM17RST`		18	TIM17 reset
`APB1RSTR`	`0x10`	32	RCC APB1 peripheral reset register
`RCC_APB1RSTR_TIM2RST`		0	Timer 2 reset
`RCC_APB1RSTR_TIM3RST`		1	Timer 3 reset
`RCC_APB1RSTR_TIM4RST`		2	Timer 4 reset
`RCC_APB1RSTR_TIM6RST`		4	Timer 6 reset
`RCC_APB1RSTR_TIM7RST`		5	Timer 7 reset
`RCC_APB1RSTR_WWDGRST`		11	Window Watchdog reset
`RCC_APB1RSTR_SPI2RST`		14	SPI2 reset
`RCC_APB1RSTR_SPI3RST`		15	SPI3 reset
`RCC_APB1RSTR_USART2RST`		17	USART 2 reset
`RCC_APB1RSTR_USART3RST`		18	USART 3 reset
`RCC_APB1RSTR_UART4RST`		19	UART 4 reset
`RCC_APB1RSTR_UART5RST`		20	UART 5 reset
`RCC_APB1RSTR_I2C1RST`		21	I2C 1 reset
`RCC_APB1RSTR_I2C2RST`		22	I2C 2 reset
`RCC_APB1RSTR_USBRST`		23	USB reset
`RCC_APB1RSTR_CANRST`		25	CAN reset
`RCC_APB1RSTR_PWRRST`		28	PWR reset
`RCC_APB1RSTR_DAC1RST`		29	DAC 1 reset
`AHBENR`	`0x14`	32	RCC AHB peripheral clock register
`RCC_AHBENR_DMA1EN`		0	DMA1 clock enable
`RCC_AHBENR_DMA2EN`		1	DMA2 clock enable
`RCC_AHBENR_SRAMEN`		2	SRAM interface clock enable
`RCC_AHBENR_FLITFEN`		4	FLITF clock enable
`RCC_AHBENR_CRCEN`		6	CRC clock enable
`RCC_AHBENR_GPIOAEN`		17	GPIOA clock enable
`RCC_AHBENR_GPIOBEN`		18	GPIOB clock enable
`RCC_AHBENR_GPIOCEN`		19	GPIOC clock enable
`RCC_AHBENR_GPIODEN`		20	GPIOD clock enable
`RCC_AHBENR_GPIOEEN`		21	GPIOE clock enable
`RCC_AHBENR_GPIOFEN`		22	GPIOF clock enable
`RCC_AHBENR_TSCEN`		24	TS clock enable
`RCC_AHBENR_ADC12EN`		28	ADC1/ ADC2 clock enable
`RCC_AHBENR_ADC34EN`		29	ADC3/ ADC4 clock enable
`APB2ENR`	`0x18`	32	RCC APB2 peripheral clock enable register
`RCC_APB2ENR_SYSCFGEN`		0	SYSCFG clock enable
`RCC_APB2ENR_TIM1EN`		11	TIM1 clock enable
`RCC_APB2ENR_SPI1EN`		12	SPI1 clock enable
`RCC_APB2ENR_TIM8EN`		13	TIM8 clock enable
`RCC_APB2ENR_USART1EN`		14	USART1 clock enable
`RCC_APB2ENR_TIM15EN`		16	TIM15 clock enable
`RCC_APB2ENR_TIM16EN`		17	TIM16 clock enable
`RCC_APB2ENR_TIM17EN`		18	TIM17 clock enable
`APB1ENR`	`0x1C`	32	RCC APB1 peripheral clock enable register
`RCC_APB1ENR_TIM2EN`		0	Timer 2 clock enable
`RCC_APB1ENR_TIM3EN`		1	Timer 3 clock enable
`RCC_APB1ENR_TIM4EN`		2	Timer 4 clock enable
`RCC_APB1ENR_TIM6EN`		4	Timer 6 clock enable
`RCC_APB1ENR_TIM7EN`		5	Timer 7 clock enable
`RCC_APB1ENR_WWDGEN`		11	Window Watchdog clock enable
`RCC_APB1ENR_SPI2EN`		14	SPI2 clock enable
`RCC_APB1ENR_SPI3EN`		15	SPI3 clock enable
`RCC_APB1ENR_USART2EN`		17	USART 2 clock enable
`RCC_APB1ENR_USART3EN`		18	USART 3 clock enable
`RCC_APB1ENR_UART4EN`		19	UART 4 clock enable
`RCC_APB1ENR_UART5EN`		20	UART 5 clock enable
`RCC_APB1ENR_I2C1EN`		21	I2C 1 clock enable
`RCC_APB1ENR_I2C2EN`		22	I2C 2 clock enable
`RCC_APB1ENR_USBEN`		23	USB clock enable
`RCC_APB1ENR_CANEN`		25	CAN clock enable
`RCC_APB1ENR_PWREN`		28	PWR clock enable
`RCC_APB1ENR_DAC1EN`		29	DAC 1 clock enable
`BDCR`	`0x20`	32	RCC Backup domain control register
`RCC_BDCR_LSE`		0:2	External Low Speed oscillator [2:0] bits
`RCC_BDCR_LSEON`		0	External Low Speed oscillator enable
`RCC_BDCR_LSERDY`		1	External Low Speed oscillator Ready
`RCC_BDCR_LSEBYP`		2	External Low Speed oscillator Bypass
`RCC_BDCR_LSEDRV`		3:4	LSEDRV[1:0] bits (LSE Osc. drive capability)
`RCC_BDCR_RTCSEL`		8:9	RTCSEL[1:0] bits (RTC clock source selection)
`RCC_BDCR_RTCEN`		15	RTC clock enable
`RCC_BDCR_BDRST`		16	Backup domain software reset
`CSR`	`0x24`	32	RCC clock control & status register
`RCC_CSR_LSION`		0	Internal Low Speed oscillator enable
`RCC_CSR_LSIRDY`		1	Internal Low Speed oscillator Ready
`RCC_CSR_V18PWRRSTF`		23	V1.8 power domain reset flag
`RCC_CSR_RMVF`		24	Remove reset flag
`RCC_CSR_OBLRSTF`		25	OBL reset flag
`RCC_CSR_PINRSTF`		26	PIN reset flag
`RCC_CSR_PORRSTF`		27	POR/PDR reset flag
`RCC_CSR_SFTRSTF`		28	Software Reset flag
`RCC_CSR_IWDGRSTF`		29	Independent Watchdog reset flag
`RCC_CSR_WWDGRSTF`		30	Window watchdog reset flag
`RCC_CSR_LPWRRSTF`		31	Low-Power reset flag
`AHBRSTR`	`0x28`	32	RCC AHB peripheral reset register
`RCC_AHBRSTR_GPIOARST`		17	GPIOA reset
`RCC_AHBRSTR_GPIOBRST`		18	GPIOB reset
`RCC_AHBRSTR_GPIOCRST`		19	GPIOC reset
`RCC_AHBRSTR_GPIODRST`		20	GPIOD reset
`RCC_AHBRSTR_GPIOERST`		21	GPIOE reset
`RCC_AHBRSTR_GPIOFRST`		22	GPIOF reset
`RCC_AHBRSTR_TSCRST`		24	TSC reset
`RCC_AHBRSTR_ADC12RST`		28	ADC1 & ADC2 reset
`RCC_AHBRSTR_ADC34RST`		29	ADC3 & ADC4 reset
`CFGR2`	`0x2C`	32	RCC clock configuration register 2
`RCC_CFGR2_PREDIV`		0:3	PREDIV[3:0] bits
`RCC_CFGR2_ADCPRE12`		4:8	ADCPRE12[8:4] bits
`RCC_CFGR2_ADCPRE34`		9:13	ADCPRE34[13:5] bits
`CFGR3`	`0x30`	32	RCC clock configuration register 3
`RCC_CFGR3_USART1SW`		0:1	USART1SW[1:0] bits
`RCC_CFGR3_I2CSW`		4:5	I2CSW bits
`RCC_CFGR3_I2C1SW`		4	I2C1SW bits
`RCC_CFGR3_I2C1SW_SYSCLK`		4	System clock selected as I2C1 clock source
`RCC_CFGR3_I2C2SW`		5	I2C2SW bits
`RCC_CFGR3_I2C2SW_SYSCLK`		5	System clock selected as I2C2 clock source
`RCC_CFGR3_TIMSW`		8:9	TIMSW bits
`RCC_CFGR3_TIM1SW`		8	TIM1SW bits
`RCC_CFGR3_TIM1SW_PLL`		8	PLL clock used as TIM1 clock source
`RCC_CFGR3_TIM8SW`		9	TIM8SW bits
`RCC_CFGR3_TIM8SW_PLL`		9	PLL clock used as TIM8 clock source
`RCC_CFGR3_USART2SW`		16:17	USART2SW[1:0] bits
`RCC_CFGR3_USART3SW`		18:19	USART3SW[1:0] bits
`RCC_CFGR3_UART4SW`		20:21	UART4SW[1:0] bits
`RCC_CFGR3_UART5SW`		22:23	UART5SW[1:0] bits

GPIO — Порты ввода-вывода (раздел 8)

Регистр	Смещение	Бит	Назначение
`MODER`	`0x00`	32	GPIO port mode register
`GPIO_MODER_MODER0`		0:1
`GPIO_MODER_MODER1`		2:3
`GPIO_MODER_MODER2`		4:5
`GPIO_MODER_MODER3`		6:7
`GPIO_MODER_MODER4`		8:9
`GPIO_MODER_MODER5`		10:11
`GPIO_MODER_MODER6`		12:13
`GPIO_MODER_MODER7`		14:15
`GPIO_MODER_MODER8`		16:17
`GPIO_MODER_MODER9`		18:19
`GPIO_MODER_MODER10`		20:21
`GPIO_MODER_MODER11`		22:23
`GPIO_MODER_MODER12`		24:25
`GPIO_MODER_MODER13`		26:27
`GPIO_MODER_MODER14`		28:29
`GPIO_MODER_MODER15`		30:31
`OTYPER`	`0x04`	32	GPIO port output type register
`OSPEEDR`	`0x08`	32	GPIO port output speed register
`PUPDR`	`0x0C`	32	GPIO port pull-up/pull-down register
`GPIO_PUPDR_PUPDR0`		0:1
`GPIO_PUPDR_PUPDR1`		2:3
`GPIO_PUPDR_PUPDR2`		4:5
`GPIO_PUPDR_PUPDR3`		6:7
`GPIO_PUPDR_PUPDR4`		8:9
`GPIO_PUPDR_PUPDR5`		10:11
`GPIO_PUPDR_PUPDR6`		12:13
`GPIO_PUPDR_PUPDR7`		14:15
`GPIO_PUPDR_PUPDR8`		16:17
`GPIO_PUPDR_PUPDR9`		18:19
`GPIO_PUPDR_PUPDR10`		20:21
`GPIO_PUPDR_PUPDR11`		22:23
`GPIO_PUPDR_PUPDR12`		24:25
`GPIO_PUPDR_PUPDR13`		26:27
`GPIO_PUPDR_PUPDR14`		28:29
`GPIO_PUPDR_PUPDR15`		30:31
`IDR`	`0x10`	32	GPIO port input data register
`ODR`	`0x14`	32	GPIO port output data register
`BSRR`	`0x18`	32	GPIO port bit set/reset register
`LCKR`	`0x1C`	32	GPIO port configuration lock register
`GPIO_LCKR_LCK0`		0
`GPIO_LCKR_LCK1`		1
`GPIO_LCKR_LCK2`		2
`GPIO_LCKR_LCK3`		3
`GPIO_LCKR_LCK4`		4
`GPIO_LCKR_LCK5`		5
`GPIO_LCKR_LCK6`		6
`GPIO_LCKR_LCK7`		7
`GPIO_LCKR_LCK8`		8
`GPIO_LCKR_LCK9`		9
`GPIO_LCKR_LCK10`		10
`GPIO_LCKR_LCK11`		11
`GPIO_LCKR_LCK12`		12
`GPIO_LCKR_LCK13`		13
`GPIO_LCKR_LCK14`		14
`GPIO_LCKR_LCK15`		15
`GPIO_LCKR_LCKK`		16
`AFR`+2×4	`0x20`	32	GPIO alternate function registers
`BRR`	`0x28`	32	GPIO bit reset register

SYSCFG — Системная конфигурация (раздел 8)

Регистр	Смещение	Бит	Назначение
`CFGR1`	`0x00`	32	SYSCFG configuration register 1
`SYSCFG_CFGR1_MEM_MODE`		0:1	SYSCFG_Memory Remap Config
`SYSCFG_CFGR1_USB_IT_RMP`		5	USB interrupt remap
`SYSCFG_CFGR1_TIM1_ITR3_RMP`		6	Timer 1 ITR3 selection
`SYSCFG_CFGR1_DAC1_TRIG1_RMP`		7	DAC1 Trigger1 remap
`SYSCFG_CFGR1_DMA_RMP`		8:14	DMA remap mask
`SYSCFG_CFGR1_ADC24_DMA_RMP`		8	ADC2 and ADC4 DMA remap
`SYSCFG_CFGR1_TIM16_DMA_RMP`		11	Timer 16 DMA remap
`SYSCFG_CFGR1_TIM17_DMA_RMP`		12	Timer 17 DMA remap
`SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP`		13	Timer 6 / DAC1 Ch1 DMA remap
`SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP`		14	Timer 7 / DAC1 Ch2 DMA remap
`SYSCFG_CFGR1_I2C_PB6_FMP`		16	I2C PB6 Fast mode plus
`SYSCFG_CFGR1_I2C_PB7_FMP`		17	I2C PB7 Fast mode plus
`SYSCFG_CFGR1_I2C_PB8_FMP`		18	I2C PB8 Fast mode plus
`SYSCFG_CFGR1_I2C_PB9_FMP`		19	I2C PB9 Fast mode plus
`SYSCFG_CFGR1_I2C1_FMP`		20	I2C1 Fast mode plus
`SYSCFG_CFGR1_I2C2_FMP`		21	I2C2 Fast mode plus
`SYSCFG_CFGR1_ENCODER_MODE`		22:23	Encoder Mode
`SYSCFG_CFGR1_ENCODER_MODE_TIM2`		22	TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
`SYSCFG_CFGR1_ENCODER_MODE_TIM4`		22:23	TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
`SYSCFG_CFGR1_ENCODER_MODE_TIM3`		23	TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
`SYSCFG_CFGR1_FPU_IE`		26:31	Floating Point Unit Interrupt Enable
`RCR`	`0x04`	32	SYSCFG CCM SRAM protection register
`SYSCFG_RCR_PAGE0`		0	ICODE SRAM Write protection page 0
`SYSCFG_RCR_PAGE1`		1	ICODE SRAM Write protection page 1
`SYSCFG_RCR_PAGE2`		2	ICODE SRAM Write protection page 2
`SYSCFG_RCR_PAGE3`		3	ICODE SRAM Write protection page 3
`SYSCFG_RCR_PAGE4`		4	ICODE SRAM Write protection page 4
`SYSCFG_RCR_PAGE5`		5	ICODE SRAM Write protection page 5
`SYSCFG_RCR_PAGE6`		6	ICODE SRAM Write protection page 6
`SYSCFG_RCR_PAGE7`		7	ICODE SRAM Write protection page 7
`EXTICR`+4×4	`0x08`	32	SYSCFG external interrupt configuration registers
`CFGR2`	`0x18`	32	SYSCFG configuration register 2
`SYSCFG_CFGR2_LOCKUP_LOCK`		0	Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx
`SYSCFG_CFGR2_SRAM_PARITY_LOCK`		1	Enables and locks the SRAM_PARITY error signal with Break Input of TIMx
`SYSCFG_CFGR2_PVD_LOCK`		2	Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register
`SYSCFG_CFGR2_BYP_ADDR_PAR`		4	Disables the adddress parity check on RAM
`SYSCFG_CFGR2_SRAM_PE`		8	SRAM Parity error flag

EXTI — Внешние прерывания (раздел 7)

Регистр	Смещение	Бит	Назначение
`IMR`	`0x00`	32	EXTI Interrupt mask register
`EXTI_IMR_MR0`		0	Interrupt Mask on line 0
`EXTI_IMR_IM`		0:31	Interrupt Mask All
`EXTI_IMR_MR1`		1	Interrupt Mask on line 1
`EXTI_IMR_MR2`		2	Interrupt Mask on line 2
`EXTI_IMR_MR3`		3	Interrupt Mask on line 3
`EXTI_IMR_MR4`		4	Interrupt Mask on line 4
`EXTI_IMR_MR5`		5	Interrupt Mask on line 5
`EXTI_IMR_MR6`		6	Interrupt Mask on line 6
`EXTI_IMR_MR7`		7	Interrupt Mask on line 7
`EXTI_IMR_MR8`		8	Interrupt Mask on line 8
`EXTI_IMR_MR9`		9	Interrupt Mask on line 9
`EXTI_IMR_MR10`		10	Interrupt Mask on line 10
`EXTI_IMR_MR11`		11	Interrupt Mask on line 11
`EXTI_IMR_MR12`		12	Interrupt Mask on line 12
`EXTI_IMR_MR13`		13	Interrupt Mask on line 13
`EXTI_IMR_MR14`		14	Interrupt Mask on line 14
`EXTI_IMR_MR15`		15	Interrupt Mask on line 15
`EXTI_IMR_MR16`		16	Interrupt Mask on line 16
`EXTI_IMR_MR17`		17	Interrupt Mask on line 17
`EXTI_IMR_MR18`		18	Interrupt Mask on line 18
`EXTI_IMR_MR19`		19	Interrupt Mask on line 19
`EXTI_IMR_MR20`		20	Interrupt Mask on line 20
`EXTI_IMR_MR21`		21	Interrupt Mask on line 21
`EXTI_IMR_MR22`		22	Interrupt Mask on line 22
`EXTI_IMR_MR23`		23	Interrupt Mask on line 23
`EXTI_IMR_MR24`		24	Interrupt Mask on line 24
`EXTI_IMR_MR25`		25	Interrupt Mask on line 25
`EXTI_IMR_MR26`		26	Interrupt Mask on line 26
`EXTI_IMR_MR28`		28	Interrupt Mask on line 28
`EXTI_IMR_MR29`		29	Interrupt Mask on line 29
`EXTI_IMR_MR30`		30	Interrupt Mask on line 30
`EXTI_IMR_MR31`		31	Interrupt Mask on line 31
`EMR`	`0x04`	32	EXTI Event mask register
`EXTI_EMR_MR0`		0	Event Mask on line 0
`EXTI_EMR_MR1`		1	Event Mask on line 1
`EXTI_EMR_MR2`		2	Event Mask on line 2
`EXTI_EMR_MR3`		3	Event Mask on line 3
`EXTI_EMR_MR4`		4	Event Mask on line 4
`EXTI_EMR_MR5`		5	Event Mask on line 5
`EXTI_EMR_MR6`		6	Event Mask on line 6
`EXTI_EMR_MR7`		7	Event Mask on line 7
`EXTI_EMR_MR8`		8	Event Mask on line 8
`EXTI_EMR_MR9`		9	Event Mask on line 9
`EXTI_EMR_MR10`		10	Event Mask on line 10
`EXTI_EMR_MR11`		11	Event Mask on line 11
`EXTI_EMR_MR12`		12	Event Mask on line 12
`EXTI_EMR_MR13`		13	Event Mask on line 13
`EXTI_EMR_MR14`		14	Event Mask on line 14
`EXTI_EMR_MR15`		15	Event Mask on line 15
`EXTI_EMR_MR16`		16	Event Mask on line 16
`EXTI_EMR_MR17`		17	Event Mask on line 17
`EXTI_EMR_MR18`		18	Event Mask on line 18
`EXTI_EMR_MR19`		19	Event Mask on line 19
`EXTI_EMR_MR20`		20	Event Mask on line 20
`EXTI_EMR_MR21`		21	Event Mask on line 21
`EXTI_EMR_MR22`		22	Event Mask on line 22
`EXTI_EMR_MR23`		23	Event Mask on line 23
`EXTI_EMR_MR24`		24	Event Mask on line 24
`EXTI_EMR_MR25`		25	Event Mask on line 25
`EXTI_EMR_MR26`		26	Event Mask on line 26
`EXTI_EMR_MR28`		28	Event Mask on line 28
`EXTI_EMR_MR29`		29	Event Mask on line 29
`EXTI_EMR_MR30`		30	Event Mask on line 30
`EXTI_EMR_MR31`		31	Event Mask on line 31
`RTSR`	`0x08`	32	EXTI Rising trigger selection register
`EXTI_RTSR_TR0`		0	Rising trigger event configuration bit of line 0
`EXTI_RTSR_TR1`		1	Rising trigger event configuration bit of line 1
`EXTI_RTSR_TR2`		2	Rising trigger event configuration bit of line 2
`EXTI_RTSR_TR3`		3	Rising trigger event configuration bit of line 3
`EXTI_RTSR_TR4`		4	Rising trigger event configuration bit of line 4
`EXTI_RTSR_TR5`		5	Rising trigger event configuration bit of line 5
`EXTI_RTSR_TR6`		6	Rising trigger event configuration bit of line 6
`EXTI_RTSR_TR7`		7	Rising trigger event configuration bit of line 7
`EXTI_RTSR_TR8`		8	Rising trigger event configuration bit of line 8
`EXTI_RTSR_TR9`		9	Rising trigger event configuration bit of line 9
`EXTI_RTSR_TR10`		10	Rising trigger event configuration bit of line 10
`EXTI_RTSR_TR11`		11	Rising trigger event configuration bit of line 11
`EXTI_RTSR_TR12`		12	Rising trigger event configuration bit of line 12
`EXTI_RTSR_TR13`		13	Rising trigger event configuration bit of line 13
`EXTI_RTSR_TR14`		14	Rising trigger event configuration bit of line 14
`EXTI_RTSR_TR15`		15	Rising trigger event configuration bit of line 15
`EXTI_RTSR_TR16`		16	Rising trigger event configuration bit of line 16
`EXTI_RTSR_TR17`		17	Rising trigger event configuration bit of line 17
`EXTI_RTSR_TR18`		18	Rising trigger event configuration bit of line 18
`EXTI_RTSR_TR19`		19	Rising trigger event configuration bit of line 19
`EXTI_RTSR_TR20`		20	Rising trigger event configuration bit of line 20
`EXTI_RTSR_TR21`		21	Rising trigger event configuration bit of line 21
`EXTI_RTSR_TR22`		22	Rising trigger event configuration bit of line 22
`EXTI_RTSR_TR29`		29	Rising trigger event configuration bit of line 29
`EXTI_RTSR_TR30`		30	Rising trigger event configuration bit of line 30
`EXTI_RTSR_TR31`		31	Rising trigger event configuration bit of line 31
`FTSR`	`0x0C`	32	EXTI Falling trigger selection register
`EXTI_FTSR_TR0`		0	Falling trigger event configuration bit of line 0
`EXTI_FTSR_TR1`		1	Falling trigger event configuration bit of line 1
`EXTI_FTSR_TR2`		2	Falling trigger event configuration bit of line 2
`EXTI_FTSR_TR3`		3	Falling trigger event configuration bit of line 3
`EXTI_FTSR_TR4`		4	Falling trigger event configuration bit of line 4
`EXTI_FTSR_TR5`		5	Falling trigger event configuration bit of line 5
`EXTI_FTSR_TR6`		6	Falling trigger event configuration bit of line 6
`EXTI_FTSR_TR7`		7	Falling trigger event configuration bit of line 7
`EXTI_FTSR_TR8`		8	Falling trigger event configuration bit of line 8
`EXTI_FTSR_TR9`		9	Falling trigger event configuration bit of line 9
`EXTI_FTSR_TR10`		10	Falling trigger event configuration bit of line 10
`EXTI_FTSR_TR11`		11	Falling trigger event configuration bit of line 11
`EXTI_FTSR_TR12`		12	Falling trigger event configuration bit of line 12
`EXTI_FTSR_TR13`		13	Falling trigger event configuration bit of line 13
`EXTI_FTSR_TR14`		14	Falling trigger event configuration bit of line 14
`EXTI_FTSR_TR15`		15	Falling trigger event configuration bit of line 15
`EXTI_FTSR_TR16`		16	Falling trigger event configuration bit of line 16
`EXTI_FTSR_TR17`		17	Falling trigger event configuration bit of line 17
`EXTI_FTSR_TR18`		18	Falling trigger event configuration bit of line 18
`EXTI_FTSR_TR19`		19	Falling trigger event configuration bit of line 19
`EXTI_FTSR_TR20`		20	Falling trigger event configuration bit of line 20
`EXTI_FTSR_TR21`		21	Falling trigger event configuration bit of line 21
`EXTI_FTSR_TR22`		22	Falling trigger event configuration bit of line 22
`EXTI_FTSR_TR29`		29	Falling trigger event configuration bit of line 29
`EXTI_FTSR_TR30`		30	Falling trigger event configuration bit of line 30
`EXTI_FTSR_TR31`		31	Falling trigger event configuration bit of line 31
`SWIER`	`0x10`	32	EXTI Software interrupt event register
`EXTI_SWIER_SWIER0`		0	Software Interrupt on line 0
`EXTI_SWIER_SWIER1`		1	Software Interrupt on line 1
`EXTI_SWIER_SWIER2`		2	Software Interrupt on line 2
`EXTI_SWIER_SWIER3`		3	Software Interrupt on line 3
`EXTI_SWIER_SWIER4`		4	Software Interrupt on line 4
`EXTI_SWIER_SWIER5`		5	Software Interrupt on line 5
`EXTI_SWIER_SWIER6`		6	Software Interrupt on line 6
`EXTI_SWIER_SWIER7`		7	Software Interrupt on line 7
`EXTI_SWIER_SWIER8`		8	Software Interrupt on line 8
`EXTI_SWIER_SWIER9`		9	Software Interrupt on line 9
`EXTI_SWIER_SWIER10`		10	Software Interrupt on line 10
`EXTI_SWIER_SWIER11`		11	Software Interrupt on line 11
`EXTI_SWIER_SWIER12`		12	Software Interrupt on line 12
`EXTI_SWIER_SWIER13`		13	Software Interrupt on line 13
`EXTI_SWIER_SWIER14`		14	Software Interrupt on line 14
`EXTI_SWIER_SWIER15`		15	Software Interrupt on line 15
`EXTI_SWIER_SWIER16`		16	Software Interrupt on line 16
`EXTI_SWIER_SWIER17`		17	Software Interrupt on line 17
`EXTI_SWIER_SWIER18`		18	Software Interrupt on line 18
`EXTI_SWIER_SWIER19`		19	Software Interrupt on line 19
`EXTI_SWIER_SWIER20`		20	Software Interrupt on line 20
`EXTI_SWIER_SWIER21`		21	Software Interrupt on line 21
`EXTI_SWIER_SWIER22`		22	Software Interrupt on line 22
`EXTI_SWIER_SWIER29`		29	Software Interrupt on line 29
`EXTI_SWIER_SWIER30`		30	Software Interrupt on line 30
`EXTI_SWIER_SWIER31`		31	Software Interrupt on line 31
`PR`	`0x14`	32	EXTI Pending register
`EXTI_PR_PR0`		0	Pending bit for line 0
`EXTI_PR_PR1`		1	Pending bit for line 1
`EXTI_PR_PR2`		2	Pending bit for line 2
`EXTI_PR_PR3`		3	Pending bit for line 3
`EXTI_PR_PR4`		4	Pending bit for line 4
`EXTI_PR_PR5`		5	Pending bit for line 5
`EXTI_PR_PR6`		6	Pending bit for line 6
`EXTI_PR_PR7`		7	Pending bit for line 7
`EXTI_PR_PR8`		8	Pending bit for line 8
`EXTI_PR_PR9`		9	Pending bit for line 9
`EXTI_PR_PR10`		10	Pending bit for line 10
`EXTI_PR_PR11`		11	Pending bit for line 11
`EXTI_PR_PR12`		12	Pending bit for line 12
`EXTI_PR_PR13`		13	Pending bit for line 13
`EXTI_PR_PR14`		14	Pending bit for line 14
`EXTI_PR_PR15`		15	Pending bit for line 15
`EXTI_PR_PR16`		16	Pending bit for line 16
`EXTI_PR_PR17`		17	Pending bit for line 17
`EXTI_PR_PR18`		18	Pending bit for line 18
`EXTI_PR_PR19`		19	Pending bit for line 19
`EXTI_PR_PR20`		20	Pending bit for line 20
`EXTI_PR_PR21`		21	Pending bit for line 21
`EXTI_PR_PR22`		22	Pending bit for line 22
`EXTI_PR_PR29`		29	Pending bit for line 29
`EXTI_PR_PR30`		30	Pending bit for line 30
`EXTI_PR_PR31`		31	Pending bit for line 31
`IMR2`	`0x20`	32	EXTI Interrupt mask register
`EXTI_IMR2_MR32`		0	Interrupt Mask on line 32
`EXTI_IMR2_IM`		0
`EXTI_IMR2_MR33`		1	Interrupt Mask on line 33
`EXTI_IMR2_MR34`		2	Interrupt Mask on line 34
`EXTI_IMR2_MR35`		3	Interrupt Mask on line 35
`EMR2`	`0x24`	32	EXTI Event mask register
`EXTI_EMR2_MR32`		0	Event Mask on line 32
`EXTI_EMR2_EM`		0
`EXTI_EMR2_MR33`		1	Event Mask on line 33
`EXTI_EMR2_MR34`		2	Event Mask on line 34
`EXTI_EMR2_MR35`		3	Event Mask on line 34
`RTSR2`	`0x28`	32	EXTI Rising trigger selection register
`EXTI_RTSR2_TR32`		0	Rising trigger event configuration bit of line 32
`EXTI_RTSR2_TR33`		1	Rising trigger event configuration bit of line 33
`FTSR2`	`0x2C`	32	EXTI Falling trigger selection register
`EXTI_FTSR2_TR32`		0	Falling trigger event configuration bit of line 32
`EXTI_FTSR2_TR33`		1	Falling trigger event configuration bit of line 33
`SWIER2`	`0x30`	32	EXTI Software interrupt event register
`EXTI_SWIER2_SWIER32`		0	Software Interrupt on line 32
`EXTI_SWIER2_SWIER33`		1	Software Interrupt on line 33
`PR2`	`0x34`	32	EXTI Pending register
`EXTI_PR2_PR32`		0	Pending bit for line 32
`EXTI_PR2_PR33`		1	Pending bit for line 33

DMA — Канал DMA (раздел 9)

Регистр	Смещение	Бит	Назначение
`CCR`	`0x00`	32	DMA channel x configuration register
`DMA_CCR_EN`		0	Channel enable
`DMA_CCR_TCIE`		1	Transfer complete interrupt enable
`DMA_CCR_HTIE`		2	Half Transfer interrupt enable
`DMA_CCR_TEIE`		3	Transfer error interrupt enable
`DMA_CCR_DIR`		4	Data transfer direction
`DMA_CCR_CIRC`		5	Circular mode
`DMA_CCR_PINC`		6	Peripheral increment mode
`DMA_CCR_MINC`		7	Memory increment mode
`DMA_CCR_PSIZE`		8:9	PSIZE[1:0] bits (Peripheral size)
`DMA_CCR_MSIZE`		10:11	MSIZE[1:0] bits (Memory size)
`DMA_CCR_PL`		12:13	PL[1:0] bits(Channel Priority level)
`DMA_CCR_MEM2MEM`		14	Memory to memory mode
`CNDTR`	`0x04`	32	DMA channel x number of data register
`DMA_CNDTR_NDT`		0:15	Number of data to Transfer
`CPAR`	`0x08`	32	DMA channel x peripheral address register
`DMA_CPAR_PA`		0:31	Peripheral Address
`CMAR`	`0x0C`	32	DMA channel x memory address register
`DMA_CMAR_MA`		0:31	Memory Address

PWR — Питание и режимы сна (раздел 10)

Регистр	Смещение	Бит	Назначение
`CR`	`0x00`	32	PWR power control register
`PWR_CR_LPDS`		0	Low-power Deepsleep
`PWR_CR_PDDS`		1	Power Down Deepsleep
`PWR_CR_CWUF`		2	Clear Wakeup Flag
`PWR_CR_CSBF`		3	Clear Standby Flag
`PWR_CR_PVDE`		4	Power Voltage Detector Enable
`PWR_CR_PLS`		5:7	PLS[2:0] bits (PVD Level Selection)
`PWR_CR_DBP`		8	Disable Backup Domain write protection
`CSR`	`0x04`	32	PWR power control/status register
`PWR_CSR_WUF`		0	Wakeup Flag
`PWR_CSR_SBF`		1	Standby Flag
`PWR_CSR_PVDO`		2	PVD Output
`PWR_CSR_VREFINTRDYF`		3	Internal voltage reference (VREFINT) ready flag
`PWR_CSR_EWUP1`		8	Enable WKUP pin 1
`PWR_CSR_EWUP2`		9	Enable WKUP pin 2
`PWR_CSR_EWUP3`		10	Enable WKUP pin 3

FLASH — Контроллер флеш-памяти (раздел 11)

Регистр	Смещение	Бит	Назначение
`ACR`	`0x00`	32	FLASH access control register
`FLASH_ACR_LATENCY`		0:2	LATENCY[2:0] bits (Latency)
`FLASH_ACR_HLFCYA`		3	Flash Half Cycle Access Enable
`FLASH_ACR_PRFTBE`		4	Prefetch Buffer Enable
`FLASH_ACR_PRFTBS`		5	Prefetch Buffer Status
`KEYR`	`0x04`	32	FLASH key register
`FLASH_KEYR_FKEYR`		0:31	FPEC Key
`OPTKEYR`	`0x08`	32	FLASH option key register
`FLASH_OPTKEYR_OPTKEYR`		0:31	Option Byte Key
`SR`	`0x0C`	32	FLASH status register
`FLASH_SR_BSY`		0	Busy
`FLASH_SR_PGERR`		2	Programming Error
`FLASH_SR_WRPERR`		4	Write Protection Error
`FLASH_SR_EOP`		5	End of operation
`CR`	`0x10`	32	FLASH control register
`FLASH_CR_PG`		0	Programming
`FLASH_CR_PER`		1	Page Erase
`FLASH_CR_MER`		2	Mass Erase
`FLASH_CR_OPTPG`		4	Option Byte Programming
`FLASH_CR_OPTER`		5	Option Byte Erase
`FLASH_CR_STRT`		6	Start
`FLASH_CR_LOCK`		7	Lock
`FLASH_CR_OPTWRE`		9	Option Bytes Write Enable
`FLASH_CR_ERRIE`		10	Error Interrupt Enable
`FLASH_CR_EOPIE`		12	End of operation interrupt enable
`FLASH_CR_OBL_LAUNCH`		13	OptionBytes Loader Launch
`AR`	`0x14`	32	FLASH address register
`FLASH_AR_FAR`		0:31	Flash Address
`OBR`	`0x1C`	32	FLASH Option byte register
`FLASH_OBR_OPTERR`		0	Option Byte Error
`FLASH_OBR_RDPRT`		1:2	Read protection
`FLASH_OBR_USER`		8:14	User Option Bytes
`FLASH_OBR_IWDG_SW`		8	IWDG SW
`FLASH_OBR_nRST_STOP`		9	nRST_STOP
`FLASH_OBR_nRST_STDBY`		10	nRST_STDBY
`FLASH_OBR_nBOOT1`		12	nBOOT1
`FLASH_OBR_VDDA_MONITOR`		13	VDDA_MONITOR
`FLASH_OBR_SRAM_PE`		14	SRAM_PE
`FLASH_OBR_DATA0`		16:23	Data0
`FLASH_OBR_DATA1`		24:31	Data1
`WRPR`	`0x20`	32	FLASH Write register
`FLASH_WRPR_WRP`		0:31	Write Protect

IWDG — Независимый сторож (раздел 12)

Регистр	Смещение	Бит	Назначение
`KR`	`0x00`	32	IWDG Key register
`IWDG_KR_KEY`		0:15	Key value (write only, read 0000h)
`PR`	`0x04`	32	IWDG Prescaler register
`IWDG_PR_PR`		0:2	PR[2:0] (Prescaler divider)
`RLR`	`0x08`	32	IWDG Reload register
`IWDG_RLR_RL`		0:11	Watchdog counter reload value
`SR`	`0x0C`	32	IWDG Status register
`IWDG_SR_PVU`		0	Watchdog prescaler value update
`IWDG_SR_RVU`		1	Watchdog counter reload value update
`IWDG_SR_WVU`		2	Watchdog counter window value update
`WINR`	`0x10`	32	IWDG Window register
`IWDG_WINR_WIN`		0:11	Watchdog counter window value

WWDG — Оконный сторож (раздел 12)

Регистр	Смещение	Бит	Назначение
`CR`	`0x00`	32	WWDG Control register
`WWDG_CR_T`		0:6	T[6:0] bits (7-Bit counter (MSB to LSB))
`WWDG_CR_WDGA`		7	Activation bit
`CFR`	`0x04`	32	WWDG Configuration register
`WWDG_CFR_W`		0:6	W[6:0] bits (7-bit window value)
`WWDG_CFR_WDGTB`		7:8	WDGTB[1:0] bits (Timer Base)
`WWDG_CFR_EWI`		9	Early Wakeup Interrupt
`SR`	`0x08`	32	WWDG Status register
`WWDG_SR_EWIF`		0	Early Wakeup Interrupt Flag

CRC — Контрольная сумма (раздел 12)

Регистр	Смещение	Бит	Назначение
`DR`	`0x00`	32	CRC Data register
`CRC_DR_DR`		0:31	Data register bits
`IDR`	`0x04`	8	CRC Independent data register
`CR`	`0x08`	32	CRC Control register
`CRC_CR_RESET`		0	RESET the CRC computation unit bit
`CRC_CR_POLYSIZE`		3:4	Polynomial size bits
`CRC_CR_REV_IN`		5:6	REV_IN Reverse Input Data bits
`CRC_CR_REV_OUT`		7	REV_OUT Reverse Output Data bits
`INIT`	`0x10`	32	Initial CRC value register
`CRC_INIT_INIT`		0:31	Initial CRC value bits
`POL`	`0x14`	32	CRC polynomial register
`CRC_POL_POL`		0:31	Coefficients of the polynomial

RTC — Часы реального времени (раздел 12)

Регистр	Смещение	Бит	Назначение
`TR`	`0x00`	32	RTC time register
`RTC_TR_SU`		0:3
`RTC_TR_ST`		4:6
`RTC_TR_MNU`		8:11
`RTC_TR_MNT`		12:14
`RTC_TR_HU`		16:19
`RTC_TR_HT`		20:21
`RTC_TR_PM`		22
`DR`	`0x04`	32	RTC date register
`RTC_DR_DU`		0:3
`RTC_DR_DT`		4:5
`RTC_DR_MU`		8:11
`RTC_DR_MT`		12
`RTC_DR_WDU`		13:15
`RTC_DR_YU`		16:19
`RTC_DR_YT`		20:23
`CR`	`0x08`	32	RTC control register
`RTC_CR_WUCKSEL`		0:2
`RTC_CR_TSEDGE`		3
`RTC_CR_REFCKON`		4
`RTC_CR_BYPSHAD`		5
`RTC_CR_FMT`		6
`RTC_CR_ALRAE`		8
`RTC_CR_ALRBE`		9
`RTC_CR_WUTE`		10
`RTC_CR_TSE`		11
`RTC_CR_ALRAIE`		12
`RTC_CR_ALRBIE`		13
`RTC_CR_WUTIE`		14
`RTC_CR_TSIE`		15
`RTC_CR_ADD1H`		16
`RTC_CR_SUB1H`		17
`RTC_CR_BKP`		18
`RTC_CR_COSEL`		19
`RTC_CR_POL`		20
`RTC_CR_OSEL`		21:22
`RTC_CR_COE`		23
`ISR`	`0x0C`	32	RTC initialization and status register
`RTC_ISR_ALRAWF`		0
`RTC_ISR_ALRBWF`		1
`RTC_ISR_WUTWF`		2
`RTC_ISR_SHPF`		3
`RTC_ISR_INITS`		4
`RTC_ISR_RSF`		5
`RTC_ISR_INITF`		6
`RTC_ISR_INIT`		7
`RTC_ISR_ALRAF`		8
`RTC_ISR_ALRBF`		9
`RTC_ISR_WUTF`		10
`RTC_ISR_TSF`		11
`RTC_ISR_TSOVF`		12
`RTC_ISR_TAMP1F`		13
`RTC_ISR_TAMP2F`		14
`RTC_ISR_TAMP3F`		15
`RTC_ISR_RECALPF`		16
`PRER`	`0x10`	32	RTC prescaler register
`RTC_PRER_PREDIV_S`		0:14
`RTC_PRER_PREDIV_A`		16:22
`WUTR`	`0x14`	32	RTC wakeup timer register
`RTC_WUTR_WUT`		0:15
`ALRMAR`	`0x1C`	32	RTC alarm A register
`RTC_ALRMAR_SU`		0:3
`RTC_ALRMAR_ST`		4:6
`RTC_ALRMAR_MSK1`		7
`RTC_ALRMAR_MNU`		8:11
`RTC_ALRMAR_MNT`		12:14
`RTC_ALRMAR_MSK2`		15
`RTC_ALRMAR_HU`		16:19
`RTC_ALRMAR_HT`		20:21
`RTC_ALRMAR_PM`		22
`RTC_ALRMAR_MSK3`		23
`RTC_ALRMAR_DU`		24:27
`RTC_ALRMAR_DT`		28:29
`RTC_ALRMAR_WDSEL`		30
`RTC_ALRMAR_MSK4`		31
`ALRMBR`	`0x20`	32	RTC alarm B register
`RTC_ALRMBR_SU`		0:3
`RTC_ALRMBR_ST`		4:6
`RTC_ALRMBR_MSK1`		7
`RTC_ALRMBR_MNU`		8:11
`RTC_ALRMBR_MNT`		12:14
`RTC_ALRMBR_MSK2`		15
`RTC_ALRMBR_HU`		16:19
`RTC_ALRMBR_HT`		20:21
`RTC_ALRMBR_PM`		22
`RTC_ALRMBR_MSK3`		23
`RTC_ALRMBR_DU`		24:27
`RTC_ALRMBR_DT`		28:29
`RTC_ALRMBR_WDSEL`		30
`RTC_ALRMBR_MSK4`		31
`WPR`	`0x24`	32	RTC write protection register
`RTC_WPR_KEY`		0:7
`SSR`	`0x28`	32	RTC sub second register
`RTC_SSR_SS`		0:15
`SHIFTR`	`0x2C`	32	RTC shift control register
`RTC_SHIFTR_SUBFS`		0:14
`RTC_SHIFTR_ADD1S`		31
`TSTR`	`0x30`	32	RTC time stamp time register
`RTC_TSTR_SU`		0:3
`RTC_TSTR_ST`		4:6
`RTC_TSTR_MNU`		8:11
`RTC_TSTR_MNT`		12:14
`RTC_TSTR_HU`		16:19
`RTC_TSTR_HT`		20:21
`RTC_TSTR_PM`		22
`TSDR`	`0x34`	32	RTC time stamp date register
`RTC_TSDR_DU`		0:3
`RTC_TSDR_DT`		4:5
`RTC_TSDR_MU`		8:11
`RTC_TSDR_MT`		12
`RTC_TSDR_WDU`		13:15
`TSSSR`	`0x38`	32	RTC time-stamp sub second register
`RTC_TSSSR_SS`		0:15
`CALR`	`0x3C`	32	RTC calibration register
`RTC_CALR_CALM`		0:8
`RTC_CALR_CALW16`		13
`RTC_CALR_CALW8`		14
`RTC_CALR_CALP`		15
`TAFCR`	`0x40`	32	RTC tamper and alternate function configuration register
`RTC_TAFCR_TAMP1E`		0
`RTC_TAFCR_TAMP1TRG`		1
`RTC_TAFCR_TAMPIE`		2
`RTC_TAFCR_TAMP2E`		3
`RTC_TAFCR_TAMP2TRG`		4
`RTC_TAFCR_TAMP3E`		5
`RTC_TAFCR_TAMP3TRG`		6
`RTC_TAFCR_TAMPTS`		7
`RTC_TAFCR_TAMPFREQ`		8:10
`RTC_TAFCR_TAMPFLT`		11:12
`RTC_TAFCR_TAMPPRCH`		13:14
`RTC_TAFCR_TAMPPUDIS`		15
`RTC_TAFCR_PC13VALUE`		18
`RTC_TAFCR_PC13MODE`		19
`RTC_TAFCR_PC14VALUE`		20
`RTC_TAFCR_PC14MODE`		21
`RTC_TAFCR_PC15VALUE`		22
`RTC_TAFCR_PC15MODE`		23
`ALRMASSR`	`0x44`	32	RTC alarm A sub second register
`RTC_ALRMASSR_SS`		0:14
`RTC_ALRMASSR_MASKSS`		24:27
`ALRMBSSR`	`0x48`	32	RTC alarm B sub second register
`RTC_ALRMBSSR_SS`		0:14
`RTC_ALRMBSSR_MASKSS`		24:27
`BKP0R`	`0x50`	32	RTC backup register 0
`BKP1R`	`0x54`	32	RTC backup register 1
`BKP2R`	`0x58`	32	RTC backup register 2
`BKP3R`	`0x5C`	32	RTC backup register 3
`BKP4R`	`0x60`	32	RTC backup register 4
`BKP5R`	`0x64`	32	RTC backup register 5
`BKP6R`	`0x68`	32	RTC backup register 6
`BKP7R`	`0x6C`	32	RTC backup register 7
`BKP8R`	`0x70`	32	RTC backup register 8
`BKP9R`	`0x74`	32	RTC backup register 9
`BKP10R`	`0x78`	32	RTC backup register 10
`BKP11R`	`0x7C`	32	RTC backup register 11
`BKP12R`	`0x80`	32	RTC backup register 12
`BKP13R`	`0x84`	32	RTC backup register 13
`BKP14R`	`0x88`	32	RTC backup register 14
`BKP15R`	`0x8C`	32	RTC backup register 15

TIM — Таймеры (раздел 13)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	TIM control register 1
`TIM_CR1_CEN`		0	Counter enable
`TIM_CR1_UDIS`		1	Update disable
`TIM_CR1_URS`		2	Update request source
`TIM_CR1_OPM`		3	One pulse mode
`TIM_CR1_DIR`		4	Direction
`TIM_CR1_CMS`		5:6	CMS[1:0] bits (Center-aligned mode selection)
`TIM_CR1_ARPE`		7	Auto-reload preload enable
`TIM_CR1_CKD`		8:9	CKD[1:0] bits (clock division)
`TIM_CR1_UIFREMAP`		11	Update interrupt flag remap
`CR2`	`0x04`	32	TIM control register 2
`TIM_CR2_CCPC`		0	Capture/Compare Preloaded Control
`TIM_CR2_CCUS`		2	Capture/Compare Control Update Selection
`TIM_CR2_CCDS`		3	Capture/Compare DMA Selection
`TIM_CR2_MMS`		4:6	MMS[2:0] bits (Master Mode Selection)
`TIM_CR2_TI1S`		7	TI1 Selection
`TIM_CR2_OIS1`		8	Output Idle state 1 (OC1 output)
`TIM_CR2_OIS1N`		9	Output Idle state 1 (OC1N output)
`TIM_CR2_OIS2`		10	Output Idle state 2 (OC2 output)
`TIM_CR2_OIS2N`		11	Output Idle state 2 (OC2N output)
`TIM_CR2_OIS3`		12	Output Idle state 3 (OC3 output)
`TIM_CR2_OIS3N`		13	Output Idle state 3 (OC3N output)
`TIM_CR2_OIS4`		14	Output Idle state 4 (OC4 output)
`TIM_CR2_OIS5`		16	Output Idle state 4 (OC4 output)
`TIM_CR2_OIS6`		18	Output Idle state 4 (OC4 output)
`TIM_CR2_MMS2`		20:23	MMS[2:0] bits (Master Mode Selection)
`SMCR`	`0x08`	32	TIM slave mode control register
`TIM_SMCR_SMS`		0:16	SMS[2:0] bits (Slave mode selection)
`TIM_SMCR_OCCS`		3	OCREF clear selection
`TIM_SMCR_TS`		4:6	TS[2:0] bits (Trigger selection)
`TIM_SMCR_MSM`		7	Master/slave mode
`TIM_SMCR_ETF`		8:11	ETF[3:0] bits (External trigger filter)
`TIM_SMCR_ETPS`		12:13	ETPS[1:0] bits (External trigger prescaler)
`TIM_SMCR_ECE`		14	External clock enable
`TIM_SMCR_ETP`		15	External trigger polarity
`DIER`	`0x0C`	32	TIM DMA/interrupt enable register
`TIM_DIER_UIE`		0	Update interrupt enable
`TIM_DIER_CC1IE`		1	Capture/Compare 1 interrupt enable
`TIM_DIER_CC2IE`		2	Capture/Compare 2 interrupt enable
`TIM_DIER_CC3IE`		3	Capture/Compare 3 interrupt enable
`TIM_DIER_CC4IE`		4	Capture/Compare 4 interrupt enable
`TIM_DIER_COMIE`		5	COM interrupt enable
`TIM_DIER_TIE`		6	Trigger interrupt enable
`TIM_DIER_BIE`		7	Break interrupt enable
`TIM_DIER_UDE`		8	Update DMA request enable
`TIM_DIER_CC1DE`		9	Capture/Compare 1 DMA request enable
`TIM_DIER_CC2DE`		10	Capture/Compare 2 DMA request enable
`TIM_DIER_CC3DE`		11	Capture/Compare 3 DMA request enable
`TIM_DIER_CC4DE`		12	Capture/Compare 4 DMA request enable
`TIM_DIER_COMDE`		13	COM DMA request enable
`TIM_DIER_TDE`		14	Trigger DMA request enable
`SR`	`0x10`	32	TIM status register
`TIM_SR_UIF`		0	Update interrupt Flag
`TIM_SR_CC1IF`		1	Capture/Compare 1 interrupt Flag
`TIM_SR_CC2IF`		2	Capture/Compare 2 interrupt Flag
`TIM_SR_CC3IF`		3	Capture/Compare 3 interrupt Flag
`TIM_SR_CC4IF`		4	Capture/Compare 4 interrupt Flag
`TIM_SR_COMIF`		5	COM interrupt Flag
`TIM_SR_TIF`		6	Trigger interrupt Flag
`TIM_SR_BIF`		7	Break interrupt Flag
`TIM_SR_B2IF`		8	Break2 interrupt Flag
`TIM_SR_CC1OF`		9	Capture/Compare 1 Overcapture Flag
`TIM_SR_CC2OF`		10	Capture/Compare 2 Overcapture Flag
`TIM_SR_CC3OF`		11	Capture/Compare 3 Overcapture Flag
`TIM_SR_CC4OF`		12	Capture/Compare 4 Overcapture Flag
`TIM_SR_CC5IF`		16	Capture/Compare 5 interrupt Flag
`TIM_SR_CC6IF`		17	Capture/Compare 6 interrupt Flag
`EGR`	`0x14`	32	TIM event generation register
`TIM_EGR_UG`		0	Update Generation
`TIM_EGR_CC1G`		1	Capture/Compare 1 Generation
`TIM_EGR_CC2G`		2	Capture/Compare 2 Generation
`TIM_EGR_CC3G`		3	Capture/Compare 3 Generation
`TIM_EGR_CC4G`		4	Capture/Compare 4 Generation
`TIM_EGR_COMG`		5	Capture/Compare Control Update Generation
`TIM_EGR_TG`		6	Trigger Generation
`TIM_EGR_BG`		7	Break Generation
`TIM_EGR_B2G`		8	Break Generation
`CCMR1`	`0x18`	32	TIM capture/compare mode register 1
`TIM_CCMR1_CC1S`		0:1	CC1S[1:0] bits (Capture/Compare 1 Selection)
`TIM_CCMR1_OC1FE`		2	Output Compare 1 Fast enable
`TIM_CCMR1_IC1PSC`		2:3	IC1PSC[1:0] bits (Input Capture 1 Prescaler)
`TIM_CCMR1_OC1PE`		3	Output Compare 1 Preload enable
`TIM_CCMR1_OC1M`		4:16	OC1M[2:0] bits (Output Compare 1 Mode)
`TIM_CCMR1_IC1F`		4:7	IC1F[3:0] bits (Input Capture 1 Filter)
`TIM_CCMR1_OC1CE`		7	Output Compare 1Clear Enable
`TIM_CCMR1_CC2S`		8:9	CC2S[1:0] bits (Capture/Compare 2 Selection)
`TIM_CCMR1_OC2FE`		10	Output Compare 2 Fast enable
`TIM_CCMR1_IC2PSC`		10:11	IC2PSC[1:0] bits (Input Capture 2 Prescaler)
`TIM_CCMR1_OC2PE`		11	Output Compare 2 Preload enable
`TIM_CCMR1_OC2M`		12:24	OC2M[2:0] bits (Output Compare 2 Mode)
`TIM_CCMR1_IC2F`		12:15	IC2F[3:0] bits (Input Capture 2 Filter)
`TIM_CCMR1_OC2CE`		15	Output Compare 2 Clear Enable
`CCMR2`	`0x1C`	32	TIM capture/compare mode register 2
`TIM_CCMR2_CC3S`		0:1	CC3S[1:0] bits (Capture/Compare 3 Selection)
`TIM_CCMR2_OC3FE`		2	Output Compare 3 Fast enable
`TIM_CCMR2_IC3PSC`		2:3	IC3PSC[1:0] bits (Input Capture 3 Prescaler)
`TIM_CCMR2_OC3PE`		3	Output Compare 3 Preload enable
`TIM_CCMR2_OC3M`		4:16	OC3M[2:0] bits (Output Compare 3 Mode)
`TIM_CCMR2_IC3F`		4:7	IC3F[3:0] bits (Input Capture 3 Filter)
`TIM_CCMR2_OC3CE`		7	Output Compare 3 Clear Enable
`TIM_CCMR2_CC4S`		8:9	CC4S[1:0] bits (Capture/Compare 4 Selection)
`TIM_CCMR2_OC4FE`		10	Output Compare 4 Fast enable
`TIM_CCMR2_IC4PSC`		10:11	IC4PSC[1:0] bits (Input Capture 4 Prescaler)
`TIM_CCMR2_OC4PE`		11	Output Compare 4 Preload enable
`TIM_CCMR2_OC4M`		12:24	OC4M[2:0] bits (Output Compare 4 Mode)
`TIM_CCMR2_IC4F`		12:15	IC4F[3:0] bits (Input Capture 4 Filter)
`TIM_CCMR2_OC4CE`		15	Output Compare 4 Clear Enable
`CCER`	`0x20`	32	TIM capture/compare enable register
`TIM_CCER_CC1E`		0	Capture/Compare 1 output enable
`TIM_CCER_CC1P`		1	Capture/Compare 1 output Polarity
`TIM_CCER_CC1NE`		2	Capture/Compare 1 Complementary output enable
`TIM_CCER_CC1NP`		3	Capture/Compare 1 Complementary output Polarity
`TIM_CCER_CC2E`		4	Capture/Compare 2 output enable
`TIM_CCER_CC2P`		5	Capture/Compare 2 output Polarity
`TIM_CCER_CC2NE`		6	Capture/Compare 2 Complementary output enable
`TIM_CCER_CC2NP`		7	Capture/Compare 2 Complementary output Polarity
`TIM_CCER_CC3E`		8	Capture/Compare 3 output enable
`TIM_CCER_CC3P`		9	Capture/Compare 3 output Polarity
`TIM_CCER_CC3NE`		10	Capture/Compare 3 Complementary output enable
`TIM_CCER_CC3NP`		11	Capture/Compare 3 Complementary output Polarity
`TIM_CCER_CC4E`		12	Capture/Compare 4 output enable
`TIM_CCER_CC4P`		13	Capture/Compare 4 output Polarity
`TIM_CCER_CC4NP`		15	Capture/Compare 4 Complementary output Polarity
`TIM_CCER_CC5E`		16	Capture/Compare 5 output enable
`TIM_CCER_CC5P`		17	Capture/Compare 5 output Polarity
`TIM_CCER_CC6E`		20	Capture/Compare 6 output enable
`TIM_CCER_CC6P`		21	Capture/Compare 6 output Polarity
`CNT`	`0x24`	32	TIM counter register
`TIM_CNT_CNT`		0:31	Counter Value
`TIM_CNT_UIFCPY`		31	Update interrupt flag copy
`PSC`	`0x28`	32	TIM prescaler
`TIM_PSC_PSC`		0:15	Prescaler Value
`ARR`	`0x2C`	32	TIM auto-reload register
`TIM_ARR_ARR`		0:31	actual auto-reload Value
`RCR`	`0x30`	32	TIM repetition counter register
`TIM_RCR_REP`		0:15	Repetition Counter Value
`CCR1`	`0x34`	32	TIM capture/compare register 1
`TIM_CCR1_CCR1`		0:15	Capture/Compare 1 Value
`CCR2`	`0x38`	32	TIM capture/compare register 2
`TIM_CCR2_CCR2`		0:15	Capture/Compare 2 Value
`CCR3`	`0x3C`	32	TIM capture/compare register 3
`TIM_CCR3_CCR3`		0:15	Capture/Compare 3 Value
`CCR4`	`0x40`	32	TIM capture/compare register 4
`TIM_CCR4_CCR4`		0:15	Capture/Compare 4 Value
`BDTR`	`0x44`	32	TIM break and dead-time register
`TIM_BDTR_DTG`		0:7	DTG[0:7] bits (Dead-Time Generator set-up)
`TIM_BDTR_LOCK`		8:9	LOCK[1:0] bits (Lock Configuration)
`TIM_BDTR_OSSI`		10	Off-State Selection for Idle mode
`TIM_BDTR_OSSR`		11	Off-State Selection for Run mode
`TIM_BDTR_BKE`		12	Break enable for Break1
`TIM_BDTR_BKP`		13	Break Polarity for Break1
`TIM_BDTR_AOE`		14	Automatic Output enable
`TIM_BDTR_MOE`		15	Main Output enable
`TIM_BDTR_BKF`		16:19	Break Filter for Break1
`TIM_BDTR_BK2F`		20:23	Break Filter for Break2
`TIM_BDTR_BK2E`		24	Break enable for Break2
`TIM_BDTR_BK2P`		25	Break Polarity for Break2
`DCR`	`0x48`	32	TIM DMA control register
`TIM_DCR_DBA`		0:4	DBA[4:0] bits (DMA Base Address)
`TIM_DCR_DBL`		8:12	DBL[4:0] bits (DMA Burst Length)
`DMAR`	`0x4C`	32	TIM DMA address for full transfer
`TIM_DMAR_DMAB`		0:15	DMA register for burst accesses
`OR`	`0x50`	32	TIM option register
`CCMR3`	`0x54`	32	TIM capture/compare mode register 3
`TIM_CCMR3_OC5FE`		2	Output Compare 5 Fast enable
`TIM_CCMR3_OC5PE`		3	Output Compare 5 Preload enable
`TIM_CCMR3_OC5M`		4:16	OC5M[2:0] bits (Output Compare 5 Mode)
`TIM_CCMR3_OC5CE`		7	Output Compare 5 Clear Enable
`TIM_CCMR3_OC6FE`		10	Output Compare 6 Fast enable
`TIM_CCMR3_OC6PE`		11	Output Compare 6 Preload enable
`TIM_CCMR3_OC6M`		12:24	OC6M[2:0] bits (Output Compare 6 Mode)
`TIM_CCMR3_OC6CE`		15	Output Compare 6 Clear Enable
`CCR5`	`0x58`	32	TIM capture/compare register5
`TIM_CCR5_CCR5`		0:31	Capture/Compare 5 Value
`TIM_CCR5_GC5C1`		29	Group Channel 5 and Channel 1
`TIM_CCR5_GC5C2`		30	Group Channel 5 and Channel 2
`TIM_CCR5_GC5C3`		31	Group Channel 5 and Channel 3
`CCR6`	`0x5C`	32	TIM capture/compare register 4
`TIM_CCR6_CCR6`		0:15	Capture/Compare 6 Value

ADC — АЦП (раздел 14)

Регистр	Смещение	Бит	Назначение
`ISR`	`0x00`	32	ADC Interrupt and Status Register
`ADC_ISR_ADRDY`		0	ADC ready flag
`ADC_ISR_EOSMP`		1	ADC group regular end of sampling flag
`ADC_ISR_EOC`		2	ADC group regular end of unitary conversion flag
`ADC_ISR_EOS`		3	ADC group regular end of sequence conversions flag
`ADC_ISR_OVR`		4	ADC group regular overrun flag
`ADC_ISR_JEOC`		5	ADC group injected end of unitary conversion flag
`ADC_ISR_JEOS`		6	ADC group injected end of sequence conversions flag
`ADC_ISR_AWD1`		7	ADC analog watchdog 1 flag
`ADC_ISR_AWD2`		8	ADC analog watchdog 2 flag
`ADC_ISR_AWD3`		9	ADC analog watchdog 3 flag
`ADC_ISR_JQOVF`		10	ADC group injected contexts queue overflow flag
`IER`	`0x04`	32	ADC Interrupt Enable Register
`ADC_IER_ADRDYIE`		0	ADC ready interrupt
`ADC_IER_EOSMPIE`		1	ADC group regular end of sampling interrupt
`ADC_IER_EOCIE`		2	ADC group regular end of unitary conversion interrupt
`ADC_IER_EOSIE`		3	ADC group regular end of sequence conversions interrupt
`ADC_IER_OVRIE`		4	ADC group regular overrun interrupt
`ADC_IER_JEOCIE`		5	ADC group injected end of unitary conversion interrupt
`ADC_IER_JEOSIE`		6	ADC group injected end of sequence conversions interrupt
`ADC_IER_AWD1IE`		7	ADC analog watchdog 1 interrupt
`ADC_IER_AWD2IE`		8	ADC analog watchdog 2 interrupt
`ADC_IER_AWD3IE`		9	ADC analog watchdog 3 interrupt
`ADC_IER_JQOVFIE`		10	ADC group injected contexts queue overflow interrupt
`CR`	`0x08`	32	ADC control register
`ADC_CR_ADEN`		0	ADC enable
`ADC_CR_ADDIS`		1	ADC disable
`ADC_CR_ADSTART`		2	ADC group regular conversion start
`ADC_CR_JADSTART`		3	ADC group injected conversion start
`ADC_CR_ADSTP`		4	ADC group regular conversion stop
`ADC_CR_JADSTP`		5	ADC group injected conversion stop
`ADC_CR_ADVREGEN`		28:29	ADC voltage regulator enable
`ADC_CR_ADCALDIF`		30	ADC differential mode for calibration
`ADC_CR_ADCAL`		31	ADC calibration
`CFGR`	`0x0C`	32	ADC Configuration register
`ADC_CFGR_DMAEN`		0	ADC DMA enable
`ADC_CFGR_DMACFG`		1	ADC DMA configuration
`ADC_CFGR_RES`		3:4	ADC data resolution
`ADC_CFGR_ALIGN`		5	ADC data alignement
`ADC_CFGR_EXTSEL`		6:9	ADC group regular external trigger source
`ADC_CFGR_EXTEN`		10:11	ADC group regular external trigger polarity
`ADC_CFGR_OVRMOD`		12	ADC group regular overrun configuration
`ADC_CFGR_CONT`		13	ADC group regular continuous conversion mode
`ADC_CFGR_AUTDLY`		14	ADC low power auto wait
`ADC_CFGR_AUTOFF`		15	ADC low power auto power off
`ADC_CFGR_DISCEN`		16	ADC group regular sequencer discontinuous mode
`ADC_CFGR_DISCNUM`		17:19	ADC Discontinuous mode channel count
`ADC_CFGR_JDISCEN`		20	ADC Discontinuous mode on injected channels
`ADC_CFGR_JQM`		21	ADC group injected contexts queue mode
`ADC_CFGR_AWD1SGL`		22	ADC analog watchdog 1 monitoring a single channel or all channels
`ADC_CFGR_AWD1EN`		23	ADC analog watchdog 1 enable on scope ADC group regular
`ADC_CFGR_JAWD1EN`		24	ADC analog watchdog 1 enable on scope ADC group injected
`ADC_CFGR_JAUTO`		25	ADC group injected automatic trigger mode
`ADC_CFGR_AWD1CH`		26:30	ADC analog watchdog 1 monitored channel selection
`SMPR1`	`0x14`	32	ADC sample time register 1
`ADC_SMPR1_SMP0`		0:2	ADC channel 0 sampling time selection
`ADC_SMPR1_SMP1`		3:5	ADC channel 1 sampling time selection
`ADC_SMPR1_SMP2`		6:8	ADC channel 2 sampling time selection
`ADC_SMPR1_SMP3`		9:11	ADC channel 3 sampling time selection
`ADC_SMPR1_SMP4`		12:14	ADC channel 4 sampling time selection
`ADC_SMPR1_SMP5`		15:17	ADC channel 5 sampling time selection
`ADC_SMPR1_SMP6`		18:20	ADC channel 6 sampling time selection
`ADC_SMPR1_SMP7`		21:23	ADC channel 7 sampling time selection
`ADC_SMPR1_SMP8`		24:26	ADC channel 8 sampling time selection
`ADC_SMPR1_SMP9`		27:29	ADC channel 9 sampling time selection
`SMPR2`	`0x18`	32	ADC sample time register 2
`ADC_SMPR2_SMP10`		0:2	ADC channel 10 sampling time selection
`ADC_SMPR2_SMP11`		3:5	ADC channel 11 sampling time selection
`ADC_SMPR2_SMP12`		6:8	ADC channel 12 sampling time selection
`ADC_SMPR2_SMP13`		9:11	ADC channel 13 sampling time selection
`ADC_SMPR2_SMP14`		12:14	ADC channel 14 sampling time selection
`ADC_SMPR2_SMP15`		15:17	ADC channel 15 sampling time selection
`ADC_SMPR2_SMP16`		18:20	ADC channel 16 sampling time selection
`ADC_SMPR2_SMP17`		21:23	ADC channel 17 sampling time selection
`ADC_SMPR2_SMP18`		24:26	ADC channel 18 sampling time selection
`TR1`	`0x20`	32	ADC watchdog threshold register 1
`ADC_TR1_LT1`		0:11	ADC analog watchdog 1 threshold low
`ADC_TR1_HT1`		16:27	ADC Analog watchdog 1 threshold high
`TR2`	`0x24`	32	ADC watchdog threshold register 2
`ADC_TR2_LT2`		0:7	ADC analog watchdog 2 threshold low
`ADC_TR2_HT2`		16:23	ADC analog watchdog 2 threshold high
`TR3`	`0x28`	32	ADC watchdog threshold register 3
`ADC_TR3_LT3`		0:7	ADC analog watchdog 3 threshold low
`ADC_TR3_HT3`		16:23	ADC analog watchdog 3 threshold high
`SQR1`	`0x30`	32	ADC regular sequence register 1
`ADC_SQR1_L`		0:3	ADC group regular sequencer scan length
`ADC_SQR1_SQ1`		6:10	ADC group regular sequencer rank 1
`ADC_SQR1_SQ2`		12:16	ADC group regular sequencer rank 2
`ADC_SQR1_SQ3`		18:22	ADC group regular sequencer rank 3
`ADC_SQR1_SQ4`		24:28	ADC group regular sequencer rank 4
`SQR2`	`0x34`	32	ADC regular sequence register 2
`ADC_SQR2_SQ5`		0:4	ADC group regular sequencer rank 5
`ADC_SQR2_SQ6`		6:10	ADC group regular sequencer rank 6
`ADC_SQR2_SQ7`		12:16	ADC group regular sequencer rank 7
`ADC_SQR2_SQ8`		18:22	ADC group regular sequencer rank 8
`ADC_SQR2_SQ9`		24:28	ADC group regular sequencer rank 9
`SQR3`	`0x38`	32	ADC regular sequence register 3
`ADC_SQR3_SQ10`		0:4	ADC group regular sequencer rank 10
`ADC_SQR3_SQ11`		6:10	ADC group regular sequencer rank 11
`ADC_SQR3_SQ12`		12:16	ADC group regular sequencer rank 12
`ADC_SQR3_SQ13`		18:22	ADC group regular sequencer rank 13
`ADC_SQR3_SQ14`		24:28	ADC group regular sequencer rank 14
`SQR4`	`0x3C`	32	ADC regular sequence register 4
`ADC_SQR4_SQ15`		0:4	ADC group regular sequencer rank 15
`ADC_SQR4_SQ16`		6:10	ADC group regular sequencer rank 16
`DR`	`0x40`	32	ADC regular data register
`ADC_DR_RDATA`		0:15	ADC group regular conversion data
`JSQR`	`0x4C`	32	ADC injected sequence register
`ADC_JSQR_JL`		0:1	ADC group injected sequencer scan length
`ADC_JSQR_JEXTSEL`		2:5	ADC group injected external trigger source
`ADC_JSQR_JEXTEN`		6:7	ADC group injected external trigger polarity
`ADC_JSQR_JSQ1`		8:12	ADC group injected sequencer rank 1
`ADC_JSQR_JSQ2`		14:18	ADC group injected sequencer rank 2
`ADC_JSQR_JSQ3`		20:24	ADC group injected sequencer rank 3
`ADC_JSQR_JSQ4`		26:30	ADC group injected sequencer rank 4
`OFR1`	`0x60`	32	ADC offset register 1
`ADC_OFR1_OFFSET1`		0:11	ADC offset number 1 offset level
`ADC_OFR1_OFFSET1_CH`		26:30	ADC offset number 1 channel selection
`ADC_OFR1_OFFSET1_EN`		31	ADC offset number 1 enable
`OFR2`	`0x64`	32	ADC offset register 2
`ADC_OFR2_OFFSET2`		0:11	ADC offset number 2 offset level
`ADC_OFR2_OFFSET2_CH`		26:30	ADC offset number 2 channel selection
`ADC_OFR2_OFFSET2_EN`		31	ADC offset number 2 enable
`OFR3`	`0x68`	32	ADC offset register 3
`ADC_OFR3_OFFSET3`		0:11	ADC offset number 3 offset level
`ADC_OFR3_OFFSET3_CH`		26:30	ADC offset number 3 channel selection
`ADC_OFR3_OFFSET3_EN`		31	ADC offset number 3 enable
`OFR4`	`0x6C`	32	ADC offset register 4
`ADC_OFR4_OFFSET4`		0:11	ADC offset number 4 offset level
`ADC_OFR4_OFFSET4_CH`		26:30	ADC offset number 4 channel selection
`ADC_OFR4_OFFSET4_EN`		31	ADC offset number 4 enable
`JDR1`	`0x80`	32	ADC injected data register 1
`ADC_JDR1_JDATA`		0:15	ADC group injected sequencer rank 1 conversion data
`JDR2`	`0x84`	32	ADC injected data register 2
`ADC_JDR2_JDATA`		0:15	ADC group injected sequencer rank 2 conversion data
`JDR3`	`0x88`	32	ADC injected data register 3
`ADC_JDR3_JDATA`		0:15	ADC group injected sequencer rank 3 conversion data
`JDR4`	`0x8C`	32	ADC injected data register 4
`ADC_JDR4_JDATA`		0:15	ADC group injected sequencer rank 4 conversion data
`AWD2CR`	`0xA0`	32	ADC Analog Watchdog 2 Configuration Register
`ADC_AWD2CR_AWD2CH`		0:17	ADC analog watchdog 2 monitored channel selection
`AWD3CR`	`0xA4`	32	ADC Analog Watchdog 3 Configuration Register
`ADC_AWD3CR_AWD3CH`		0:17	ADC analog watchdog 3 monitored channel selection
`DIFSEL`	`0xB0`	32	ADC Differential Mode Selection Register
`ADC_DIFSEL_DIFSEL`		0:17	ADC channel differential or single-ended mode
`CALFACT`	`0xB4`	32	ADC Calibration Factors
`ADC_CALFACT_CALFACT_S`		0:6	ADC calibration factor in single-ended mode
`ADC_CALFACT_CALFACT_D`		16:22	ADC calibration factor in differential mode

ADC_Common — АЦП: общие регистры (раздел 14)

Регистр	Смещение	Бит	Назначение
`CSR`	`0x00`	32	ADC Common status register
`ADC_CSR_ADRDY_MST`		0	ADC multimode master ready flag
`ADC_CSR_EOSMP_MST`		1	ADC multimode master group regular end of sampling flag
`ADC_CSR_EOC_MST`		2	ADC multimode master group regular end of unitary conversion flag
`ADC_CSR_EOS_MST`		3	ADC multimode master group regular end of sequence conversions flag
`ADC_CSR_OVR_MST`		4	ADC multimode master group regular overrun flag
`ADC_CSR_JEOC_MST`		5	ADC multimode master group injected end of unitary conversion flag
`ADC_CSR_JEOS_MST`		6	ADC multimode master group injected end of sequence conversions flag
`ADC_CSR_AWD1_MST`		7	ADC multimode master analog watchdog 1 flag
`ADC_CSR_AWD2_MST`		8	ADC multimode master analog watchdog 2 flag
`ADC_CSR_AWD3_MST`		9	ADC multimode master analog watchdog 3 flag
`ADC_CSR_JQOVF_MST`		10	ADC multimode master group injected contexts queue overflow flag
`ADC_CSR_ADRDY_SLV`		16	ADC multimode slave ready flag
`ADC_CSR_EOSMP_SLV`		17	ADC multimode slave group regular end of sampling flag
`ADC_CSR_EOC_SLV`		18	ADC multimode slave group regular end of unitary conversion flag
`ADC_CSR_EOS_SLV`		19	ADC multimode slave group regular end of sequence conversions flag
`ADC_CSR_OVR_SLV`		20	ADC multimode slave group regular overrun flag
`ADC_CSR_JEOC_SLV`		21	ADC multimode slave group injected end of unitary conversion flag
`ADC_CSR_JEOS_SLV`		22	ADC multimode slave group injected end of sequence conversions flag
`ADC_CSR_AWD1_SLV`		23	ADC multimode slave analog watchdog 1 flag
`ADC_CSR_AWD2_SLV`		24	ADC multimode slave analog watchdog 2 flag
`ADC_CSR_AWD3_SLV`		25	ADC multimode slave analog watchdog 3 flag
`ADC_CSR_JQOVF_SLV`		26	ADC multimode slave group injected contexts queue overflow flag
`CCR`	`0x08`	32	ADC common control register
`ADC_CCR_DUAL`		0:4	ADC multimode mode selection
`ADC_CCR_DELAY`		8:11	ADC multimode delay between 2 sampling phases
`ADC_CCR_DMACFG`		13	ADC multimode DMA transfer configuration
`ADC_CCR_MDMA`		14:15	ADC multimode DMA transfer enable
`ADC_CCR_CKMODE`		16:17	ADC common clock source and prescaler (prescaler only for clock source synchronous)
`ADC_CCR_VREFEN`		22	ADC internal path to VrefInt enable
`ADC_CCR_TSEN`		23	ADC internal path to temperature sensor enable
`ADC_CCR_VBATEN`		24	ADC internal path to battery voltage enable
`CDR`	`0x0C`	32
`ADC_CDR_RDATA_MST`		0:15	ADC multimode master group regular conversion data
`ADC_CDR_RDATA_SLV`		16:31	ADC multimode slave group regular conversion data

DAC — ЦАП (раздел 15)

Регистр	Смещение	Бит	Назначение
`CR`	`0x00`	32	DAC control register
`DAC_CR_EN1`		0	DAC channel1 enable
`DAC_CR_BOFF1`		1	DAC channel1 output buffer disable
`DAC_CR_TEN1`		2	DAC channel1 Trigger enable
`DAC_CR_TSEL1`		3:5	TSEL1[2:0] (DAC channel1 Trigger selection)
`DAC_CR_WAVE1`		6:7	WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
`DAC_CR_MAMP1`		8:11	MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
`DAC_CR_DMAEN1`		12	DAC channel1 DMA enable
`DAC_CR_DMAUDRIE1`		13	DAC channel1 DMA underrun IT enable
`DAC_CR_EN2`		16	DAC channel2 enable
`DAC_CR_BOFF2`		17	DAC channel2 output buffer disable
`DAC_CR_TEN2`		18	DAC channel2 Trigger enable
`DAC_CR_TSEL2`		19:21	TSEL2[2:0] (DAC channel2 Trigger selection)
`DAC_CR_WAVE2`		22:23	WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)
`DAC_CR_MAMP2`		24:27	MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)
`DAC_CR_DMAEN2`		28	DAC channel2 DMA enabled
`DAC_CR_DMAUDRIE2`		29	DAC channel2 DMA underrun IT enable
`SWTRIGR`	`0x04`	32	DAC software trigger register
`DAC_SWTRIGR_SWTRIG1`		0	DAC channel1 software trigger
`DAC_SWTRIGR_SWTRIG2`		1	DAC channel2 software trigger
`DHR12R1`	`0x08`	32	DAC channel1 12-bit right-aligned data holding register
`DAC_DHR12R1_DACC1DHR`		0:11	DAC channel1 12-bit Right aligned data
`DHR12L1`	`0x0C`	32	DAC channel1 12-bit left aligned data holding register
`DAC_DHR12L1_DACC1DHR`		4:15	DAC channel1 12-bit Left aligned data
`DHR8R1`	`0x10`	32	DAC channel1 8-bit right aligned data holding register
`DAC_DHR8R1_DACC1DHR`		0:7	DAC channel1 8-bit Right aligned data
`DHR12R2`	`0x14`	32	DAC channel2 12-bit right aligned data holding register
`DAC_DHR12R2_DACC2DHR`		0:11	DAC channel2 12-bit Right aligned data
`DHR12L2`	`0x18`	32	DAC channel2 12-bit left aligned data holding register
`DAC_DHR12L2_DACC2DHR`		4:15	DAC channel2 12-bit Left aligned data
`DHR8R2`	`0x1C`	32	DAC channel2 8-bit right-aligned data holding register
`DAC_DHR8R2_DACC2DHR`		0:7	DAC channel2 8-bit Right aligned data
`DHR12RD`	`0x20`	32	Dual DAC 12-bit right-aligned data holding register
`DAC_DHR12RD_DACC1DHR`		0:11	DAC channel1 12-bit Right aligned data
`DAC_DHR12RD_DACC2DHR`		16:27	DAC channel2 12-bit Right aligned data
`DHR12LD`	`0x24`	32	DUAL DAC 12-bit left aligned data holding register
`DAC_DHR12LD_DACC1DHR`		4:15	DAC channel1 12-bit Left aligned data
`DAC_DHR12LD_DACC2DHR`		20:31	DAC channel2 12-bit Left aligned data
`DHR8RD`	`0x28`	32	DUAL DAC 8-bit right aligned data holding register
`DAC_DHR8RD_DACC1DHR`		0:7	DAC channel1 8-bit Right aligned data
`DAC_DHR8RD_DACC2DHR`		8:15	DAC channel2 8-bit Right aligned data
`DOR1`	`0x2C`	32	DAC channel1 data output register
`DAC_DOR1_DACC1DOR`		0:11	DAC channel1 data output
`DOR2`	`0x30`	32	DAC channel2 data output register
`DAC_DOR2_DACC2DOR`		0:11	DAC channel2 data output
`SR`	`0x34`	32	DAC status register
`DAC_SR_DMAUDR1`		13	DAC channel1 DMA underrun flag
`DAC_SR_DMAUDR2`		29	DAC channel2 DMA underrun flag

COMP — Компаратор (раздел 44)

Регистр	Смещение	Бит	Назначение
`CSR`	`0x00`	32	COMP control and status register
`COMP_CSR_COMPxEN`		0	COMPx enable
`COMP_CSR_COMPxSW1`		1	COMPx SW1 switch control
`COMP_CSR_COMPxMODE`		2:3	COMPx power mode
`COMP_CSR_COMPxINSEL`		4:6	COMPx inverting input select
`COMP_CSR_COMPxNONINSEL`		7	COMPx non inverting input select
`COMP_CSR_COMPxWNDWEN`		9	COMPx window mode enable
`COMP_CSR_COMPxOUTSEL`		10:13	COMPx output select
`COMP_CSR_COMPxPOL`		15	COMPx output polarity
`COMP_CSR_COMPxHYST`		16:17	COMPx hysteresis
`COMP_CSR_COMPxBLANKING`		18:19	COMPx blanking
`COMP_CSR_COMPxOUT`		30	COMPx output level
`COMP_CSR_COMPxLOCK`		31	COMPx lock

OPAMP — Операционный усилитель (раздел 44)

Регистр	Смещение	Бит	Назначение
`CSR`	`0x00`	32	OPAMP control and status register
`OPAMP_CSR_OPAMPxEN`		0	OPAMP enable
`OPAMP_CSR_FORCEVP`		1	Connect the internal references to the plus input of the OPAMPX
`OPAMP_CSR_VPSEL`		2:3	Non inverting input selection
`OPAMP_CSR_VMSEL`		5:6	Inverting input selection
`OPAMP_CSR_TCMEN`		7	Timer-Controlled Mux mode enable
`OPAMP_CSR_VMSSEL`		8	Inverting input secondary selection
`OPAMP_CSR_VPSSEL`		9:10	Non inverting input secondary selection
`OPAMP_CSR_CALON`		11	Calibration mode enable
`OPAMP_CSR_CALSEL`		12:13	Calibration selection
`OPAMP_CSR_PGGAIN`		14:17	Gain in PGA mode
`OPAMP_CSR_USERTRIM`		18	User trimming enable
`OPAMP_CSR_TRIMOFFSETP`		19:23	Offset trimming value (PMOS)
`OPAMP_CSR_TRIMOFFSETN`		24:28	Offset trimming value (NMOS)
`OPAMP_CSR_TSTREF`		29	It enables the switch to put out the internal reference
`OPAMP_CSR_OUTCAL`		30	OPAMP ouput status flag
`OPAMP_CSR_LOCK`		31	OPAMP lock

USART — UART / USART / LPUART (раздел 16)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	USART Control register 1
`USART_CR1_UE`		0	USART Enable
`USART_CR1_UESM`		1	USART Enable in STOP Mode
`USART_CR1_RE`		2	Receiver Enable
`USART_CR1_TE`		3	Transmitter Enable
`USART_CR1_IDLEIE`		4	IDLE Interrupt Enable
`USART_CR1_RXNEIE`		5	RXNE Interrupt Enable
`USART_CR1_TCIE`		6	Transmission Complete Interrupt Enable
`USART_CR1_TXEIE`		7	TXE Interrupt Enable
`USART_CR1_PEIE`		8	PE Interrupt Enable
`USART_CR1_PS`		9	Parity Selection
`USART_CR1_PCE`		10	Parity Control Enable
`USART_CR1_WAKE`		11	Receiver Wakeup method
`USART_CR1_M`		12	Word length
`USART_CR1_M0`		12	SmartCard Word length
`USART_CR1_MME`		13	Mute Mode Enable
`USART_CR1_CMIE`		14	Character match interrupt enable
`USART_CR1_OVER8`		15	Oversampling by 8-bit or 16-bit mode
`USART_CR1_DEDT`		16:20	DEDT[4:0] bits (Driver Enable Deassertion Time)
`USART_CR1_DEAT`		21:25	DEAT[4:0] bits (Driver Enable Assertion Time)
`USART_CR1_RTOIE`		26	Receive Time Out interrupt enable
`USART_CR1_EOBIE`		27	End of Block interrupt enable
`CR2`	`0x04`	32	USART Control register 2
`USART_CR2_ADDM7`		4	7-bit or 4-bit Address Detection
`USART_CR2_LBDL`		5	LIN Break Detection Length
`USART_CR2_LBDIE`		6	LIN Break Detection Interrupt Enable
`USART_CR2_LBCL`		8	Last Bit Clock pulse
`USART_CR2_CPHA`		9	Clock Phase
`USART_CR2_CPOL`		10	Clock Polarity
`USART_CR2_CLKEN`		11	Clock Enable
`USART_CR2_STOP`		12:13	STOP[1:0] bits (STOP bits)
`USART_CR2_LINEN`		14	LIN mode enable
`USART_CR2_SWAP`		15	SWAP TX/RX pins
`USART_CR2_RXINV`		16	RX pin active level inversion
`USART_CR2_TXINV`		17	TX pin active level inversion
`USART_CR2_DATAINV`		18	Binary data inversion
`USART_CR2_MSBFIRST`		19	Most Significant Bit First
`USART_CR2_ABREN`		20	Auto Baud-Rate Enable
`USART_CR2_ABRMODE`		21:22	ABRMOD[1:0] bits (Auto Baud-Rate Mode)
`USART_CR2_RTOEN`		23	Receiver Time-Out enable
`USART_CR2_ADD`		24:31	Address of the USART node
`CR3`	`0x08`	32	USART Control register 3
`USART_CR3_EIE`		0	Error Interrupt Enable
`USART_CR3_IREN`		1	IrDA mode Enable
`USART_CR3_IRLP`		2	IrDA Low-Power
`USART_CR3_HDSEL`		3	Half-Duplex Selection
`USART_CR3_NACK`		4	SmartCard NACK enable
`USART_CR3_SCEN`		5	SmartCard mode enable
`USART_CR3_DMAR`		6	DMA Enable Receiver
`USART_CR3_DMAT`		7	DMA Enable Transmitter
`USART_CR3_RTSE`		8	RTS Enable
`USART_CR3_CTSE`		9	CTS Enable
`USART_CR3_CTSIE`		10	CTS Interrupt Enable
`USART_CR3_ONEBIT`		11	One sample bit method enable
`USART_CR3_OVRDIS`		12	Overrun Disable
`USART_CR3_DDRE`		13	DMA Disable on Reception Error
`USART_CR3_DEM`		14	Driver Enable Mode
`USART_CR3_DEP`		15	Driver Enable Polarity Selection
`USART_CR3_SCARCNT`		17:19	SCARCNT[2:0] bits (SmartCard Auto-Retry Count)
`USART_CR3_WUS`		20:21	WUS[1:0] bits (Wake UP Interrupt Flag Selection)
`USART_CR3_WUFIE`		22	Wake Up Interrupt Enable
`BRR`	`0x0C`	32	USART Baud rate register
`USART_BRR_DIV_FRACTION`		0:3	Fraction of USARTDIV
`USART_BRR_DIV_MANTISSA`		4:15	Mantissa of USARTDIV
`GTPR`	`0x10`	32	USART Guard time and prescaler register
`USART_GTPR_PSC`		0:7	PSC[7:0] bits (Prescaler value)
`USART_GTPR_GT`		8:15	GT[7:0] bits (Guard time value)
`RTOR`	`0x14`	32	USART Receiver Time Out register
`USART_RTOR_RTO`		0:23	Receiver Time Out Value
`USART_RTOR_BLEN`		24:31	Block Length
`RQR`	`0x18`	32	USART Request register
`USART_RQR_ABRRQ`		0	Auto-Baud Rate Request
`USART_RQR_SBKRQ`		1	Send Break Request
`USART_RQR_MMRQ`		2	Mute Mode Request
`USART_RQR_RXFRQ`		3	Receive Data flush Request
`USART_RQR_TXFRQ`		4	Transmit data flush Request
`ISR`	`0x1C`	32	USART Interrupt and status register
`USART_ISR_PE`		0	Parity Error
`USART_ISR_FE`		1	Framing Error
`USART_ISR_NE`		2	Noise detected Flag
`USART_ISR_ORE`		3	OverRun Error
`USART_ISR_IDLE`		4	IDLE line detected
`USART_ISR_RXNE`		5	Read Data Register Not Empty
`USART_ISR_TC`		6	Transmission Complete
`USART_ISR_TXE`		7	Transmit Data Register Empty
`USART_ISR_LBDF`		8	LIN Break Detection Flag
`USART_ISR_CTSIF`		9	CTS interrupt flag
`USART_ISR_CTS`		10	CTS flag
`USART_ISR_RTOF`		11	Receiver Time Out
`USART_ISR_EOBF`		12	End Of Block Flag
`USART_ISR_ABRE`		14	Auto-Baud Rate Error
`USART_ISR_ABRF`		15	Auto-Baud Rate Flag
`USART_ISR_BUSY`		16	Busy Flag
`USART_ISR_CMF`		17	Character Match Flag
`USART_ISR_SBKF`		18	Send Break Flag
`USART_ISR_RWU`		19	Receive Wake Up from mute mode Flag
`USART_ISR_WUF`		20	Wake Up from stop mode Flag
`USART_ISR_TEACK`		21	Transmit Enable Acknowledge Flag
`USART_ISR_REACK`		22	Receive Enable Acknowledge Flag
`ICR`	`0x20`	32	USART Interrupt flag Clear register
`USART_ICR_PECF`		0	Parity Error Clear Flag
`USART_ICR_FECF`		1	Framing Error Clear Flag
`USART_ICR_NCF`		2	Noise detected Clear Flag
`USART_ICR_ORECF`		3	OverRun Error Clear Flag
`USART_ICR_IDLECF`		4	IDLE line detected Clear Flag
`USART_ICR_TCCF`		6	Transmission Complete Clear Flag
`USART_ICR_LBDCF`		8	LIN Break Detection Clear Flag
`USART_ICR_CTSCF`		9	CTS Interrupt Clear Flag
`USART_ICR_RTOCF`		11	Receiver Time Out Clear Flag
`USART_ICR_EOBCF`		12	End Of Block Clear Flag
`USART_ICR_CMCF`		17	Character Match Clear Flag
`USART_ICR_WUCF`		20	Wake Up from stop mode Clear Flag
`RDR`	`0x24`	16	USART Receive Data register
`USART_RDR_RDR`		0:8	RDR[8:0] bits (Receive Data value)
`TDR`	`0x28`	16	USART Transmit Data register
`USART_TDR_TDR`		0:8	TDR[8:0] bits (Transmit Data value)

I2C — I²C (раздел 17)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	I2C Control register 1
`I2C_CR1_PE`		0	Peripheral enable
`I2C_CR1_TXIE`		1	TX interrupt enable
`I2C_CR1_RXIE`		2	RX interrupt enable
`I2C_CR1_ADDRIE`		3	Address match interrupt enable
`I2C_CR1_NACKIE`		4	NACK received interrupt enable
`I2C_CR1_STOPIE`		5	STOP detection interrupt enable
`I2C_CR1_TCIE`		6	Transfer complete interrupt enable
`I2C_CR1_ERRIE`		7	Errors interrupt enable
`I2C_CR1_DNF`		8:11	Digital noise filter
`I2C_CR1_ANFOFF`		12	Analog noise filter OFF
`I2C_CR1_SWRST`		13	Software reset
`I2C_CR1_TXDMAEN`		14	DMA transmission requests enable
`I2C_CR1_RXDMAEN`		15	DMA reception requests enable
`I2C_CR1_SBC`		16	Slave byte control
`I2C_CR1_NOSTRETCH`		17	Clock stretching disable
`I2C_CR1_WUPEN`		18	Wakeup from STOP enable
`I2C_CR1_GCEN`		19	General call enable
`I2C_CR1_SMBHEN`		20	SMBus host address enable
`I2C_CR1_SMBDEN`		21	SMBus device default address enable
`I2C_CR1_ALERTEN`		22	SMBus alert enable
`I2C_CR1_PECEN`		23	PEC enable
`CR2`	`0x04`	32	I2C Control register 2
`I2C_CR2_SADD`		0:9	Slave address (master mode)
`I2C_CR2_RD_WRN`		10	Transfer direction (master mode)
`I2C_CR2_ADD10`		11	10-bit addressing mode (master mode)
`I2C_CR2_HEAD10R`		12	10-bit address header only read direction (master mode)
`I2C_CR2_START`		13	START generation
`I2C_CR2_STOP`		14	STOP generation (master mode)
`I2C_CR2_NACK`		15	NACK generation (slave mode)
`I2C_CR2_NBYTES`		16:23	Number of bytes
`I2C_CR2_RELOAD`		24	NBYTES reload mode
`I2C_CR2_AUTOEND`		25	Automatic end mode (master mode)
`I2C_CR2_PECBYTE`		26	Packet error checking byte
`OAR1`	`0x08`	32	I2C Own address 1 register
`I2C_OAR1_OA1`		0:9	Interface own address 1
`I2C_OAR1_OA1MODE`		10	Own address 1 10-bit mode
`I2C_OAR1_OA1EN`		15	Own address 1 enable
`OAR2`	`0x0C`	32	I2C Own address 2 register
`I2C_OAR2_OA2`		1:7	Interface own address 2
`I2C_OAR2_OA2MSK`		8:10	Own address 2 masks
`I2C_OAR2_OA2MASK01`		8	OA2[1] is masked, Only OA2[7:2] are compared
`I2C_OAR2_OA2MASK03`		8:9	OA2[3:1] is masked, Only OA2[7:4] are compared
`I2C_OAR2_OA2MASK05`		8:10	OA2[5:1] is masked, Only OA2[7:6] are compared
`I2C_OAR2_OA2MASK07`		8:10	OA2[7:1] is masked, No comparison is done
`I2C_OAR2_OA2MASK02`		9	OA2[2:1] is masked, Only OA2[7:3] are compared
`I2C_OAR2_OA2MASK06`		9:10	OA2[6:1] is masked, Only OA2[7] are compared
`I2C_OAR2_OA2MASK04`		10	OA2[4:1] is masked, Only OA2[7:5] are compared
`I2C_OAR2_OA2EN`		15	Own address 2 enable
`TIMINGR`	`0x10`	32	I2C Timing register
`I2C_TIMINGR_SCLL`		0:7	SCL low period (master mode)
`I2C_TIMINGR_SCLH`		8:15	SCL high period (master mode)
`I2C_TIMINGR_SDADEL`		16:19	Data hold time
`I2C_TIMINGR_SCLDEL`		20:23	Data setup time
`I2C_TIMINGR_PRESC`		28:31	Timings prescaler
`TIMEOUTR`	`0x14`	32	I2C Timeout register
`I2C_TIMEOUTR_TIMEOUTA`		0:11	Bus timeout A
`I2C_TIMEOUTR_TIDLE`		12	Idle clock timeout detection
`I2C_TIMEOUTR_TIMOUTEN`		15	Clock timeout enable
`I2C_TIMEOUTR_TIMEOUTB`		16:27	Bus timeout B
`I2C_TIMEOUTR_TEXTEN`		31	Extended clock timeout enable
`ISR`	`0x18`	32	I2C Interrupt and status register
`I2C_ISR_TXE`		0	Transmit data register empty
`I2C_ISR_TXIS`		1	Transmit interrupt status
`I2C_ISR_RXNE`		2	Receive data register not empty
`I2C_ISR_ADDR`		3	Address matched (slave mode)
`I2C_ISR_NACKF`		4	NACK received flag
`I2C_ISR_STOPF`		5	STOP detection flag
`I2C_ISR_TC`		6	Transfer complete (master mode)
`I2C_ISR_TCR`		7	Transfer complete reload
`I2C_ISR_BERR`		8	Bus error
`I2C_ISR_ARLO`		9	Arbitration lost
`I2C_ISR_OVR`		10	Overrun/Underrun
`I2C_ISR_PECERR`		11	PEC error in reception
`I2C_ISR_TIMEOUT`		12	Timeout or Tlow detection flag
`I2C_ISR_ALERT`		13	SMBus alert
`I2C_ISR_BUSY`		15	Bus busy
`I2C_ISR_DIR`		16	Transfer direction (slave mode)
`I2C_ISR_ADDCODE`		17:23	Address match code (slave mode)
`ICR`	`0x1C`	32	I2C Interrupt clear register
`I2C_ICR_ADDRCF`		3	Address matched clear flag
`I2C_ICR_NACKCF`		4	NACK clear flag
`I2C_ICR_STOPCF`		5	STOP detection clear flag
`I2C_ICR_BERRCF`		8	Bus error clear flag
`I2C_ICR_ARLOCF`		9	Arbitration lost clear flag
`I2C_ICR_OVRCF`		10	Overrun/Underrun clear flag
`I2C_ICR_PECCF`		11	PAC error clear flag
`I2C_ICR_TIMOUTCF`		12	Timeout clear flag
`I2C_ICR_ALERTCF`		13	Alert clear flag
`PECR`	`0x20`	32	I2C PEC register
`I2C_PECR_PEC`		0:7	PEC register
`RXDR`	`0x24`	32	I2C Receive data register
`I2C_RXDR_RXDATA`		0:7	8-bit receive data
`TXDR`	`0x28`	32	I2C Transmit data register
`I2C_TXDR_TXDATA`		0:7	8-bit transmit data

SPI — SPI / I²S (раздел 18)

Регистр	Смещение	Бит	Назначение
`CR1`	`0x00`	32	SPI Control register 1
`SPI_CR1_CPHA`		0	Clock Phase
`SPI_CR1_CPOL`		1	Clock Polarity
`SPI_CR1_MSTR`		2	Master Selection
`SPI_CR1_BR`		3:5	BR[2:0] bits (Baud Rate Control)
`SPI_CR1_SPE`		6	SPI Enable
`SPI_CR1_LSBFIRST`		7	Frame Format
`SPI_CR1_SSI`		8	Internal slave select
`SPI_CR1_SSM`		9	Software slave management
`SPI_CR1_RXONLY`		10	Receive only
`SPI_CR1_CRCL`		11	CRC Length
`SPI_CR1_CRCNEXT`		12	Transmit CRC next
`SPI_CR1_CRCEN`		13	Hardware CRC calculation enable
`SPI_CR1_BIDIOE`		14	Output enable in bidirectional mode
`SPI_CR1_BIDIMODE`		15	Bidirectional data mode enable
`CR2`	`0x04`	32	SPI Control register 2
`SPI_CR2_RXDMAEN`		0	Rx Buffer DMA Enable
`SPI_CR2_TXDMAEN`		1	Tx Buffer DMA Enable
`SPI_CR2_SSOE`		2	SS Output Enable
`SPI_CR2_NSSP`		3	NSS pulse management Enable
`SPI_CR2_FRF`		4	Frame Format Enable
`SPI_CR2_ERRIE`		5	Error Interrupt Enable
`SPI_CR2_RXNEIE`		6	RX buffer Not Empty Interrupt Enable
`SPI_CR2_TXEIE`		7	Tx buffer Empty Interrupt Enable
`SPI_CR2_DS`		8:11	DS[3:0] Data Size
`SPI_CR2_FRXTH`		12	FIFO reception Threshold
`SPI_CR2_LDMARX`		13	Last DMA transfer for reception
`SPI_CR2_LDMATX`		14	Last DMA transfer for transmission
`SR`	`0x08`	32	SPI Status register
`SPI_SR_RXNE`		0	Receive buffer Not Empty
`SPI_SR_TXE`		1	Transmit buffer Empty
`SPI_SR_CHSIDE`		2	Channel side
`SPI_SR_UDR`		3	Underrun flag
`SPI_SR_CRCERR`		4	CRC Error flag
`SPI_SR_MODF`		5	Mode fault
`SPI_SR_OVR`		6	Overrun flag
`SPI_SR_BSY`		7	Busy flag
`SPI_SR_FRE`		8	TI frame format error
`SPI_SR_FRLVL`		9:10	FIFO Reception Level
`SPI_SR_FTLVL`		11:12	FIFO Transmission Level
`DR`	`0x0C`	32	SPI data register
`SPI_DR_DR`		0:15	Data Register
`CRCPR`	`0x10`	32	SPI CRC polynomial register
`SPI_CRCPR_CRCPOLY`		0:15	CRC polynomial register
`RXCRCR`	`0x14`	32	SPI Rx CRC register
`SPI_RXCRCR_RXCRC`		0:15	Rx CRC Register
`TXCRCR`	`0x18`	32	SPI Tx CRC register
`SPI_TXCRCR_TXCRC`		0:15	Tx CRC Register
`I2SCFGR`	`0x1C`	32	SPI_I2S configuration register
`SPI_I2SCFGR_CHLEN`		0	Channel length (number of bits per audio channel)
`SPI_I2SCFGR_DATLEN`		1:2	DATLEN[1:0] bits (Data length to be transferred)
`SPI_I2SCFGR_CKPOL`		3	steady state clock polarity
`SPI_I2SCFGR_I2SSTD`		4:5	I2SSTD[1:0] bits (I2S standard selection)
`SPI_I2SCFGR_PCMSYNC`		7	PCM frame synchronization
`SPI_I2SCFGR_I2SCFG`		8:9	I2SCFG[1:0] bits (I2S configuration mode)
`SPI_I2SCFGR_I2SE`		10	I2S Enable
`SPI_I2SCFGR_I2SMOD`		11	I2S mode selection
`I2SPR`	`0x20`	32	SPI_I2S prescaler register
`SPI_I2SPR_I2SDIV`		0:7	I2S Linear prescaler
`SPI_I2SPR_ODD`		8	Odd factor for the prescaler
`SPI_I2SPR_MCKOE`		9	Master Clock Output Enable

CAN — CAN (раздел 19)

Регистр	Смещение	Бит	Назначение
`MCR`	`0x00`	32	CAN master control register
`CAN_MCR_INRQ`		0	Initialization Request
`CAN_MCR_SLEEP`		1	Sleep Mode Request
`CAN_MCR_TXFP`		2	Transmit FIFO Priority
`CAN_MCR_RFLM`		3	Receive FIFO Locked Mode
`CAN_MCR_NART`		4	No Automatic Retransmission
`CAN_MCR_AWUM`		5	Automatic Wakeup Mode
`CAN_MCR_ABOM`		6	Automatic Bus-Off Management
`CAN_MCR_TTCM`		7	Time Triggered Communication Mode
`CAN_MCR_RESET`		15	bxCAN software master reset
`MSR`	`0x04`	32	CAN master status register
`CAN_MSR_INAK`		0	Initialization Acknowledge
`CAN_MSR_SLAK`		1	Sleep Acknowledge
`CAN_MSR_ERRI`		2	Error Interrupt
`CAN_MSR_WKUI`		3	Wakeup Interrupt
`CAN_MSR_SLAKI`		4	Sleep Acknowledge Interrupt
`CAN_MSR_TXM`		8	Transmit Mode
`CAN_MSR_RXM`		9	Receive Mode
`CAN_MSR_SAMP`		10	Last Sample Point
`CAN_MSR_RX`		11	CAN Rx Signal
`TSR`	`0x08`	32	CAN transmit status register
`CAN_TSR_RQCP0`		0	Request Completed Mailbox0
`CAN_TSR_TXOK0`		1	Transmission OK of Mailbox0
`CAN_TSR_ALST0`		2	Arbitration Lost for Mailbox0
`CAN_TSR_TERR0`		3	Transmission Error of Mailbox0
`CAN_TSR_ABRQ0`		7	Abort Request for Mailbox0
`CAN_TSR_RQCP1`		8	Request Completed Mailbox1
`CAN_TSR_TXOK1`		9	Transmission OK of Mailbox1
`CAN_TSR_ALST1`		10	Arbitration Lost for Mailbox1
`CAN_TSR_TERR1`		11	Transmission Error of Mailbox1
`CAN_TSR_ABRQ1`		15	Abort Request for Mailbox 1
`CAN_TSR_RQCP2`		16	Request Completed Mailbox2
`CAN_TSR_TXOK2`		17	Transmission OK of Mailbox 2
`CAN_TSR_ALST2`		18	Arbitration Lost for mailbox 2
`CAN_TSR_TERR2`		19	Transmission Error of Mailbox 2
`CAN_TSR_ABRQ2`		23	Abort Request for Mailbox 2
`CAN_TSR_CODE`		24:25	Mailbox Code
`CAN_TSR_TME`		26:28	TME[2:0] bits
`CAN_TSR_TME0`		26	Transmit Mailbox 0 Empty
`CAN_TSR_TME1`		27	Transmit Mailbox 1 Empty
`CAN_TSR_TME2`		28	Transmit Mailbox 2 Empty
`CAN_TSR_LOW`		29:31	LOW[2:0] bits
`CAN_TSR_LOW0`		29	Lowest Priority Flag for Mailbox 0
`CAN_TSR_LOW1`		30	Lowest Priority Flag for Mailbox 1
`CAN_TSR_LOW2`		31	Lowest Priority Flag for Mailbox 2
`RF0R`	`0x0C`	32	CAN receive FIFO 0 register
`CAN_RF0R_FMP0`		0:1	FIFO 0 Message Pending
`CAN_RF0R_FULL0`		3	FIFO 0 Full
`CAN_RF0R_FOVR0`		4	FIFO 0 Overrun
`CAN_RF0R_RFOM0`		5	Release FIFO 0 Output Mailbox
`RF1R`	`0x10`	32	CAN receive FIFO 1 register
`CAN_RF1R_FMP1`		0:1	FIFO 1 Message Pending
`CAN_RF1R_FULL1`		3	FIFO 1 Full
`CAN_RF1R_FOVR1`		4	FIFO 1 Overrun
`CAN_RF1R_RFOM1`		5	Release FIFO 1 Output Mailbox
`IER`	`0x14`	32	CAN interrupt enable register
`CAN_IER_TMEIE`		0	Transmit Mailbox Empty Interrupt Enable
`CAN_IER_FMPIE0`		1	FIFO Message Pending Interrupt Enable
`CAN_IER_FFIE0`		2	FIFO Full Interrupt Enable
`CAN_IER_FOVIE0`		3	FIFO Overrun Interrupt Enable
`CAN_IER_FMPIE1`		4	FIFO Message Pending Interrupt Enable
`CAN_IER_FFIE1`		5	FIFO Full Interrupt Enable
`CAN_IER_FOVIE1`		6	FIFO Overrun Interrupt Enable
`CAN_IER_EWGIE`		8	Error Warning Interrupt Enable
`CAN_IER_EPVIE`		9	Error Passive Interrupt Enable
`CAN_IER_BOFIE`		10	Bus-Off Interrupt Enable
`CAN_IER_LECIE`		11	Last Error Code Interrupt Enable
`CAN_IER_ERRIE`		15	Error Interrupt Enable
`CAN_IER_WKUIE`		16	Wakeup Interrupt Enable
`CAN_IER_SLKIE`		17	Sleep Interrupt Enable
`ESR`	`0x18`	32	CAN error status register
`CAN_ESR_EWGF`		0	Error Warning Flag
`CAN_ESR_EPVF`		1	Error Passive Flag
`CAN_ESR_BOFF`		2	Bus-Off Flag
`CAN_ESR_LEC`		4:6	LEC[2:0] bits (Last Error Code)
`CAN_ESR_TEC`		16:23	Least significant byte of the 9-bit Transmit Error Counter
`CAN_ESR_REC`		24:31	Receive Error Counter
`BTR`	`0x1C`	32	CAN bit timing register
`CAN_BTR_BRP`		0:9	Baud Rate Prescaler
`CAN_BTR_TS1`		16:19	Time Segment 1
`CAN_BTR_TS2`		20:22	Time Segment 2
`CAN_BTR_SJW`		24:25	Resynchronization Jump Width
`CAN_BTR_LBKM`		30	Loop Back Mode (Debug)
`CAN_BTR_SILM`		31	Silent Mode
`FMR`	`0x200`	32	CAN filter master register
`CAN_FMR_FINIT`		0	Filter Init Mode
`FM1R`	`0x204`	32	CAN filter mode register
`CAN_FM1R_FBM`		0:13	Filter Mode
`CAN_FM1R_FBM0`		0	Filter Init Mode bit 0
`CAN_FM1R_FBM1`		1	Filter Init Mode bit 1
`CAN_FM1R_FBM2`		2	Filter Init Mode bit 2
`CAN_FM1R_FBM3`		3	Filter Init Mode bit 3
`CAN_FM1R_FBM4`		4	Filter Init Mode bit 4
`CAN_FM1R_FBM5`		5	Filter Init Mode bit 5
`CAN_FM1R_FBM6`		6	Filter Init Mode bit 6
`CAN_FM1R_FBM7`		7	Filter Init Mode bit 7
`CAN_FM1R_FBM8`		8	Filter Init Mode bit 8
`CAN_FM1R_FBM9`		9	Filter Init Mode bit 9
`CAN_FM1R_FBM10`		10	Filter Init Mode bit 10
`CAN_FM1R_FBM11`		11	Filter Init Mode bit 11
`CAN_FM1R_FBM12`		12	Filter Init Mode bit 12
`CAN_FM1R_FBM13`		13	Filter Init Mode bit 13
`FS1R`	`0x20C`	32	CAN filter scale register
`CAN_FS1R_FSC`		0:13	Filter Scale Configuration
`CAN_FS1R_FSC0`		0	Filter Scale Configuration bit 0
`CAN_FS1R_FSC1`		1	Filter Scale Configuration bit 1
`CAN_FS1R_FSC2`		2	Filter Scale Configuration bit 2
`CAN_FS1R_FSC3`		3	Filter Scale Configuration bit 3
`CAN_FS1R_FSC4`		4	Filter Scale Configuration bit 4
`CAN_FS1R_FSC5`		5	Filter Scale Configuration bit 5
`CAN_FS1R_FSC6`		6	Filter Scale Configuration bit 6
`CAN_FS1R_FSC7`		7	Filter Scale Configuration bit 7
`CAN_FS1R_FSC8`		8	Filter Scale Configuration bit 8
`CAN_FS1R_FSC9`		9	Filter Scale Configuration bit 9
`CAN_FS1R_FSC10`		10	Filter Scale Configuration bit 10
`CAN_FS1R_FSC11`		11	Filter Scale Configuration bit 11
`CAN_FS1R_FSC12`		12	Filter Scale Configuration bit 12
`CAN_FS1R_FSC13`		13	Filter Scale Configuration bit 13
`FFA1R`	`0x214`	32	CAN filter FIFO assignment register
`CAN_FFA1R_FFA`		0:13	Filter FIFO Assignment
`CAN_FFA1R_FFA0`		0	Filter FIFO Assignment for Filter 0
`CAN_FFA1R_FFA1`		1	Filter FIFO Assignment for Filter 1
`CAN_FFA1R_FFA2`		2	Filter FIFO Assignment for Filter 2
`CAN_FFA1R_FFA3`		3	Filter FIFO Assignment for Filter 3
`CAN_FFA1R_FFA4`		4	Filter FIFO Assignment for Filter 4
`CAN_FFA1R_FFA5`		5	Filter FIFO Assignment for Filter 5
`CAN_FFA1R_FFA6`		6	Filter FIFO Assignment for Filter 6
`CAN_FFA1R_FFA7`		7	Filter FIFO Assignment for Filter 7
`CAN_FFA1R_FFA8`		8	Filter FIFO Assignment for Filter 8
`CAN_FFA1R_FFA9`		9	Filter FIFO Assignment for Filter 9
`CAN_FFA1R_FFA10`		10	Filter FIFO Assignment for Filter 10
`CAN_FFA1R_FFA11`		11	Filter FIFO Assignment for Filter 11
`CAN_FFA1R_FFA12`		12	Filter FIFO Assignment for Filter 12
`CAN_FFA1R_FFA13`		13	Filter FIFO Assignment for Filter 13
`FA1R`	`0x21C`	32	CAN filter activation register
`CAN_FA1R_FACT`		0:13	Filter Active
`CAN_FA1R_FACT0`		0	Filter 0 Active
`CAN_FA1R_FACT1`		1	Filter 1 Active
`CAN_FA1R_FACT2`		2	Filter 2 Active
`CAN_FA1R_FACT3`		3	Filter 3 Active
`CAN_FA1R_FACT4`		4	Filter 4 Active
`CAN_FA1R_FACT5`		5	Filter 5 Active
`CAN_FA1R_FACT6`		6	Filter 6 Active
`CAN_FA1R_FACT7`		7	Filter 7 Active
`CAN_FA1R_FACT8`		8	Filter 8 Active
`CAN_FA1R_FACT9`		9	Filter 9 Active
`CAN_FA1R_FACT10`		10	Filter 10 Active
`CAN_FA1R_FACT11`		11	Filter 11 Active
`CAN_FA1R_FACT12`		12	Filter 12 Active
`CAN_FA1R_FACT13`		13	Filter 13 Active

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