STM32H563 · level reference · 115 min read

Appendix A8. STM32H5 register maps

The STM32H5 series: Cortex-M33 up to 250 MHz with TrustZone — the new series replacing the F4/F7. Registers and bits of the main blocks come from the STM32H563 header, made by the same generator as the F1 and F4 maps: offsets from the *_TypeDef structures, register purposes and bit descriptions from the header comments. Blocks the series lacks are left out. The handbook sections are written for the F103 and F407; register and bit names are mostly the same across series — the map helps move code over and see what is arranged differently.

How to read: the offset is from the block's base address; 31:16 is a bit field from 16 to 31; a single number is a single bit. The number in brackets in a block heading is the section where the block is covered.

STM32H563 peripherals by bus: bus bases and the appendix block offsets, as in a debugger window

RCC — Clocks (section 6)

Register	Offset	Bits	Purpose
`CR`	`0x00`	32	RCC clock control register
`RCC_CR_HSION`		0	Internal High Speed oscillator (HSI) clock enable
`RCC_CR_HSIRDY`		1	Internal High Speed oscillator (HSI) clock ready flag
`RCC_CR_HSIKERON`		2	Internal High Speed oscillator (HSI) clock enable for some IPs Kernel
`RCC_CR_HSIDIV`		3:4	Internal High Speed clock divider selection
`RCC_CR_HSIDIVF`		5	HSI Divider flag
`RCC_CR_CSION`		8	The Internal RC 4MHz oscillator (CSI) clock enable
`RCC_CR_CSIRDY`		9	The Internal RC 4MHz oscillator (CSI) clock ready
`RCC_CR_CSIKERON`		10	The Internal RC 4MHz oscillator (CSI) clock enable for some IPs Kernel
`RCC_CR_HSI48ON`		12	HSI48 clock enable
`RCC_CR_HSI48RDY`		13	HSI48 clock ready
`RCC_CR_HSEON`		16	External High Speed oscillator (HSE) clock enable
`RCC_CR_HSERDY`		17	External High Speed oscillator (HSE) clock ready
`RCC_CR_HSEBYP`		18	External High Speed oscillator (HSE) clock bypass
`RCC_CR_HSECSSON`		19	HSE Clock Security System enable
`RCC_CR_HSEEXT`		20	External High Speed clock type in Bypass mode
`RCC_CR_PLL1ON`		24	System PLL clock enable
`RCC_CR_PLL1RDY`		25	System PLL clock ready
`RCC_CR_PLL2ON`		26	PLL2 enable
`RCC_CR_PLL2RDY`		27	PLL2 ready
`RCC_CR_PLL3ON`		28	PLL3 enable
`RCC_CR_PLL3RDY`		29	PLL3 ready
`HSICFGR`	`0x10`	32	RCC HSI Clock Calibration Register
`RCC_HSICFGR_HSICAL`		0:11	HSICAL[11:0] bits
`RCC_HSICFGR_HSITRIM`		16:22	HSITRIM[6:0] bits
`CRRCR`	`0x14`	32	RCC Clock Recovery RC Register
`RCC_CRRCR_HSI48CAL`		0:9	HSI48CAL[8:0] bits
`CSICFGR`	`0x18`	32	RCC CSI Clock Calibration Register
`RCC_CSICFGR_CSICAL`		0:7	CSICAL[7:0] bits
`RCC_CSICFGR_CSITRIM`		16:21	CSITRIM[5:0] bits
`CFGR1`	`0x1C`	32	RCC clock configuration register 1
`RCC_CFGR1_SW`		0:1	SW[1:0] bits (System clock Switch)
`RCC_CFGR1_SWS`		3:4	SWS[1:0] bits (System Clock Switch Status)
`RCC_CFGR1_STOPWUCK`		6	Wake Up from stop and HSE CSS backup clock selection
`RCC_CFGR1_STOPKERWUCK`		7	Kernel Clock Selection after a Wake Up from STOP
`RCC_CFGR1_RTCPRE`		8:13	HSE division factor for RTC Clock
`CFGR2`	`0x20`	32	RCC clock configuration register 2
`RCC_CFGR2_HPRE`		0:3	HPRE[3:0] bits (AHB prescaler)
`RCC_CFGR2_PPRE1`		4:6	PPRE1[2:0] bits (APB1 prescaler)
`RCC_CFGR2_PPRE2`		8:10	PPRE2[2:0] bits (APB2 prescaler)
`RCC_CFGR2_PPRE3`		12:14	PPRE3[2:0] bits (APB3 prescaler)
`RCC_CFGR2_AHB1DIS`		16	AHB1 clock disable
`RCC_CFGR2_AHB2DIS`		17	AHB2 clock disable
`RCC_CFGR2_AHB4DIS`		19	AHB4 clock disable
`RCC_CFGR2_APB1DIS`		20	APB1 clock disable
`RCC_CFGR2_APB2DIS`		21	APB2 clock disable
`RCC_CFGR2_APB3DIS`		22	APB3 clock disable
`PLL1CFGR`	`0x28`	32	RCC PLL1 Configuration Register
`RCC_PLL1CFGR_PLL1SRC`		0:1
`RCC_PLL1CFGR_PLL1RGE`		2:3
`RCC_PLL1CFGR_PLL1FRACEN`		4
`RCC_PLL1CFGR_PLL1VCOSEL`		5
`RCC_PLL1CFGR_PLL1M`		8:13
`RCC_PLL1CFGR_PLL1PEN`		16
`RCC_PLL1CFGR_PLL1QEN`		17
`RCC_PLL1CFGR_PLL1REN`		18
`PLL2CFGR`	`0x2C`	32	RCC PLL2 Configuration Register
`RCC_PLL2CFGR_PLL2SRC`		0:1
`RCC_PLL2CFGR_PLL2RGE`		2:3
`RCC_PLL2CFGR_PLL2FRACEN`		4
`RCC_PLL2CFGR_PLL2VCOSEL`		5
`RCC_PLL2CFGR_PLL2M`		8:13
`RCC_PLL2CFGR_PLL2PEN`		16
`RCC_PLL2CFGR_PLL2QEN`		17
`RCC_PLL2CFGR_PLL2REN`		18
`PLL3CFGR`	`0x30`	32	RCC PLL3 Configuration Register
`RCC_PLL3CFGR_PLL3SRC`		0:1
`RCC_PLL3CFGR_PLL3RGE`		2:3
`RCC_PLL3CFGR_PLL3FRACEN`		4
`RCC_PLL3CFGR_PLL3VCOSEL`		5
`RCC_PLL3CFGR_PLL3M`		8:13
`RCC_PLL3CFGR_PLL3PEN`		16
`RCC_PLL3CFGR_PLL3QEN`		17
`RCC_PLL3CFGR_PLL3REN`		18
`PLL1DIVR`	`0x34`	32	RCC PLL1 Dividers Configuration Register
`RCC_PLL1DIVR_PLL1N`		0:8
`RCC_PLL1DIVR_PLL1P`		9:15
`RCC_PLL1DIVR_PLL1Q`		16:22
`RCC_PLL1DIVR_PLL1R`		24:30
`PLL1FRACR`	`0x38`	32	RCC PLL1 Fractional Divider Configuration Register
`RCC_PLL1FRACR_PLL1FRACN`		3:15
`PLL2DIVR`	`0x3C`	32	RCC PLL2 Dividers Configuration Register
`RCC_PLL2DIVR_PLL2N`		0:8
`RCC_PLL2DIVR_PLL2P`		9:15
`RCC_PLL2DIVR_PLL2Q`		16:22
`RCC_PLL2DIVR_PLL2R`		24:30
`PLL2FRACR`	`0x40`	32	RCC PLL2 Fractional Divider Configuration Register
`RCC_PLL2FRACR_PLL2FRACN`		3:15
`PLL3DIVR`	`0x44`	32	RCC PLL3 Dividers Configuration Register
`RCC_PLL3DIVR_PLL3N`		0:8
`RCC_PLL3DIVR_PLL3P`		9:15
`RCC_PLL3DIVR_PLL3Q`		16:22
`RCC_PLL3DIVR_PLL3R`		24:30
`PLL3FRACR`	`0x48`	32	RCC PLL3 Fractional Divider Configuration Register
`RCC_PLL3FRACR_PLL3FRACN`		3:15
`CIER`	`0x50`	32	RCC Clock Interrupt Enable Register
`RCC_CIER_LSIRDYIE`		0
`RCC_CIER_LSERDYIE`		1
`RCC_CIER_CSIRDYIE`		2
`RCC_CIER_HSIRDYIE`		3
`RCC_CIER_HSERDYIE`		4
`RCC_CIER_HSI48RDYIE`		5
`RCC_CIER_PLL1RDYIE`		6
`RCC_CIER_PLL2RDYIE`		7
`RCC_CIER_PLL3RDYIE`		8
`CIFR`	`0x54`	32	RCC Clock Interrupt Flag Register
`RCC_CIFR_LSIRDYF`		0
`RCC_CIFR_LSERDYF`		1
`RCC_CIFR_CSIRDYF`		2
`RCC_CIFR_HSIRDYF`		3
`RCC_CIFR_HSERDYF`		4
`RCC_CIFR_HSI48RDYF`		5
`RCC_CIFR_PLL1RDYF`		6
`RCC_CIFR_PLL2RDYF`		7
`RCC_CIFR_PLL3RDYF`		8
`RCC_CIFR_HSECSSF`		10
`CICR`	`0x58`	32	RCC Clock Interrupt Clear Register
`RCC_CICR_LSIRDYC`		0
`RCC_CICR_LSERDYC`		1
`RCC_CICR_CSIRDYC`		2
`RCC_CICR_HSIRDYC`		3
`RCC_CICR_HSERDYC`		4
`RCC_CICR_HSI48RDYC`		5
`RCC_CICR_PLL1RDYC`		6
`RCC_CICR_PLL2RDYC`		7
`RCC_CICR_PLL3RDYC`		8
`RCC_CICR_HSECSSC`		10
`AHB1RSTR`	`0x60`	32	RCC AHB1 Peripherals Reset Register
`RCC_AHB1RSTR_GPDMA1RST`		0
`RCC_AHB1RSTR_GPDMA2RST`		1
`RCC_AHB1RSTR_CRCRST`		12
`RCC_AHB1RSTR_CORDICRST`		14
`RCC_AHB1RSTR_FMACRST`		15
`RCC_AHB1RSTR_RAMCFGRST`		17
`RCC_AHB1RSTR_ETHRST`		19
`RCC_AHB1RSTR_TZSC1RST`		24
`AHB2RSTR`	`0x64`	32	RCC AHB2 Peripherals Reset Register
`RCC_AHB2RSTR_GPIOARST`		0
`RCC_AHB2RSTR_GPIOBRST`		1
`RCC_AHB2RSTR_GPIOCRST`		2
`RCC_AHB2RSTR_GPIODRST`		3
`RCC_AHB2RSTR_GPIOERST`		4
`RCC_AHB2RSTR_GPIOFRST`		5
`RCC_AHB2RSTR_GPIOGRST`		6
`RCC_AHB2RSTR_GPIOHRST`		7
`RCC_AHB2RSTR_GPIOIRST`		8
`RCC_AHB2RSTR_ADCRST`		10
`RCC_AHB2RSTR_DAC1RST`		11
`RCC_AHB2RSTR_DCMI_PSSIRST`		12
`RCC_AHB2RSTR_HASHRST`		17
`RCC_AHB2RSTR_RNGRST`		18
`RCC_AHB2RSTR_PKARST`		19
`AHB4RSTR`	`0x6C`	32	RCC AHB4 Peripherals Reset Register
`RCC_AHB4RSTR_SDMMC1RST`		11
`RCC_AHB4RSTR_SDMMC2RST`		12
`RCC_AHB4RSTR_FMCRST`		16
`RCC_AHB4RSTR_OCTOSPI1RST`		20
`APB1LRSTR`	`0x74`	32	RCC APB1 Peripherals reset Low Word register
`RCC_APB1LRSTR_TIM2RST`		0
`RCC_APB1LRSTR_TIM3RST`		1
`RCC_APB1LRSTR_TIM4RST`		2
`RCC_APB1LRSTR_TIM5RST`		3
`RCC_APB1LRSTR_TIM6RST`		4
`RCC_APB1LRSTR_TIM7RST`		5
`RCC_APB1LRSTR_TIM12RST`		6
`RCC_APB1LRSTR_TIM13RST`		7
`RCC_APB1LRSTR_TIM14RST`		8
`RCC_APB1LRSTR_SPI2RST`		14
`RCC_APB1LRSTR_SPI3RST`		15
`RCC_APB1LRSTR_USART2RST`		17
`RCC_APB1LRSTR_USART3RST`		18
`RCC_APB1LRSTR_UART4RST`		19
`RCC_APB1LRSTR_UART5RST`		20
`RCC_APB1LRSTR_I2C1RST`		21
`RCC_APB1LRSTR_I2C2RST`		22
`RCC_APB1LRSTR_I3C1RST`		23
`RCC_APB1LRSTR_CRSRST`		24
`RCC_APB1LRSTR_USART6RST`		25
`RCC_APB1LRSTR_USART10RST`		26
`RCC_APB1LRSTR_USART11RST`		27
`RCC_APB1LRSTR_CECRST`		28
`RCC_APB1LRSTR_UART7RST`		30
`RCC_APB1LRSTR_UART8RST`		31
`APB1HRSTR`	`0x78`	32	RCC APB1 Peripherals reset High Word register
`RCC_APB1HRSTR_UART9RST`		0
`RCC_APB1HRSTR_UART12RST`		1
`RCC_APB1HRSTR_DTSRST`		3
`RCC_APB1HRSTR_LPTIM2RST`		5
`RCC_APB1HRSTR_FDCANRST`		9
`RCC_APB1HRSTR_UCPD1RST`		23
`APB2RSTR`	`0x7C`	32	RCC APB2 Peripherals Reset Register
`RCC_APB2RSTR_TIM1RST`		11
`RCC_APB2RSTR_SPI1RST`		12
`RCC_APB2RSTR_TIM8RST`		13
`RCC_APB2RSTR_USART1RST`		14
`RCC_APB2RSTR_TIM15RST`		16
`RCC_APB2RSTR_TIM16RST`		17
`RCC_APB2RSTR_TIM17RST`		18
`RCC_APB2RSTR_SPI4RST`		19
`RCC_APB2RSTR_SPI6RST`		20
`RCC_APB2RSTR_SAI1RST`		21
`RCC_APB2RSTR_SAI2RST`		22
`RCC_APB2RSTR_USBRST`		24
`APB3RSTR`	`0x80`	32	RCC APB3 Peripherals Reset Register
`RCC_APB3RSTR_SPI5RST`		5
`RCC_APB3RSTR_LPUART1RST`		6
`RCC_APB3RSTR_I2C3RST`		7
`RCC_APB3RSTR_I2C4RST`		8
`RCC_APB3RSTR_LPTIM1RST`		11
`RCC_APB3RSTR_LPTIM3RST`		12
`RCC_APB3RSTR_LPTIM4RST`		13
`RCC_APB3RSTR_LPTIM5RST`		14
`RCC_APB3RSTR_LPTIM6RST`		15
`RCC_APB3RSTR_VREFRST`		20
`AHB1ENR`	`0x88`	32	RCC AHB1 Peripherals Clock Enable Register
`RCC_AHB1ENR_GPDMA1EN`		0
`RCC_AHB1ENR_GPDMA2EN`		1
`RCC_AHB1ENR_FLITFEN`		8
`RCC_AHB1ENR_CRCEN`		12
`RCC_AHB1ENR_CORDICEN`		14
`RCC_AHB1ENR_FMACEN`		15
`RCC_AHB1ENR_RAMCFGEN`		17
`RCC_AHB1ENR_ETHEN`		19
`RCC_AHB1ENR_ETHTXEN`		20
`RCC_AHB1ENR_ETHRXEN`		21
`RCC_AHB1ENR_TZSC1EN`		24
`RCC_AHB1ENR_BKPRAMEN`		28
`RCC_AHB1ENR_DCACHE1EN`		30
`RCC_AHB1ENR_SRAM1EN`		31
`AHB2ENR`	`0x8C`	32	RCC AHB2 Peripherals Clock Enable Register
`RCC_AHB2ENR_GPIOAEN`		0
`RCC_AHB2ENR_GPIOBEN`		1
`RCC_AHB2ENR_GPIOCEN`		2
`RCC_AHB2ENR_GPIODEN`		3
`RCC_AHB2ENR_GPIOEEN`		4
`RCC_AHB2ENR_GPIOFEN`		5
`RCC_AHB2ENR_GPIOGEN`		6
`RCC_AHB2ENR_GPIOHEN`		7
`RCC_AHB2ENR_GPIOIEN`		8
`RCC_AHB2ENR_ADCEN`		10
`RCC_AHB2ENR_DAC1EN`		11
`RCC_AHB2ENR_DCMI_PSSIEN`		12
`RCC_AHB2ENR_HASHEN`		17
`RCC_AHB2ENR_RNGEN`		18
`RCC_AHB2ENR_PKAEN`		19
`RCC_AHB2ENR_SRAM2EN`		30
`RCC_AHB2ENR_SRAM3EN`		31
`AHB4ENR`	`0x94`	32	RCC AHB4 Peripherals Clock Enable Register
`RCC_AHB4ENR_SDMMC2EN`		8
`RCC_AHB4ENR_SDMMC1EN`		11
`RCC_AHB4ENR_FMCEN`		16
`RCC_AHB4ENR_OCTOSPI1EN`		20
`APB1LENR`	`0x9C`	32	RCC APB1 Peripherals clock Enable Low Word register
`RCC_APB1LENR_TIM2EN`		0
`RCC_APB1LENR_TIM3EN`		1
`RCC_APB1LENR_TIM4EN`		2
`RCC_APB1LENR_TIM5EN`		3
`RCC_APB1LENR_TIM6EN`		4
`RCC_APB1LENR_TIM7EN`		5
`RCC_APB1LENR_TIM12EN`		6
`RCC_APB1LENR_TIM13EN`		7
`RCC_APB1LENR_TIM14EN`		8
`RCC_APB1LENR_WWDGEN`		11
`RCC_APB1LENR_SPI2EN`		14
`RCC_APB1LENR_SPI3EN`		15
`RCC_APB1LENR_USART2EN`		17
`RCC_APB1LENR_USART3EN`		18
`RCC_APB1LENR_UART4EN`		19
`RCC_APB1LENR_UART5EN`		20
`RCC_APB1LENR_I2C1EN`		21
`RCC_APB1LENR_I2C2EN`		22
`RCC_APB1LENR_I3C1EN`		23
`RCC_APB1LENR_CRSEN`		24
`RCC_APB1LENR_USART6EN`		25
`RCC_APB1LENR_USART10EN`		26
`RCC_APB1LENR_USART11EN`		27
`RCC_APB1LENR_CECEN`		28
`RCC_APB1LENR_UART7EN`		30
`RCC_APB1LENR_UART8EN`		31
`APB1HENR`	`0xA0`	32	RCC APB1 Peripherals clock Enable High Word register
`RCC_APB1HENR_UART9EN`		0
`RCC_APB1HENR_UART12EN`		1
`RCC_APB1HENR_DTSEN`		3
`RCC_APB1HENR_LPTIM2EN`		5
`RCC_APB1HENR_FDCANEN`		9
`RCC_APB1HENR_UCPD1EN`		23
`APB2ENR`	`0xA4`	32	RCC APB2 Peripherals Clock Enable Register
`RCC_APB2ENR_TIM1EN`		11
`RCC_APB2ENR_SPI1EN`		12
`RCC_APB2ENR_TIM8EN`		13
`RCC_APB2ENR_USART1EN`		14
`RCC_APB2ENR_TIM15EN`		16
`RCC_APB2ENR_TIM16EN`		17
`RCC_APB2ENR_TIM17EN`		18
`RCC_APB2ENR_SPI4EN`		19
`RCC_APB2ENR_SPI6EN`		20
`RCC_APB2ENR_SAI1EN`		21
`RCC_APB2ENR_SAI2EN`		22
`RCC_APB2ENR_USBEN`		24
`APB3ENR`	`0xA8`	32	RCC APB3 Peripherals Clock Enable Register
`RCC_APB3ENR_SBSEN`		1
`RCC_APB3ENR_SPI5EN`		4
`RCC_APB3ENR_LPUART1EN`		6
`RCC_APB3ENR_I2C3EN`		7
`RCC_APB3ENR_I2C4EN`		8
`RCC_APB3ENR_LPTIM1EN`		11
`RCC_APB3ENR_LPTIM3EN`		12
`RCC_APB3ENR_LPTIM4EN`		13
`RCC_APB3ENR_LPTIM5EN`		14
`RCC_APB3ENR_LPTIM6EN`		15
`RCC_APB3ENR_VREFEN`		20
`RCC_APB3ENR_RTCAPBEN`		21
`AHB1LPENR`	`0xB0`	32	RCC AHB1 Peripheral sleep clock Register
`RCC_AHB1LPENR_GPDMA1LPEN`		—
`RCC_AHB1LPENR_GPDMA2LPEN`		—
`RCC_AHB1LPENR_FLITFLPEN`		8
`RCC_AHB1LPENR_CRCLPEN`		12
`RCC_AHB1LPENR_CORDICLPEN`		14
`RCC_AHB1LPENR_FMACLPEN`		15
`RCC_AHB1LPENR_RAMCFGLPEN`		17
`RCC_AHB1LPENR_ETHLPEN`		19
`RCC_AHB1LPENR_ETHTXLPEN`		20
`RCC_AHB1LPENR_ETHRXLPEN`		21
`RCC_AHB1LPENR_TZSC1LPEN`		24
`RCC_AHB1LPENR_BKPRAMLPEN`		28
`RCC_AHB1LPENR_ICACHELPEN`		29
`RCC_AHB1LPENR_DCACHE1LPEN`		30
`RCC_AHB1LPENR_SRAM1LPEN`		31
`AHB2LPENR`	`0xB4`	32	RCC AHB2 Peripheral sleep clock Register
`RCC_AHB2LPENR_GPIOALPEN`		0
`RCC_AHB2LPENR_GPIOBLPEN`		1
`RCC_AHB2LPENR_GPIOCLPEN`		2
`RCC_AHB2LPENR_GPIODLPEN`		3
`RCC_AHB2LPENR_GPIOELPEN`		4
`RCC_AHB2LPENR_GPIOFLPEN`		5
`RCC_AHB2LPENR_GPIOGLPEN`		6
`RCC_AHB2LPENR_GPIOHLPEN`		7
`RCC_AHB2LPENR_GPIOILPEN`		8
`RCC_AHB2LPENR_ADCLPEN`		10
`RCC_AHB2LPENR_DAC1LPEN`		11
`RCC_AHB2LPENR_DCMI_PSSILPEN`		12
`RCC_AHB2LPENR_HASHLPEN`		17
`RCC_AHB2LPENR_RNGLPEN`		18
`RCC_AHB2LPENR_PKALPEN`		19
`RCC_AHB2LPENR_SRAM2LPEN`		30
`RCC_AHB2LPENR_SRAM3LPEN`		31
`AHB4LPENR`	`0xBC`	32	RCC AHB4 Peripherals sleep clock Register
`RCC_AHB4LPENR_SDMMC1LPEN`		11
`RCC_AHB4LPENR_SDMMC2LPEN`		12
`RCC_AHB4LPENR_FMCLPEN`		16
`RCC_AHB4LPENR_OCTOSPI1LPEN`		20
`APB1LLPENR`	`0xC4`	32	RCC APB1 Peripherals sleep clock Low Word Register
`RCC_APB1LLPENR_TIM2LPEN`		0
`RCC_APB1LLPENR_TIM3LPEN`		1
`RCC_APB1LLPENR_TIM4LPEN`		2
`RCC_APB1LLPENR_TIM5LPEN`		3
`RCC_APB1LLPENR_TIM6LPEN`		4
`RCC_APB1LLPENR_TIM7LPEN`		5
`RCC_APB1LLPENR_TIM12LPEN`		6
`RCC_APB1LLPENR_TIM13LPEN`		7
`RCC_APB1LLPENR_TIM14LPEN`		8
`RCC_APB1LLPENR_WWDGLPEN`		11
`RCC_APB1LLPENR_SPI2LPEN`		14
`RCC_APB1LLPENR_SPI3LPEN`		15
`RCC_APB1LLPENR_USART2LPEN`		17
`RCC_APB1LLPENR_USART3LPEN`		18
`RCC_APB1LLPENR_UART4LPEN`		19
`RCC_APB1LLPENR_UART5LPEN`		20
`RCC_APB1LLPENR_I2C1LPEN`		21
`RCC_APB1LLPENR_I2C2LPEN`		22
`RCC_APB1LLPENR_I3C1LPEN`		23
`RCC_APB1LLPENR_CRSLPEN`		24
`RCC_APB1LLPENR_USART6LPEN`		25
`RCC_APB1LLPENR_USART10LPEN`		26
`RCC_APB1LLPENR_USART11LPEN`		27
`RCC_APB1LLPENR_CECLPEN`		28
`RCC_APB1LLPENR_UART7LPEN`		30
`RCC_APB1LLPENR_UART8LPEN`		31
`APB1HLPENR`	`0xC8`	32	RCC APB1 Peripherals sleep clock High Word Register
`RCC_APB1HLPENR_UART9LPEN`		0
`RCC_APB1HLPENR_UART12LPEN`		1
`RCC_APB1HLPENR_DTSLPEN`		3
`RCC_APB1HLPENR_LPTIM2LPEN`		5
`RCC_APB1HLPENR_FDCANLPEN`		9
`RCC_APB1HLPENR_UCPD1LPEN`		23
`APB2LPENR`	`0xCC`	32	RCC APB2 Peripherals sleep clock Register
`RCC_APB2LPENR_TIM1LPEN`		11
`RCC_APB2LPENR_SPI1LPEN`		12
`RCC_APB2LPENR_TIM8LPEN`		13
`RCC_APB2LPENR_USART1LPEN`		14
`RCC_APB2LPENR_TIM15LPEN`		16
`RCC_APB2LPENR_TIM16LPEN`		17
`RCC_APB2LPENR_TIM17LPEN`		18
`RCC_APB2LPENR_SPI4LPEN`		19
`RCC_APB2LPENR_SPI6LPEN`		20
`RCC_APB2LPENR_SAI1LPEN`		21
`RCC_APB2LPENR_SAI2LPEN`		22
`RCC_APB2LPENR_USBLPEN`		24
`APB3LPENR`	`0xD0`	32	RCC APB3 Peripherals Clock Low Power Enable Register
`RCC_APB3LPENR_SBSLPEN`		0
`RCC_APB3LPENR_SPI5LPEN`		4
`RCC_APB3LPENR_LPUART1LPEN`		6
`RCC_APB3LPENR_I2C3LPEN`		7
`RCC_APB3LPENR_I2C4LPEN`		8
`RCC_APB3LPENR_LPTIM1LPEN`		11
`RCC_APB3LPENR_LPTIM3LPEN`		12
`RCC_APB3LPENR_LPTIM4LPEN`		13
`RCC_APB3LPENR_LPTIM5LPEN`		14
`RCC_APB3LPENR_LPTIM6LPEN`		15
`RCC_APB3LPENR_VREFLPEN`		20
`RCC_APB3LPENR_RTCAPBLPEN`		21
`CCIPR1`	`0xD8`	32	RCC IPs Clocks Configuration Register 1
`RCC_CCIPR1_USART1SEL`		0:2
`RCC_CCIPR1_USART2SEL`		3:5
`RCC_CCIPR1_USART3SEL`		6:8
`RCC_CCIPR1_UART4SEL`		9:11
`RCC_CCIPR1_UART5SEL`		12:14
`RCC_CCIPR1_USART6SEL`		15:17
`RCC_CCIPR1_UART7SEL`		18:20
`RCC_CCIPR1_UART8SEL`		21:23
`RCC_CCIPR1_UART9SEL`		24:26
`RCC_CCIPR1_USART10SEL`		27:29
`RCC_CCIPR1_TIMICSEL`		28
`CCIPR2`	`0xDC`	32	RCC IPs Clocks Configuration Register 2
`RCC_CCIPR2_USART11SEL`		0:2
`RCC_CCIPR2_UART12SEL`		4:6
`RCC_CCIPR2_LPTIM1SEL`		8:10
`RCC_CCIPR2_LPTIM2SEL`		12:14
`RCC_CCIPR2_LPTIM3SEL`		16:18
`RCC_CCIPR2_LPTIM4SEL`		20:22
`RCC_CCIPR2_LPTIM5SEL`		24:26
`RCC_CCIPR2_LPTIM6SEL`		28:30
`CCIPR3`	`0xE0`	32	RCC IPs Clocks Configuration Register 3
`RCC_CCIPR3_SPI1SEL`		0:2
`RCC_CCIPR3_SPI2SEL`		3:5
`RCC_CCIPR3_SPI3SEL`		6:8
`RCC_CCIPR3_SPI4SEL`		9:11
`RCC_CCIPR3_SPI5SEL`		12:14
`RCC_CCIPR3_SPI6SEL`		15:17
`RCC_CCIPR3_LPUART1SEL`		24:26
`CCIPR4`	`0xE4`	32	RCC IPs Clocks Configuration Register 4
`RCC_CCIPR4_OCTOSPISEL`		0:1
`RCC_CCIPR4_SYSTICKSEL`		2:3
`RCC_CCIPR4_USBSEL`		4:5
`RCC_CCIPR4_SDMMC1SEL`		6
`RCC_CCIPR4_SDMMC2SEL`		7
`RCC_CCIPR4_I2C1SEL`		16:17
`RCC_CCIPR4_I2C2SEL`		18:19
`RCC_CCIPR4_I2C3SEL`		20:21
`RCC_CCIPR4_I2C4SEL`		22:23
`RCC_CCIPR4_I3C1SEL`		24:25
`CCIPR5`	`0xE8`	32	RCC IPs Clocks Configuration Register 5
`RCC_CCIPR5_ADCDACSEL`		0:2
`RCC_CCIPR5_DACSEL`		3
`RCC_CCIPR5_RNGSEL`		4:5
`RCC_CCIPR5_CECSEL`		6:7
`RCC_CCIPR5_FDCANSEL`		8:9
`RCC_CCIPR5_SAI1SEL`		16:18
`RCC_CCIPR5_SAI2SEL`		19:21
`RCC_CCIPR5_CKERPSEL`		30:31
`BDCR`	`0xF0`	32	RCC VSW Backup Domain & V33 Domain Control Register
`RCC_BDCR_LSEON`		0
`RCC_BDCR_LSERDY`		1
`RCC_BDCR_LSEBYP`		2
`RCC_BDCR_LSEDRV`		3:4
`RCC_BDCR_LSECSSON`		5
`RCC_BDCR_LSECSSD`		6
`RCC_BDCR_LSEEXT`		7
`RCC_BDCR_RTCSEL`		8:9
`RCC_BDCR_RTCEN`		15
`RCC_BDCR_VSWRST`		16
`RCC_BDCR_LSCOEN`		24
`RCC_BDCR_LSCOSEL`		25
`RCC_BDCR_LSION`		26
`RCC_BDCR_LSIRDY`		27
`RSR`	`0xF4`	32	RCC Reset status Register
`RCC_RSR_RMVF`		23
`RCC_RSR_PINRSTF`		26
`RCC_RSR_BORRSTF`		27
`RCC_RSR_SFTRSTF`		28
`RCC_RSR_IWDGRSTF`		29
`RCC_RSR_WWDGRSTF`		30
`RCC_RSR_LPWRRSTF`		31
`SECCFGR`	`0x110`	32	RCC Secure mode configuration register
`RCC_SECCFGR_HSISEC`		0
`RCC_SECCFGR_HSESEC`		1
`RCC_SECCFGR_CSISEC`		2
`RCC_SECCFGR_LSISEC`		3
`RCC_SECCFGR_LSESEC`		4
`RCC_SECCFGR_SYSCLKSEC`		5
`RCC_SECCFGR_PRESCSEC`		6
`RCC_SECCFGR_PLL1SEC`		7
`RCC_SECCFGR_PLL2SEC`		8
`RCC_SECCFGR_PLL3SEC`		9
`RCC_SECCFGR_HSI48SEC`		11
`RCC_SECCFGR_RMVFSEC`		12
`RCC_SECCFGR_CKPERSELSEC`		13
`PRIVCFGR`	`0x114`	32	RCC Privilege configuration register
`RCC_PRIVCFGR_SPRIV`		0
`RCC_PRIVCFGR_NSPRIV`		1

GPIO — I/O ports (section 8)

Register	Offset	Bits	Purpose
`MODER`	`0x00`	32	GPIO port mode register
`GPIO_MODER_MODE0`		0:1
`GPIO_MODER_MODE1`		2:3
`GPIO_MODER_MODE2`		4:5
`GPIO_MODER_MODE3`		6:7
`GPIO_MODER_MODE4`		8:9
`GPIO_MODER_MODE5`		10:11
`GPIO_MODER_MODE6`		12:13
`GPIO_MODER_MODE7`		14:15
`GPIO_MODER_MODE8`		16:17
`GPIO_MODER_MODE9`		18:19
`GPIO_MODER_MODE10`		20:21
`GPIO_MODER_MODE11`		22:23
`GPIO_MODER_MODE12`		24:25
`GPIO_MODER_MODE13`		26:27
`GPIO_MODER_MODE14`		28:29
`GPIO_MODER_MODE15`		30:31
`OTYPER`	`0x04`	32	GPIO port output type register
`GPIO_OTYPER_OT0`		0
`GPIO_OTYPER_OT1`		1
`GPIO_OTYPER_OT2`		2
`GPIO_OTYPER_OT3`		3
`GPIO_OTYPER_OT4`		4
`GPIO_OTYPER_OT5`		5
`GPIO_OTYPER_OT6`		6
`GPIO_OTYPER_OT7`		7
`GPIO_OTYPER_OT8`		8
`GPIO_OTYPER_OT9`		9
`GPIO_OTYPER_OT10`		10
`GPIO_OTYPER_OT11`		11
`GPIO_OTYPER_OT12`		12
`GPIO_OTYPER_OT13`		13
`GPIO_OTYPER_OT14`		14
`GPIO_OTYPER_OT15`		15
`OSPEEDR`	`0x08`	32	GPIO port output speed register
`GPIO_OSPEEDR_OSPEED0`		0:1
`GPIO_OSPEEDR_OSPEED1`		2:3
`GPIO_OSPEEDR_OSPEED2`		4:5
`GPIO_OSPEEDR_OSPEED3`		6:7
`GPIO_OSPEEDR_OSPEED4`		8:9
`GPIO_OSPEEDR_OSPEED5`		10:11
`GPIO_OSPEEDR_OSPEED6`		12:13
`GPIO_OSPEEDR_OSPEED7`		14:15
`GPIO_OSPEEDR_OSPEED8`		16:17
`GPIO_OSPEEDR_OSPEED9`		18:19
`GPIO_OSPEEDR_OSPEED10`		20:21
`GPIO_OSPEEDR_OSPEED11`		22:23
`GPIO_OSPEEDR_OSPEED12`		24:25
`GPIO_OSPEEDR_OSPEED13`		26:27
`GPIO_OSPEEDR_OSPEED14`		28:29
`GPIO_OSPEEDR_OSPEED15`		30:31
`PUPDR`	`0x0C`	32	GPIO port pull-up/pull-down register
`GPIO_PUPDR_PUPD0`		0:1
`GPIO_PUPDR_PUPD1`		2:3
`GPIO_PUPDR_PUPD2`		4:5
`GPIO_PUPDR_PUPD3`		6:7
`GPIO_PUPDR_PUPD4`		8:9
`GPIO_PUPDR_PUPD5`		10:11
`GPIO_PUPDR_PUPD6`		12:13
`GPIO_PUPDR_PUPD7`		14:15
`GPIO_PUPDR_PUPD8`		16:17
`GPIO_PUPDR_PUPD9`		18:19
`GPIO_PUPDR_PUPD10`		20:21
`GPIO_PUPDR_PUPD11`		22:23
`GPIO_PUPDR_PUPD12`		24:25
`GPIO_PUPDR_PUPD13`		26:27
`GPIO_PUPDR_PUPD14`		28:29
`GPIO_PUPDR_PUPD15`		30:31
`IDR`	`0x10`	32	GPIO port input data register
`GPIO_IDR_ID0`		0
`GPIO_IDR_ID1`		1
`GPIO_IDR_ID2`		2
`GPIO_IDR_ID3`		3
`GPIO_IDR_ID4`		4
`GPIO_IDR_ID5`		5
`GPIO_IDR_ID6`		6
`GPIO_IDR_ID7`		7
`GPIO_IDR_ID8`		8
`GPIO_IDR_ID9`		9
`GPIO_IDR_ID10`		10
`GPIO_IDR_ID11`		11
`GPIO_IDR_ID12`		12
`GPIO_IDR_ID13`		13
`GPIO_IDR_ID14`		14
`GPIO_IDR_ID15`		15
`ODR`	`0x14`	32	GPIO port output data register
`GPIO_ODR_OD0`		0
`GPIO_ODR_OD1`		1
`GPIO_ODR_OD2`		2
`GPIO_ODR_OD3`		3
`GPIO_ODR_OD4`		4
`GPIO_ODR_OD5`		5
`GPIO_ODR_OD6`		6
`GPIO_ODR_OD7`		7
`GPIO_ODR_OD8`		8
`GPIO_ODR_OD9`		9
`GPIO_ODR_OD10`		10
`GPIO_ODR_OD11`		11
`GPIO_ODR_OD12`		12
`GPIO_ODR_OD13`		13
`GPIO_ODR_OD14`		14
`GPIO_ODR_OD15`		15
`BSRR`	`0x18`	32	GPIO port bit set/reset register
`GPIO_BSRR_BS0`		0
`GPIO_BSRR_BS1`		1
`GPIO_BSRR_BS2`		2
`GPIO_BSRR_BS3`		3
`GPIO_BSRR_BS4`		4
`GPIO_BSRR_BS5`		5
`GPIO_BSRR_BS6`		6
`GPIO_BSRR_BS7`		7
`GPIO_BSRR_BS8`		8
`GPIO_BSRR_BS9`		9
`GPIO_BSRR_BS10`		10
`GPIO_BSRR_BS11`		11
`GPIO_BSRR_BS12`		12
`GPIO_BSRR_BS13`		13
`GPIO_BSRR_BS14`		14
`GPIO_BSRR_BS15`		15
`GPIO_BSRR_BR0`		16
`GPIO_BSRR_BR1`		17
`GPIO_BSRR_BR2`		18
`GPIO_BSRR_BR3`		19
`GPIO_BSRR_BR4`		20
`GPIO_BSRR_BR5`		21
`GPIO_BSRR_BR6`		22
`GPIO_BSRR_BR7`		23
`GPIO_BSRR_BR8`		24
`GPIO_BSRR_BR9`		25
`GPIO_BSRR_BR10`		26
`GPIO_BSRR_BR11`		27
`GPIO_BSRR_BR12`		28
`GPIO_BSRR_BR13`		29
`GPIO_BSRR_BR14`		30
`GPIO_BSRR_BR15`		31
`LCKR`	`0x1C`	32	GPIO port configuration lock register
`GPIO_LCKR_LCK0`		0
`GPIO_LCKR_LCK1`		1
`GPIO_LCKR_LCK2`		2
`GPIO_LCKR_LCK3`		3
`GPIO_LCKR_LCK4`		4
`GPIO_LCKR_LCK5`		5
`GPIO_LCKR_LCK6`		6
`GPIO_LCKR_LCK7`		7
`GPIO_LCKR_LCK8`		8
`GPIO_LCKR_LCK9`		9
`GPIO_LCKR_LCK10`		10
`GPIO_LCKR_LCK11`		11
`GPIO_LCKR_LCK12`		12
`GPIO_LCKR_LCK13`		13
`GPIO_LCKR_LCK14`		14
`GPIO_LCKR_LCK15`		15
`GPIO_LCKR_LCKK`		16
`AFR`+2×4	`0x20`	32	GPIO alternate function registers
`BRR`	`0x28`	32	GPIO Bit Reset register
`GPIO_BRR_BR0`		0
`GPIO_BRR_BR1`		1
`GPIO_BRR_BR2`		2
`GPIO_BRR_BR3`		3
`GPIO_BRR_BR4`		4
`GPIO_BRR_BR5`		5
`GPIO_BRR_BR6`		6
`GPIO_BRR_BR7`		7
`GPIO_BRR_BR8`		8
`GPIO_BRR_BR9`		9
`GPIO_BRR_BR10`		10
`GPIO_BRR_BR11`		11
`GPIO_BRR_BR12`		12
`GPIO_BRR_BR13`		13
`GPIO_BRR_BR14`		14
`GPIO_BRR_BR15`		15
`HSLVR`	`0x2C`	32	GPIO high-speed low voltage register
`GPIO_HSLVR_HSLV0`		0
`GPIO_HSLVR_HSLV1`		1
`GPIO_HSLVR_HSLV2`		2
`GPIO_HSLVR_HSLV3`		3
`GPIO_HSLVR_HSLV4`		4
`GPIO_HSLVR_HSLV5`		5
`GPIO_HSLVR_HSLV6`		6
`GPIO_HSLVR_HSLV7`		7
`GPIO_HSLVR_HSLV8`		8
`GPIO_HSLVR_HSLV9`		9
`GPIO_HSLVR_HSLV10`		10
`GPIO_HSLVR_HSLV12`		12
`GPIO_HSLVR_HSLV13`		13
`GPIO_HSLVR_HSLV14`		14
`GPIO_HSLVR_HSLV15`		15
`SECCFGR`	`0x30`	32	GPIO secure configuration register
`GPIO_SECCFGR_SEC0`		0
`GPIO_SECCFGR_SEC1`		1
`GPIO_SECCFGR_SEC2`		2
`GPIO_SECCFGR_SEC3`		3
`GPIO_SECCFGR_SEC4`		4
`GPIO_SECCFGR_SEC5`		5
`GPIO_SECCFGR_SEC6`		6
`GPIO_SECCFGR_SEC7`		7
`GPIO_SECCFGR_SEC8`		8
`GPIO_SECCFGR_SEC9`		9
`GPIO_SECCFGR_SEC10`		10
`GPIO_SECCFGR_SEC12`		12
`GPIO_SECCFGR_SEC13`		13
`GPIO_SECCFGR_SEC14`		14
`GPIO_SECCFGR_SEC15`		15

EXTI — External interrupts (section 7)

Register	Offset	Bits	Purpose
`RTSR1`	`0x00`	32	EXTI Rising Trigger Selection Register 1
`EXTI_RTSR1_RT0`		0	Rising trigger configuration for input line 0
`EXTI_RTSR1_RT1`		1	Rising trigger configuration for input line 1
`EXTI_RTSR1_RT2`		2	Rising trigger configuration for input line 2
`EXTI_RTSR1_RT3`		3	Rising trigger configuration for input line 3
`EXTI_RTSR1_RT4`		4	Rising trigger configuration for input line 4
`EXTI_RTSR1_RT5`		5	Rising trigger configuration for input line 5
`EXTI_RTSR1_RT6`		6	Rising trigger configuration for input line 6
`EXTI_RTSR1_RT7`		7	Rising trigger configuration for input line 7
`EXTI_RTSR1_RT8`		8	Rising trigger configuration for input line 8
`EXTI_RTSR1_RT9`		9	Rising trigger configuration for input line 9
`EXTI_RTSR1_RT10`		10	Rising trigger configuration for input line 10
`EXTI_RTSR1_RT11`		11	Rising trigger configuration for input line 11
`EXTI_RTSR1_RT12`		12	Rising trigger configuration for input line 12
`EXTI_RTSR1_RT13`		13	Rising trigger configuration for input line 13
`EXTI_RTSR1_RT14`		14	Rising trigger configuration for input line 14
`EXTI_RTSR1_RT15`		15	Rising trigger configuration for input line 15
`EXTI_RTSR1_RT16`		16	Rising trigger configuration for input line 16
`FTSR1`	`0x04`	32	EXTI Falling Trigger Selection Register 1
`EXTI_FTSR1_FT0`		0	Falling trigger configuration for input line 0
`EXTI_FTSR1_FT1`		1	Falling trigger configuration for input line 1
`EXTI_FTSR1_FT2`		2	Falling trigger configuration for input line 2
`EXTI_FTSR1_FT3`		3	Falling trigger configuration for input line 3
`EXTI_FTSR1_FT4`		4	Falling trigger configuration for input line 4
`EXTI_FTSR1_FT5`		5	Falling trigger configuration for input line 5
`EXTI_FTSR1_FT6`		6	Falling trigger configuration for input line 6
`EXTI_FTSR1_FT7`		7	Falling trigger configuration for input line 7
`EXTI_FTSR1_FT8`		8	Falling trigger configuration for input line 8
`EXTI_FTSR1_FT9`		9	Falling trigger configuration for input line 9
`EXTI_FTSR1_FT10`		10	Falling trigger configuration for input line 10
`EXTI_FTSR1_FT11`		11	Falling trigger configuration for input line 11
`EXTI_FTSR1_FT12`		12	Falling trigger configuration for input line 12
`EXTI_FTSR1_FT13`		13	Falling trigger configuration for input line 13
`EXTI_FTSR1_FT14`		14	Falling trigger configuration for input line 14
`EXTI_FTSR1_FT15`		15	Falling trigger configuration for input line 15
`EXTI_FTSR1_FT16`		16	Falling trigger configuration for input line 16
`SWIER1`	`0x08`	32	EXTI Software Interrupt event Register 1
`EXTI_SWIER1_SWI0`		0	Software Interrupt on line 0
`EXTI_SWIER1_SWI1`		1	Software Interrupt on line 1
`EXTI_SWIER1_SWI2`		2	Software Interrupt on line 2
`EXTI_SWIER1_SWI3`		3	Software Interrupt on line 3
`EXTI_SWIER1_SWI4`		4	Software Interrupt on line 4
`EXTI_SWIER1_SWI5`		5	Software Interrupt on line 5
`EXTI_SWIER1_SWI6`		6	Software Interrupt on line 6
`EXTI_SWIER1_SWI7`		7	Software Interrupt on line 7
`EXTI_SWIER1_SWI8`		8	Software Interrupt on line 8
`EXTI_SWIER1_SWI9`		9	Software Interrupt on line 9
`EXTI_SWIER1_SWI10`		10	Software Interrupt on line 10
`EXTI_SWIER1_SWI11`		11	Software Interrupt on line 11
`EXTI_SWIER1_SWI12`		12	Software Interrupt on line 12
`EXTI_SWIER1_SWI13`		13	Software Interrupt on line 13
`EXTI_SWIER1_SWI14`		14	Software Interrupt on line 14
`EXTI_SWIER1_SWI15`		15	Software Interrupt on line 15
`EXTI_SWIER1_SWI16`		16	Software Interrupt on line 16
`RPR1`	`0x0C`	32	EXTI Rising Pending Register 1
`EXTI_RPR1_RPIF0`		0	Rising Pending Interrupt Flag on line 0
`EXTI_RPR1_RPIF1`		1	Rising Pending Interrupt Flag on line 1
`EXTI_RPR1_RPIF2`		2	Rising Pending Interrupt Flag on line 2
`EXTI_RPR1_RPIF3`		3	Rising Pending Interrupt Flag on line 3
`EXTI_RPR1_RPIF4`		4	Rising Pending Interrupt Flag on line 4
`EXTI_RPR1_RPIF5`		5	Rising Pending Interrupt Flag on line 5
`EXTI_RPR1_RPIF6`		6	Rising Pending Interrupt Flag on line 6
`EXTI_RPR1_RPIF7`		7	Rising Pending Interrupt Flag on line 7
`EXTI_RPR1_RPIF8`		8	Rising Pending Interrupt Flag on line 8
`EXTI_RPR1_RPIF9`		9	Rising Pending Interrupt Flag on line 9
`EXTI_RPR1_RPIF10`		10	Rising Pending Interrupt Flag on line 10
`EXTI_RPR1_RPIF11`		11	Rising Pending Interrupt Flag on line 11
`EXTI_RPR1_RPIF12`		12	Rising Pending Interrupt Flag on line 12
`EXTI_RPR1_RPIF13`		13	Rising Pending Interrupt Flag on line 13
`EXTI_RPR1_RPIF14`		14	Rising Pending Interrupt Flag on line 14
`EXTI_RPR1_RPIF15`		15	Rising Pending Interrupt Flag on line 15
`EXTI_RPR1_RPIF16`		16	Rising Pending Interrupt Flag on line 16
`FPR1`	`0x10`	32	EXTI Falling Pending Register 1
`EXTI_FPR1_FPIF0`		0	Falling Pending Interrupt Flag on line 0
`EXTI_FPR1_FPIF1`		1	Falling Pending Interrupt Flag on line 1
`EXTI_FPR1_FPIF2`		2	Falling Pending Interrupt Flag on line 2
`EXTI_FPR1_FPIF3`		3	Falling Pending Interrupt Flag on line 3
`EXTI_FPR1_FPIF4`		4	Falling Pending Interrupt Flag on line 4
`EXTI_FPR1_FPIF5`		5	Falling Pending Interrupt Flag on line 5
`EXTI_FPR1_FPIF6`		6	Falling Pending Interrupt Flag on line 6
`EXTI_FPR1_FPIF7`		7	Falling Pending Interrupt Flag on line 7
`EXTI_FPR1_FPIF8`		8	Falling Pending Interrupt Flag on line 8
`EXTI_FPR1_FPIF9`		9	Falling Pending Interrupt Flag on line 9
`EXTI_FPR1_FPIF10`		10	Falling Pending Interrupt Flag on line 10
`EXTI_FPR1_FPIF11`		11	Falling Pending Interrupt Flag on line 11
`EXTI_FPR1_FPIF12`		12	Falling Pending Interrupt Flag on line 12
`EXTI_FPR1_FPIF13`		13	Falling Pending Interrupt Flag on line 13
`EXTI_FPR1_FPIF14`		14	Falling Pending Interrupt Flag on line 14
`EXTI_FPR1_FPIF15`		15	Falling Pending Interrupt Flag on line 15
`EXTI_FPR1_FPIF16`		16	Falling Pending Interrupt Flag on line 16
`SECCFGR1`	`0x14`	32	EXTI Security Configuration Register 1
`PRIVCFGR1`	`0x18`	32	EXTI Privilege Configuration Register 1
`RTSR2`	`0x20`	32	EXTI Rising Trigger Selection Register 2
`EXTI_RTSR2_TR`		14:21	Rising trigger event configuration bit
`EXTI_RTSR2_TR46`		14	Rising trigger event configuration bit of line 46
`EXTI_RTSR2_TR50`		18	Rising trigger event configuration bit of line 50
`EXTI_RTSR2_TR53`		21	Rising trigger event configuration bit of line 53
`FTSR2`	`0x24`	32	EXTI Falling Trigger Selection Register 2
`EXTI_FTSR2_TR46`		14	Falling trigger event configuration bit of line 46
`EXTI_FTSR2_TR50`		18	Falling trigger event configuration bit of line 50
`EXTI_FTSR2_TR53`		21	Falling trigger event configuration bit of line 53
`SWIER2`	`0x28`	32	EXTI Software Interrupt event Register 2
`EXTI_SWIER2_SWIER46`		14	Software Interrupt on line 46
`EXTI_SWIER2_SWIER50`		18	Software Interrupt on line 50
`EXTI_SWIER2_SWIER53`		21	Software Interrupt on line 53
`RPR2`	`0x2C`	32	EXTI Rising Pending Register 2
`EXTI_RPR2_RPIF`		14:21	Rising pending edge configuration bits
`EXTI_RPR2_RPIF46`		14	Rising pending edge configuration bit of line 46
`EXTI_RPR2_RPIF50`		18	Rising pending edge configuration bit of line 50
`EXTI_RPR2_RPIF53`		21	Rising pending edge configuration bit of line 53
`FPR2`	`0x30`	32	EXTI Falling Pending Register 2
`EXTI_FPR2_FPIF`		14:21	Rising falling edge configuration bits
`EXTI_FPR2_FPIF46`		14	Rising falling edge configuration bit of line 46
`EXTI_FPR2_FPIF50`		18	Rising falling edge configuration bit of line 50
`EXTI_FPR2_FPIF53`		21	Rising falling edge configuration bit of line 53
`SECCFGR2`	`0x34`	32	EXTI Security Configuration Register 2
`PRIVCFGR2`	`0x38`	32	EXTI Privilege Configuration Register 2
`EXTICR`+4×4	`0x60`	32	EXIT External Interrupt Configuration Register, 0x60 -- 0x6C
`LOCKR`	`0x70`	32	EXTI Lock Register
`EXTI_LOCKR_LOCK`		0	Lock Mask
`IMR1`	`0x80`	32	EXTI Interrupt Mask Register 1
`EXTI_IMR1_IM`		0:31	Interrupt Mask
`EXTI_IMR1_IM0`		0	Interrupt Mask on line 0
`EXTI_IMR1_IM1`		1	Interrupt Mask on line 1
`EXTI_IMR1_IM2`		2	Interrupt Mask on line 2
`EXTI_IMR1_IM3`		3	Interrupt Mask on line 3
`EXTI_IMR1_IM4`		4	Interrupt Mask on line 4
`EXTI_IMR1_IM5`		5	Interrupt Mask on line 5
`EXTI_IMR1_IM6`		6	Interrupt Mask on line 6
`EXTI_IMR1_IM7`		7	Interrupt Mask on line 7
`EXTI_IMR1_IM8`		8	Interrupt Mask on line 8
`EXTI_IMR1_IM9`		9	Interrupt Mask on line 9
`EXTI_IMR1_IM10`		10	Interrupt Mask on line 10
`EXTI_IMR1_IM11`		11	Interrupt Mask on line 11
`EXTI_IMR1_IM12`		12	Interrupt Mask on line 12
`EXTI_IMR1_IM13`		13	Interrupt Mask on line 13
`EXTI_IMR1_IM14`		14	Interrupt Mask on line 14
`EXTI_IMR1_IM15`		15	Interrupt Mask on line 15
`EXTI_IMR1_IM16`		16	Interrupt Mask on line 16
`EXTI_IMR1_IM17`		17	Interrupt Mask on line 17
`EXTI_IMR1_IM18`		18	Interrupt Mask on line 18
`EXTI_IMR1_IM19`		19	Interrupt Mask on line 19
`EXTI_IMR1_IM20`		20	Interrupt Mask on line 20
`EXTI_IMR1_IM21`		21	Interrupt Mask on line 21
`EXTI_IMR1_IM22`		22	Interrupt Mask on line 22
`EXTI_IMR1_IM23`		23	Interrupt Mask on line 23
`EXTI_IMR1_IM24`		24	Interrupt Mask on line 24
`EXTI_IMR1_IM25`		25	Interrupt Mask on line 25
`EXTI_IMR1_IM26`		26	Interrupt Mask on line 26
`EXTI_IMR1_IM27`		27	Interrupt Mask on line 27
`EXTI_IMR1_IM28`		28	Interrupt Mask on line 28
`EXTI_IMR1_IM29`		29	Interrupt Mask on line 29
`EXTI_IMR1_IM30`		30	Interrupt Mask on line 30
`EXTI_IMR1_IM31`		31	Interrupt Mask on line 31
`EMR1`	`0x84`	32	EXTI Event Mask Register 1
`EXTI_EMR1_EM`		0:31	Event Mask
`EXTI_EMR1_EM0`		0	Event Mask on line 0
`EXTI_EMR1_EM1`		1	Event Mask on line 1
`EXTI_EMR1_EM2`		2	Event Mask on line 2
`EXTI_EMR1_EM3`		3	Event Mask on line 3
`EXTI_EMR1_EM4`		4	Event Mask on line 4
`EXTI_EMR1_EM5`		5	Event Mask on line 5
`EXTI_EMR1_EM6`		6	Event Mask on line 6
`EXTI_EMR1_EM7`		7	Event Mask on line 7
`EXTI_EMR1_EM8`		8	Event Mask on line 8
`EXTI_EMR1_EM9`		9	Event Mask on line 9
`EXTI_EMR1_EM10`		10	Event Mask on line 10
`EXTI_EMR1_EM11`		11	Event Mask on line 11
`EXTI_EMR1_EM12`		12	Event Mask on line 12
`EXTI_EMR1_EM13`		13	Event Mask on line 13
`EXTI_EMR1_EM14`		14	Event Mask on line 14
`EXTI_EMR1_EM15`		15	Event Mask on line 15
`EXTI_EMR1_EM16`		16	Event Mask on line 16
`EXTI_EMR1_EM17`		17	Event Mask on line 17
`EXTI_EMR1_EM18`		18	Event Mask on line 18
`EXTI_EMR1_EM19`		19	Event Mask on line 19
`EXTI_EMR1_EM20`		20	Event Mask on line 20
`EXTI_EMR1_EM21`		21	Event Mask on line 21
`EXTI_EMR1_EM22`		22	Event Mask on line 22
`EXTI_EMR1_EM23`		23	Event Mask on line 23
`EXTI_EMR1_EM24`		24	Event Mask on line 24
`EXTI_EMR1_EM25`		25	Event Mask on line 25
`EXTI_EMR1_EM26`		26	Event Mask on line 26
`EXTI_EMR1_EM27`		27	Event Mask on line 27
`EXTI_EMR1_EM28`		28	Event Mask on line 28
`EXTI_EMR1_EM29`		29	Event Mask on line 29
`EXTI_EMR1_EM30`		30	Event Mask on line 30
`EXTI_EMR1_EM31`		31	Event Mask on line 31
`IMR2`	`0x90`	32	EXTI Interrupt Mask Register 2
`EXTI_IMR2_IM`		0:25	Interrupt Mask
`EXTI_IMR2_IM32`		0	Interrupt Mask on line 32
`EXTI_IMR2_IM33`		1	Interrupt Mask on line 33
`EXTI_IMR2_IM34`		2	Interrupt Mask on line 34
`EXTI_IMR2_IM35`		3	Interrupt Mask on line 35
`EXTI_IMR2_IM36`		4	Interrupt Mask on line 36
`EXTI_IMR2_IM37`		5	Interrupt Mask on line 37
`EXTI_IMR2_IM38`		6	Interrupt Mask on line 38
`EXTI_IMR2_IM39`		7	Interrupt Mask on line 39
`EXTI_IMR2_IM40`		8	Interrupt Mask on line 40
`EXTI_IMR2_IM41`		9	Interrupt Mask on line 41
`EXTI_IMR2_IM42`		10	Interrupt Mask on line 42
`EXTI_IMR2_IM43`		11	Interrupt Mask on line 43
`EXTI_IMR2_IM44`		12	Interrupt Mask on line 44
`EXTI_IMR2_IM45`		13	Interrupt Mask on line 45
`EXTI_IMR2_IM46`		14	Interrupt Mask on line 46
`EXTI_IMR2_IM47`		15	Interrupt Mask on line 47
`EXTI_IMR2_IM48`		16	Interrupt Mask on line 48
`EXTI_IMR2_IM49`		17	Interrupt Mask on line 49
`EXTI_IMR2_IM50`		18	Interrupt Mask on line 50
`EXTI_IMR2_IM51`		19	Interrupt Mask on line 51
`EXTI_IMR2_IM52`		20	Interrupt Mask on line 52
`EXTI_IMR2_IM53`		21	Interrupt Mask on line 53
`EXTI_IMR2_IM54`		22	Interrupt Mask on line 54
`EXTI_IMR2_IM55`		23	Interrupt Mask on line 55
`EXTI_IMR2_IM56`		24	Interrupt Mask on line 56
`EXTI_IMR2_IM57`		25	Interrupt Mask on line 57
`EMR2`	`0x94`	32	EXTI Event Mask Register 2
`EXTI_EMR2_EM`		0:25	Event Mask
`EXTI_EMR2_EM32`		0	Event Mask on line 32
`EXTI_EMR2_EM33`		1	Event Mask on line 33
`EXTI_EMR2_EM34`		2	Event Mask on line 34
`EXTI_EMR2_EM35`		3	Event Mask on line 35
`EXTI_EMR2_EM36`		4	Event Mask on line 36
`EXTI_EMR2_EM37`		5	Event Mask on line 37
`EXTI_EMR2_EM38`		6	Event Mask on line 38
`EXTI_EMR2_EM39`		7	Event Mask on line 39
`EXTI_EMR2_EM40`		8	Event Mask on line 40
`EXTI_EMR2_EM41`		9	Event Mask on line 41
`EXTI_EMR2_EM42`		10	Event Mask on line 42
`EXTI_EMR2_EM43`		11	Event Mask on line 43
`EXTI_EMR2_EM44`		12	Event Mask on line 44
`EXTI_EMR2_EM45`		13	Event Mask on line 45
`EXTI_EMR2_EM46`		14	Event Mask on line 46
`EXTI_EMR2_EM47`		15	Event Mask on line 47
`EXTI_EMR2_EM48`		16	Event Mask on line 48
`EXTI_EMR2_EM49`		17	Event Mask on line 49
`EXTI_EMR2_EM50`		18	Event Mask on line 50
`EXTI_EMR2_EM51`		19	Event Mask on line 51
`EXTI_EMR2_EM52`		20	Event Mask on line 52
`EXTI_EMR2_EM53`		21	Event Mask on line 53
`EXTI_EMR2_EM54`		22	Event Mask on line 54
`EXTI_EMR2_EM55`		23	Event Mask on line 55
`EXTI_EMR2_EM56`		24	Event Mask on line 56
`EXTI_EMR2_EM57`		25	Event Mask on line 57

DMA — DMA channel (section 9)

Register	Offset	Bits	Purpose
`CLBAR`	`0x00`	32	DMA channel x linked-list base address register
`DMA_CLBAR_LBA`		16:31	Linked-list Base Address of DMA channel x
`CFCR`	`0x0C`	32	DMA channel x flag clear register
`DMA_CFCR_TCF`		8	Transfer complete flag clear
`DMA_CFCR_HTF`		9	Half transfer complete flag clear
`DMA_CFCR_DTEF`		10	Data transfer error flag clear
`DMA_CFCR_ULEF`		11	Update linked-list item error flag clear
`DMA_CFCR_USEF`		12	User setting error flag clear
`DMA_CFCR_SUSPF`		13	Completed suspension flag clear
`DMA_CFCR_TOF`		14	Trigger overrun flag clear
`CSR`	`0x10`	32	DMA channel x flag status register
`DMA_CSR_IDLEF`		0	Idle flag
`DMA_CSR_TCF`		8	Transfer complete flag
`DMA_CSR_HTF`		9	Half transfer complete flag
`DMA_CSR_DTEF`		10	Data transfer error flag
`DMA_CSR_ULEF`		11	Update linked-list item error flag
`DMA_CSR_USEF`		12	User setting error flag
`DMA_CSR_SUSPF`		13	User setting error flag
`DMA_CSR_TOF`		14	Trigger overrun flag
`DMA_CSR_FIFOL`		16:23	Monitored FIFO level in bytes
`CCR`	`0x14`	32	DMA channel x control register
`DMA_CCR_EN`		0	Channel enable
`DMA_CCR_RESET`		1	Channel reset
`DMA_CCR_SUSP`		2	Channel suspend
`DMA_CCR_TCIE`		8	Transfer complete interrupt enable
`DMA_CCR_HTIE`		9	Half transfer complete interrupt enable
`DMA_CCR_DTEIE`		10	Data transfer error interrupt enable
`DMA_CCR_ULEIE`		11	Update linked-list item error interrupt enable
`DMA_CCR_USEIE`		12	User setting error interrupt enable
`DMA_CCR_SUSPIE`		13	Completed suspension interrupt enable
`DMA_CCR_TOIE`		14	Trigger overrun interrupt enable
`DMA_CCR_LSM`		16	Link step mode
`DMA_CCR_LAP`		17	Linked-list allocated port
`DMA_CCR_PRIO`		22:23	Priority level
`CTR1`	`0x40`	32	DMA channel x transfer register 1
`DMA_CTR1_SDW_LOG2`		0:1	Binary logarithm of the source data width of a burst
`DMA_CTR1_SINC`		3	Source incrementing burst
`DMA_CTR1_SBL_1`		4:9	Source burst length minus 1
`DMA_CTR1_PAM`		11:12	Padding / alignment mode
`DMA_CTR1_SBX`		13	Source byte exchange within the unaligned half-word of each source word
`DMA_CTR1_SAP`		14	Source allocated port
`DMA_CTR1_SSEC`		15	Security attribute of the DMA transfer from the source
`DMA_CTR1_DDW_LOG2`		16:17	Binary logarithm of the destination data width of a burst
`DMA_CTR1_DINC`		19	Destination incrementing burst
`DMA_CTR1_DBL_1`		20:25	Destination burst length minus 1
`DMA_CTR1_DBX`		26	Destination byte exchange
`DMA_CTR1_DHX`		27	Destination half-word exchange
`DMA_CTR1_DAP`		30	Destination allocated port
`DMA_CTR1_DSEC`		31	Security attribute of the DMA transfer from the destination
`CTR2`	`0x44`	32	DMA channel x transfer register 2
`DMA_CTR2_REQSEL`		0:7	DMA hardware request selection
`DMA_CTR2_SWREQ`		9	Software request
`DMA_CTR2_DREQ`		10	Destination hardware request
`DMA_CTR2_BREQ`		11	Block hardware request
`DMA_CTR2_PFREQ`		12	Block hardware request
`DMA_CTR2_TRIGM`		14:15	Trigger mode
`DMA_CTR2_TRIGSEL`		16:21	Trigger event input selection
`DMA_CTR2_TRIGPOL`		24:25	Trigger event polarity
`DMA_CTR2_TCEM`		30:31	Transfer complete event mode
`CBR1`	`0x48`	32	DMA channel x block register 1
`DMA_CBR1_BNDT`		0:15	Block number of data bytes to transfer from the source
`DMA_CBR1_BRC`		16:26	Block repeat counter
`DMA_CBR1_SDEC`		28	Source address decrement
`DMA_CBR1_DDEC`		29	Destination address decrement
`DMA_CBR1_BRSDEC`		30	Block repeat source address decrement
`DMA_CBR1_BRDDEC`		31	Block repeat destination address decrement
`CSAR`	`0x4C`	32	DMA channel x source address register
`DMA_CSAR_SA`		0:31	Source Address
`CDAR`	`0x50`	32	DMA channel x destination address register
`DMA_CDAR_DA`		0:31	Destination address
`CTR3`	`0x54`	32	DMA channel x transfer register 3
`DMA_CTR3_SAO`		0:12	Source address offset increment
`DMA_CTR3_DAO`		16:28	Destination address offset increment
`CBR2`	`0x58`	32	DMA channel x block register 2
`DMA_CBR2_BRSAO`		0:15	Block repeated source address offset
`DMA_CBR2_BRDAO`		16:31	Block repeated destination address offset
`CLLR`	`0x7C`	32	DMA channel x linked-list address register
`DMA_CLLR_LA`		2:15	Pointer to the next linked-list data structure
`DMA_CLLR_ULL`		16	Update link address register from memory
`DMA_CLLR_UB2`		25	Update block register 2 from memory
`DMA_CLLR_UT3`		26	Update transfer register 3 from SRAM
`DMA_CLLR_UDA`		27	Update destination address register from SRAM
`DMA_CLLR_USA`		28	Update source address register from SRAM
`DMA_CLLR_UB1`		29	Update block register 1 from SRAM
`DMA_CLLR_UT2`		30	Update transfer register 2 from SRAM
`DMA_CLLR_UT1`		31	Update transfer register 1 from SRAM

PWR — Power and sleep modes (section 10)

Register	Offset	Bits	Purpose
`PMCR`	`0x00`	32	Power mode control register
`PMSR`	`0x04`	32	Power mode status register
`VOSCR`	`0x10`	32	Voltage scaling control register
`VOSSR`	`0x14`	32	Voltage sacling status register
`BDCR`	`0x20`	32	BacKup domain control register
`DBPCR`	`0x24`	32	DBP control register
`BDSR`	`0x28`	32	BacKup domain status register
`UCPDR`	`0x2C`	32	Usb typeC and Power Delivery Register
`SCCR`	`0x30`	32	Supply configuration control register
`VMCR`	`0x34`	32	Voltage Monitor Control Register
`USBSCR`	`0x38`	32	USB Supply Control Register
`VMSR`	`0x3C`	32	Status Register Voltage Monitoring
`WUSCR`	`0x40`	32	WakeUP status clear register
`WUSR`	`0x44`	32	WakeUP status Register
`WUCR`	`0x48`	32	WakeUP configuration register
`IORETR`	`0x50`	32	IO RETention Register
`SECCFGR`	`0x100`	32	Security configuration register
`PRIVCFGR`	`0x104`	32	Privilege configuration register

FLASH — Flash controller (section 11)

Register	Offset	Bits	Purpose
`ACR`	`0x00`	32	FLASH access control register
`FLASH_ACR_LATENCY`		0:3	Latency
`FLASH_ACR_WRHIGHFREQ`		4:5	Flash signal delay
`FLASH_ACR_PRFTEN`		8	Prefetch enable
`NSKEYR`	`0x04`	32	FLASH non-secure key register
`SECKEYR`	`0x08`	32	FLASH secure key register
`OPTKEYR`	`0x0C`	32	FLASH option key register
`NSOBKKEYR`	`0x10`	32	FLASH non-secure option bytes keys key register
`SECOBKKEYR`	`0x14`	32	FLASH secure option bytes keys key register
`OPSR`	`0x18`	32	FLASH OPSR register
`FLASH_OPSR_ADDR_OP`		0:19	Interrupted operation address
`FLASH_OPSR_DATA_OP`		21	Operation in Flash high-cycle data area interrupted
`FLASH_OPSR_BK_OP`		22	Interrupted operation bank
`FLASH_OPSR_SYSF_OP`		23	Operation in System Flash interrupted
`FLASH_OPSR_OTP_OP`		24	Operation in OTP area interrupted
`FLASH_OPSR_CODE_OP`		29:31	Flash memory operation code
`OPTCR`	`0x1C`	32	Flash Option Control Register
`FLASH_OPTCR_OPTLOCK`		0	FLASH_OPTCR lock option configuration bit
`FLASH_OPTCR_OPTSTART`		1	Option byte start change option configuration bit
`FLASH_OPTCR_SWAP_BANK`		31	Bank swapping option configuration bit
`NSSR`	`0x20`	32	FLASH non-secure status register
`SECSR`	`0x24`	32	FLASH secure status register
`NSCR`	`0x28`	32	FLASH non-secure control register
`SECCR`	`0x2C`	32	FLASH secure control register
`NSCCR`	`0x30`	32	FLASH non-secure clear control register
`SECCCR`	`0x34`	32	FLASH secure clear control register
`PRIVCFGR`	`0x3C`	32	FLASH privilege configuration register
`FLASH_PRIVCFGR_SPRIV`		0	Privilege protection for secure registers
`FLASH_PRIVCFGR_NSPRIV`		1	Privilege protection for non-secure registers
`NSOBKCFGR`	`0x40`	32	FLASH non-secure option byte key configuration register
`SECOBKCFGR`	`0x44`	32	FLASH secure option byte key configuration register
`HDPEXTR`	`0x48`	32	FLASH HDP extension register
`FLASH_HDPEXTR_HDP1_EXT`		0:6	HDP area extension in 8kB sectors in bank 1
`FLASH_HDPEXTR_HDP2_EXT`		16:22	HDP area extension in 8kB sectors in bank 2
`OPTSR_CUR`	`0x50`	32	FLASH option status current register
`OPTSR_PRG`	`0x54`	32	FLASH option status to program register
`NSEPOCHR_CUR`	`0x60`	32	FLASH non-secure epoch current register
`NSEPOCHR_PRG`	`0x64`	32	FLASH non-secure epoch to program register
`SECEPOCHR_CUR`	`0x68`	32	FLASH secure epoch current register
`SECEPOCHR_PRG`	`0x6C`	32	FLASH secure epoch to program register
`OPTSR2_CUR`	`0x70`	32	FLASH option status current register 2
`OPTSR2_PRG`	`0x74`	32	FLASH option status to program register 2
`NSBOOTR_CUR`	`0x80`	32	FLASH non-secure unique boot entry current register
`NSBOOTR_PRG`	`0x84`	32	FLASH non-secure unique boot entry to program register
`SECBOOTR_CUR`	`0x88`	32	FLASH secure unique boot entry current register
`SECBOOTR_PRG`	`0x8C`	32	FLASH secure unique boot entry to program register
`OTPBLR_CUR`	`0x90`	32	FLASH OTP block lock current register
`OTPBLR_PRG`	`0x94`	32	FLASH OTP block Lock to program register
`SECBB1R1`	`0xA0`	32	FLASH secure block-based bank 1 register 1
`SECBB1R2`	`0xA4`	32	FLASH secure block-based bank 1 register 2
`SECBB1R3`	`0xA8`	32	FLASH secure block-based bank 1 register 3
`SECBB1R4`	`0xAC`	32	FLASH secure block-based bank 1 register 4
`PRIVBB1R1`	`0xC0`	32	FLASH privilege block-based bank 1 register 1
`PRIVBB1R2`	`0xC4`	32	FLASH privilege block-based bank 1 register 2
`PRIVBB1R3`	`0xC8`	32	FLASH privilege block-based bank 1 register 3
`PRIVBB1R4`	`0xCC`	32	FLASH privilege block-based bank 1 register 4
`SECWM1R_CUR`	`0xE0`	32	FLASH secure watermark 1 current register
`SECWM1R_PRG`	`0xE4`	32	FLASH secure watermark 1 to program register
`WRP1R_CUR`	`0xE8`	32	FLASH write sector group protection current register for bank1
`WRP1R_PRG`	`0xEC`	32	FLASH write sector group protection to program register for bank1
`EDATA1R_CUR`	`0xF0`	32	FLASH data sectors configuration current register for bank1
`EDATA1R_PRG`	`0xF4`	32	FLASH data sectors configuration to program register for bank1
`HDP1R_CUR`	`0xF8`	32	FLASH HDP configuration current register for bank1
`HDP1R_PRG`	`0xFC`	32	FLASH HDP configuration to program register for bank1
`ECCCORR`	`0x100`	32	FLASH ECC correction register
`ECCDETR`	`0x104`	32	FLASH ECC detection register
`ECCDR`	`0x108`	32	FLASH ECC data register
`FLASH_ECCDR_FAIL_DATA`		0:15	ECC fail data
`SECBB2R1`	`0x1A0`	32	FLASH secure block-based bank 2 register 1
`SECBB2R2`	`0x1A4`	32	FLASH secure block-based bank 2 register 2
`SECBB2R3`	`0x1A8`	32	FLASH secure block-based bank 2 register 3
`SECBB2R4`	`0x1AC`	32	FLASH secure block-based bank 2 register 4
`PRIVBB2R1`	`0x1C0`	32	FLASH privilege block-based bank 2 register 1
`PRIVBB2R2`	`0x1C4`	32	FLASH privilege block-based bank 2 register 2
`PRIVBB2R3`	`0x1C8`	32	FLASH privilege block-based bank 2 register 3
`PRIVBB2R4`	`0x1CC`	32	FLASH privilege block-based bank 2 register 4
`SECWM2R_CUR`	`0x1E0`	32	FLASH secure watermark 2 current register
`SECWM2R_PRG`	`0x1E4`	32	FLASH secure watermark 2 to program register
`WRP2R_CUR`	`0x1E8`	32	FLASH write sector group protection current register for bank2
`WRP2R_PRG`	`0x1EC`	32	FLASH write sector group protection to program register for bank2
`EDATA2R_CUR`	`0x1F0`	32	FLASH data sectors configuration current register for bank2
`EDATA2R_PRG`	`0x1F4`	32	FLASH data sectors configuration to program register for bank2
`HDP2R_CUR`	`0x1F8`	32	FLASH HDP configuration current register for bank2
`HDP2R_PRG`	`0x1FC`	32	FLASH HDP configuration to program register for bank2

IWDG — Independent watchdog (section 12)

Register	Offset	Bits	Purpose
`KR`	`0x00`	32	IWDG Key register
`IWDG_KR_KEY`		0:15	Key value (write only, read 0000h)
`PR`	`0x04`	32	IWDG Prescaler register
`IWDG_PR_PR`		0:3	PR[3:0] (Prescaler divider)
`RLR`	`0x08`	32	IWDG Reload register
`IWDG_RLR_RL`		0:11	Watchdog counter reload value
`SR`	`0x0C`	32	IWDG Status register
`IWDG_SR_PVU`		0	Watchdog prescaler value update
`IWDG_SR_RVU`		1	Watchdog counter reload value update
`IWDG_SR_WVU`		2	Watchdog counter window value update
`IWDG_SR_EWU`		3	Watchdog interrupt comparator value update
`IWDG_SR_ONF`		8	Watchdog Enable status bit
`IWDG_SR_EWIF`		14	Watchdog early interrupt flag
`WINR`	`0x10`	32	IWDG Window register
`IWDG_WINR_WIN`		0:11	Watchdog counter window value
`EWCR`	`0x14`	32	IWDG Early Wakeup register
`IWDG_EWCR_EWIT`		0:11	Watchdog early wakeup comparator value
`IWDG_EWCR_EWIC`		0:11	Watchdog early wakeup comparator value
`IWDG_EWCR_EWIE`		0:11	Watchdog early wakeup comparator value

WWDG — Window watchdog (section 12)

Register	Offset	Bits	Purpose
`CR`	`0x00`	32	WWDG Control register
`WWDG_CR_T`		0:6	T[6:0] bits (7-Bit counter (MSB to LSB))
`WWDG_CR_WDGA`		7	Activation bit
`CFR`	`0x04`	32	WWDG Configuration register
`WWDG_CFR_W`		0:6	W[6:0] bits (7-bit window value)
`WWDG_CFR_EWI`		9	Early Wakeup Interrupt
`WWDG_CFR_WDGTB`		11:13	WDGTB[2:0] bits (Timer Base)
`SR`	`0x08`	32	WWDG Status register
`WWDG_SR_EWIF`		0	Early Wakeup Interrupt Flag

CRC — Checksum (CRC) (section 12)

Register	Offset	Bits	Purpose
`DR`	`0x00`	32	CRC Data register
`CRC_DR_DR`		0:31	Data register bits
`IDR`	`0x04`	32	CRC Independent data register
`CRC_IDR_IDR`		0:31	General-purpose 32-bits data register bits
`CR`	`0x08`	32	CRC Control register
`CRC_CR_RESET`		0	RESET the CRC computation unit bit
`CRC_CR_POLYSIZE`		3:4	Polynomial size bits
`CRC_CR_REV_IN`		5:6	REV_IN Reverse Input Data bits
`CRC_CR_REV_OUT`		7	REV_OUT Reverse Output Data bits
`INIT`	`0x10`	32	Initial CRC value register
`CRC_INIT_INIT`		0:31	Initial CRC value bits
`POL`	`0x14`	32	CRC polynomial register
`CRC_POL_POL`		0:31	Coefficients of the polynomial
`HWCFGR`	`0x3F0`	32	CRC IP HWCFGR register
`VERR`	`0x3F4`	32	CRC IP version register
`PIDR`	`0x3F8`	32	CRC IP type identification register
`SIDR`	`0x3FC`	32	CRC IP map Size ID register

RTC — Real-time clock (section 12)

Register	Offset	Bits	Purpose
`TR`	`0x00`	32	RTC time register
`RTC_TR_SU`		0:3
`RTC_TR_ST`		4:6
`RTC_TR_MNU`		8:11
`RTC_TR_MNT`		12:14
`RTC_TR_HU`		16:19
`RTC_TR_HT`		20:21
`RTC_TR_PM`		22
`DR`	`0x04`	32	RTC date register
`RTC_DR_DU`		0:3
`RTC_DR_DT`		4:5
`RTC_DR_MU`		8:11
`RTC_DR_MT`		12
`RTC_DR_WDU`		13:15
`RTC_DR_YU`		16:19
`RTC_DR_YT`		20:23
`SSR`	`0x08`	32	RTC sub second register
`RTC_SSR_SS`		0:31
`ICSR`	`0x0C`	32	RTC initialization control and status register
`RTC_ICSR_ALRAWF`		0
`RTC_ICSR_ALRBWF`		1
`RTC_ICSR_WUTWF`		2
`RTC_ICSR_SHPF`		3
`RTC_ICSR_INITS`		4
`RTC_ICSR_RSF`		5
`RTC_ICSR_INITF`		6
`RTC_ICSR_INIT`		7
`RTC_ICSR_BIN`		8:9
`RTC_ICSR_BCDU`		10:12
`RTC_ICSR_RECALPF`		16
`PRER`	`0x10`	32	RTC prescaler register
`RTC_PRER_PREDIV_S`		0:14
`RTC_PRER_PREDIV_A`		16:22
`WUTR`	`0x14`	32	RTC wakeup timer register
`RTC_WUTR_WUT`		0:15
`RTC_WUTR_WUTOCLR`		0:15
`CR`	`0x18`	32	RTC control register
`RTC_CR_WUCKSEL`		0:2
`RTC_CR_TSEDGE`		3
`RTC_CR_REFCKON`		4
`RTC_CR_BYPSHAD`		5
`RTC_CR_FMT`		6
`RTC_CR_SSRUIE`		7
`RTC_CR_ALRAE`		8
`RTC_CR_ALRBE`		9
`RTC_CR_WUTE`		10
`RTC_CR_TSE`		11
`RTC_CR_ALRAIE`		12
`RTC_CR_ALRBIE`		13
`RTC_CR_WUTIE`		14
`RTC_CR_TSIE`		15
`RTC_CR_ADD1H`		16
`RTC_CR_SUB1H`		17
`RTC_CR_BKP`		18
`RTC_CR_COSEL`		19
`RTC_CR_POL`		20
`RTC_CR_OSEL`		21:22
`RTC_CR_COE`		23
`RTC_CR_ITSE`		24	Timestamp on internal event enable
`RTC_CR_TAMPTS`		25	Activate timestamp on tamper detection event
`RTC_CR_TAMPOE`		26	Tamper detection output enable on TAMPALARM
`RTC_CR_ALRAFCLR`		27	Alarm A mask
`RTC_CR_ALRBFCLR`		28	Alarm B mask
`RTC_CR_TAMPALRM_PU`		29	TAMPALARM output pull-up config
`RTC_CR_TAMPALRM_TYPE`		30	TAMPALARM output type
`RTC_CR_OUT2EN`		31	RTC_OUT2 output enable
`PRIVCFGR`	`0x1C`	32	RTC privilege mode control register
`RTC_PRIVCFGR_ALRAPRIV`		0
`RTC_PRIVCFGR_ALRBPRIV`		1
`RTC_PRIVCFGR_WUTPRIV`		2
`RTC_PRIVCFGR_TSPRIV`		3
`RTC_PRIVCFGR_CALPRIV`		13
`RTC_PRIVCFGR_INITPRIV`		14
`RTC_PRIVCFGR_PRIV`		15
`SECCFGR`	`0x20`	32	RTC secure mode control register
`RTC_SECCFGR_ALRASEC`		0
`RTC_SECCFGR_ALRBSEC`		1
`RTC_SECCFGR_WUTSEC`		2
`RTC_SECCFGR_TSSEC`		3
`RTC_SECCFGR_CALSEC`		13
`RTC_SECCFGR_INITSEC`		14
`RTC_SECCFGR_SEC`		15
`WPR`	`0x24`	32	RTC write protection register
`RTC_WPR_KEY`		0:7
`CALR`	`0x28`	32	RTC calibration register
`RTC_CALR_CALM`		0:8
`RTC_CALR_LPCAL`		12
`RTC_CALR_CALW16`		13
`RTC_CALR_CALW8`		14
`RTC_CALR_CALP`		15
`SHIFTR`	`0x2C`	32	RTC shift control register
`RTC_SHIFTR_SUBFS`		0:14
`RTC_SHIFTR_ADD1S`		31
`TSTR`	`0x30`	32	RTC time stamp time register
`RTC_TSTR_SU`		0:3
`RTC_TSTR_ST`		4:6
`RTC_TSTR_MNU`		8:11
`RTC_TSTR_MNT`		12:14
`RTC_TSTR_HU`		16:19
`RTC_TSTR_HT`		20:21
`RTC_TSTR_PM`		22
`TSDR`	`0x34`	32	RTC time stamp date register
`RTC_TSDR_DU`		0:3
`RTC_TSDR_DT`		4:5
`RTC_TSDR_MU`		8:11
`RTC_TSDR_MT`		12
`RTC_TSDR_WDU`		13:15
`TSSSR`	`0x38`	32	RTC time-stamp sub second register
`RTC_TSSSR_SS`		0:31	rtc timestamp sub second >
`ALRMAR`	`0x40`	32	RTC alarm A register
`RTC_ALRMAR_SU`		0:3
`RTC_ALRMAR_ST`		4:6
`RTC_ALRMAR_MSK1`		7
`RTC_ALRMAR_MNU`		8:11
`RTC_ALRMAR_MNT`		12:14
`RTC_ALRMAR_MSK2`		15
`RTC_ALRMAR_HU`		16:19
`RTC_ALRMAR_HT`		20:21
`RTC_ALRMAR_PM`		22
`RTC_ALRMAR_MSK3`		23
`RTC_ALRMAR_DU`		24:27
`RTC_ALRMAR_DT`		28:29
`RTC_ALRMAR_WDSEL`		30
`RTC_ALRMAR_MSK4`		31
`ALRMASSR`	`0x44`	32	RTC alarm A sub second register
`RTC_ALRMASSR_SS`		0:14
`RTC_ALRMASSR_MASKSS`		24:29
`RTC_ALRMASSR_SSCLR`		31
`ALRMBR`	`0x48`	32	RTC alarm B register
`RTC_ALRMBR_SU`		0:3
`RTC_ALRMBR_ST`		4:6
`RTC_ALRMBR_MSK1`		7
`RTC_ALRMBR_MNU`		8:11
`RTC_ALRMBR_MNT`		12:14
`RTC_ALRMBR_MSK2`		15
`RTC_ALRMBR_HU`		16:19
`RTC_ALRMBR_HT`		20:21
`RTC_ALRMBR_PM`		22
`RTC_ALRMBR_MSK3`		23
`RTC_ALRMBR_DU`		24:27
`RTC_ALRMBR_DT`		28:29
`RTC_ALRMBR_WDSEL`		30
`RTC_ALRMBR_MSK4`		31
`ALRMBSSR`	`0x4C`	32	RTC alarm B sub second register
`RTC_ALRMBSSR_SS`		0:14
`RTC_ALRMBSSR_MASKSS`		24:29
`RTC_ALRMBSSR_SSCLR`		31
`SR`	`0x50`	32	RTC Status register
`RTC_SR_ALRAF`		0
`RTC_SR_ALRBF`		1
`RTC_SR_WUTF`		2
`RTC_SR_TSF`		3
`RTC_SR_TSOVF`		4
`RTC_SR_ITSF`		5
`RTC_SR_SSRUF`		6
`MISR`	`0x54`	32	RTC masked interrupt status register
`RTC_MISR_ALRAMF`		0
`RTC_MISR_ALRBMF`		1
`RTC_MISR_WUTMF`		2
`RTC_MISR_TSMF`		3
`RTC_MISR_TSOVMF`		4
`RTC_MISR_ITSMF`		5
`RTC_MISR_SSRUMF`		6
`SMISR`	`0x58`	32	RTC secure masked interrupt status register
`RTC_SMISR_ALRAMF`		0
`RTC_SMISR_ALRBMF`		1
`RTC_SMISR_WUTMF`		2
`RTC_SMISR_TSMF`		3
`RTC_SMISR_TSOVMF`		4
`RTC_SMISR_ITSMF`		5
`RTC_SMISR_SSRUMF`		6
`SCR`	`0x5C`	32	RTC status Clear register
`RTC_SCR_CALRAF`		0
`RTC_SCR_CALRBF`		1
`RTC_SCR_CWUTF`		2
`RTC_SCR_CTSF`		3
`RTC_SCR_CTSOVF`		4
`RTC_SCR_CITSF`		5
`RTC_SCR_CSSRUF`		6
`OR`	`0x60`	32	RTC option register
`RTC_OR_OUT2_RMP`		0
`ALRABINR`	`0x70`	32	RTC alarm A binary mode register
`RTC_ALRABINR_SS`		0:31
`ALRBBINR`	`0x74`	32	RTC alarm B binary mode register
`RTC_ALRBBINR_SS`		0:31

TAMP — Tamper detection and backup registers (section 12)

Register	Offset	Bits	Purpose
`CR1`	`0x00`	32	TAMP control register 1
`TAMP_CR1_TAMP1E`		0
`TAMP_CR1_TAMP2E`		1
`TAMP_CR1_TAMP3E`		2
`TAMP_CR1_TAMP4E`		3
`TAMP_CR1_TAMP5E`		4
`TAMP_CR1_TAMP6E`		5
`TAMP_CR1_TAMP7E`		6
`TAMP_CR1_TAMP8E`		7
`TAMP_CR1_ITAMP1E`		16
`TAMP_CR1_ITAMP2E`		17
`TAMP_CR1_ITAMP3E`		18
`TAMP_CR1_ITAMP4E`		19
`TAMP_CR1_ITAMP5E`		20
`TAMP_CR1_ITAMP6E`		21
`TAMP_CR1_ITAMP7E`		22
`TAMP_CR1_ITAMP8E`		23
`TAMP_CR1_ITAMP9E`		24
`TAMP_CR1_ITAMP11E`		26
`TAMP_CR1_ITAMP12E`		27
`TAMP_CR1_ITAMP13E`		28
`TAMP_CR1_ITAMP15E`		30
`CR2`	`0x04`	32	TAMP control register 2
`TAMP_CR2_TAMP1NOERASE`		0
`TAMP_CR2_TAMP2NOERASE`		1
`TAMP_CR2_TAMP3NOERASE`		2
`TAMP_CR2_TAMP4NOERASE`		3
`TAMP_CR2_TAMP5NOERASE`		4
`TAMP_CR2_TAMP6NOERASE`		5
`TAMP_CR2_TAMP7NOERASE`		6
`TAMP_CR2_TAMP8NOERASE`		7
`TAMP_CR2_TAMP1MSK`		16
`TAMP_CR2_TAMP2MSK`		17
`TAMP_CR2_TAMP3MSK`		18
`TAMP_CR2_BKBLOCK`		22
`TAMP_CR2_BKERASE`		23
`TAMP_CR2_TAMP1TRG`		24
`TAMP_CR2_TAMP2TRG`		25
`TAMP_CR2_TAMP3TRG`		25
`TAMP_CR2_TAMP4TRG`		25
`TAMP_CR2_TAMP5TRG`		25
`TAMP_CR2_TAMP6TRG`		25
`TAMP_CR2_TAMP7TRG`		25
`TAMP_CR2_TAMP8TRG`		25
`CR3`	`0x08`	32	TAMP control register 3
`TAMP_CR3_ITAMP1NOER`		0
`TAMP_CR3_ITAMP2NOER`		1
`TAMP_CR3_ITAMP3NOER`		2
`TAMP_CR3_ITAMP4NOER`		3
`TAMP_CR3_ITAMP5NOER`		4
`TAMP_CR3_ITAMP6NOER`		5
`TAMP_CR3_ITAMP7NOER`		6
`TAMP_CR3_ITAMP8NOER`		7
`TAMP_CR3_ITAMP9NOER`		8
`TAMP_CR3_ITAMP11NOER`		10
`TAMP_CR3_ITAMP12NOER`		11
`TAMP_CR3_ITAMP13NOER`		12
`TAMP_CR3_ITAMP15NOER`		14
`FLTCR`	`0x0C`	32	TAMP filter control register
`TAMP_FLTCR_TAMPFREQ`		0:2
`TAMP_FLTCR_TAMPFLT`		3:4
`TAMP_FLTCR_TAMPPRCH`		5:6
`TAMP_FLTCR_TAMPPUDIS`		7
`ATCR1`	`0x10`	32	TAMP filter control register 1
`TAMP_ATCR1_TAMP1AM`		0
`TAMP_ATCR1_TAMP2AM`		1
`TAMP_ATCR1_TAMP3AM`		2
`TAMP_ATCR1_TAMP4AM`		3
`TAMP_ATCR1_TAMP5AM`		4
`TAMP_ATCR1_TAMP6AM`		4
`TAMP_ATCR1_TAMP7AM`		6
`TAMP_ATCR1_TAMP8AM`		7
`TAMP_ATCR1_ATOSEL1`		8:9
`TAMP_ATCR1_ATOSEL2`		10:11
`TAMP_ATCR1_ATOSEL3`		12:13
`TAMP_ATCR1_ATOSEL4`		14:15
`TAMP_ATCR1_ATCKSEL`		16:19
`TAMP_ATCR1_ATPER`		24:26
`TAMP_ATCR1_ATOSHARE`		30
`TAMP_ATCR1_FLTEN`		31
`ATSEEDR`	`0x14`	32	TAMP active tamper seed register
`TAMP_ATSEEDR_SEED`		0:31
`ATOR`	`0x18`	32	TAMP active tamper output register
`TAMP_ATOR_PRNG`		0:7
`ATCR2`	`0x1C`	32	TAMP filter control register 2
`TAMP_ATCR2_ATOSEL1`		8:10
`TAMP_ATCR2_ATOSEL2`		11:13
`TAMP_ATCR2_ATOSEL3`		14:16
`TAMP_ATCR2_ATOSEL4`		17:19
`TAMP_ATCR2_ATOSEL5`		20:22
`TAMP_ATCR2_ATOSEL6`		23:25
`TAMP_ATCR2_ATOSEL7`		26:28
`TAMP_ATCR2_ATOSEL8`		29:31
`SECCFGR`	`0x20`	32	TAMP secure mode control register
`TAMP_SECCFGR_BKPRWSEC`		0:7
`TAMP_SECCFGR_CNT1SEC`		15
`TAMP_SECCFGR_BKPWSEC`		16:23
`TAMP_SECCFGR_BHKLOCK`		30
`TAMP_SECCFGR_TAMPSEC`		31
`PRIVCFGR`	`0x24`	32	TAMP privilege mode control register
`TAMP_PRIVCFGR_CNT1PRIV`		29
`TAMP_PRIVCFGR_BKPRWPRIV`		29
`TAMP_PRIVCFGR_BKPWPRIV`		30
`TAMP_PRIVCFGR_TAMPPRIV`		31
`IER`	`0x2C`	32	TAMP interrupt enable register
`TAMP_IER_TAMP1IE`		0
`TAMP_IER_TAMP2IE`		1
`TAMP_IER_TAMP3IE`		2
`TAMP_IER_TAMP4IE`		3
`TAMP_IER_TAMP5IE`		4
`TAMP_IER_TAMP6IE`		5
`TAMP_IER_TAMP7IE`		6
`TAMP_IER_TAMP8IE`		7
`TAMP_IER_ITAMP1IE`		16
`TAMP_IER_ITAMP2IE`		17
`TAMP_IER_ITAMP3IE`		18
`TAMP_IER_ITAMP4IE`		19
`TAMP_IER_ITAMP5IE`		20
`TAMP_IER_ITAMP6IE`		21
`TAMP_IER_ITAMP7IE`		22
`TAMP_IER_ITAMP8IE`		23
`TAMP_IER_ITAMP9IE`		24
`TAMP_IER_ITAMP11IE`		26
`TAMP_IER_ITAMP12IE`		27
`TAMP_IER_ITAMP13IE`		28
`TAMP_IER_ITAMP15IE`		30
`SR`	`0x30`	32	TAMP status register
`TAMP_SR_TAMP1F`		0
`TAMP_SR_TAMP2F`		1
`TAMP_SR_TAMP3F`		2
`TAMP_SR_TAMP4F`		3
`TAMP_SR_TAMP5F`		4
`TAMP_SR_TAMP6F`		5
`TAMP_SR_TAMP7F`		6
`TAMP_SR_TAMP8F`		7
`TAMP_SR_ITAMP1F`		16
`TAMP_SR_ITAMP2F`		17
`TAMP_SR_ITAMP3F`		18
`TAMP_SR_ITAMP4F`		19
`TAMP_SR_ITAMP5F`		20
`TAMP_SR_ITAMP6F`		21
`TAMP_SR_ITAMP7F`		22
`TAMP_SR_ITAMP8F`		23
`TAMP_SR_ITAMP9F`		24
`TAMP_SR_ITAMP11F`		26
`TAMP_SR_ITAMP12F`		27
`TAMP_SR_ITAMP13F`		28
`TAMP_SR_ITAMP15F`		30
`MISR`	`0x34`	32	TAMP masked interrupt status register
`TAMP_MISR_TAMP1MF`		0
`TAMP_MISR_TAMP2MF`		1
`TAMP_MISR_TAMP3MF`		2
`TAMP_MISR_TAMP4MF`		3
`TAMP_MISR_TAMP5MF`		4
`TAMP_MISR_TAMP6MF`		5
`TAMP_MISR_TAMP7MF`		6
`TAMP_MISR_TAMP8MF`		7
`TAMP_MISR_ITAMP1MF`		16
`TAMP_MISR_ITAMP2MF`		17
`TAMP_MISR_ITAMP3MF`		18
`TAMP_MISR_ITAMP4MF`		19
`TAMP_MISR_ITAMP5MF`		20
`TAMP_MISR_ITAMP6MF`		21
`TAMP_MISR_ITAMP7MF`		22
`TAMP_MISR_ITAMP8MF`		23
`TAMP_MISR_ITAMP9MF`		24
`TAMP_MISR_ITAMP11MF`		26
`TAMP_MISR_ITAMP12MF`		27
`TAMP_MISR_ITAMP13MF`		28
`TAMP_MISR_ITAMP15MF`		30
`SMISR`	`0x38`	32	TAMP secure masked interrupt status register
`TAMP_SMISR_TAMP1MF`		0
`TAMP_SMISR_TAMP2MF`		1
`TAMP_SMISR_TAMP3MF`		2
`TAMP_SMISR_TAMP4MF`		3
`TAMP_SMISR_TAMP5MF`		4
`TAMP_SMISR_TAMP6MF`		5
`TAMP_SMISR_TAMP7MF`		6
`TAMP_SMISR_TAMP8MF`		7
`TAMP_SMISR_ITAMP1MF`		16
`TAMP_SMISR_ITAMP2MF`		17
`TAMP_SMISR_ITAMP3MF`		18
`TAMP_SMISR_ITAMP4MF`		19
`TAMP_SMISR_ITAMP5MF`		20
`TAMP_SMISR_ITAMP9MF`		20
`TAMP_SMISR_ITAMP6MF`		21
`TAMP_SMISR_ITAMP7MF`		22
`TAMP_SMISR_ITAMP11MF`		22
`TAMP_SMISR_ITAMP8MF`		23
`TAMP_SMISR_ITAMP12MF`		27
`TAMP_SMISR_ITAMP13MF`		28
`TAMP_SMISR_ITAMP15MF`		30
`SCR`	`0x3C`	32	TAMP status clear register
`TAMP_SCR_CTAMP1F`		0
`TAMP_SCR_CTAMP2F`		1
`TAMP_SCR_CTAMP3F`		2
`TAMP_SCR_CTAMP4F`		3
`TAMP_SCR_CTAMP5F`		4
`TAMP_SCR_CTAMP6F`		5
`TAMP_SCR_CTAMP7F`		6
`TAMP_SCR_CTAMP8F`		7
`TAMP_SCR_CITAMP1F`		16
`TAMP_SCR_CITAMP2F`		17
`TAMP_SCR_CITAMP3F`		18
`TAMP_SCR_CITAMP4F`		19
`TAMP_SCR_CITAMP5F`		20
`TAMP_SCR_CITAMP9F`		20
`TAMP_SCR_CITAMP6F`		21
`TAMP_SCR_CITAMP7F`		22
`TAMP_SCR_CITAMP11F`		22
`TAMP_SCR_CITAMP8F`		23
`TAMP_SCR_CITAMP12F`		27
`TAMP_SCR_CITAMP13F`		28
`TAMP_SCR_CITAMP15F`		30
`COUNT1R`	`0x40`	32	TAMP monotonic counter register
`TAMP_COUNT1R_COUNT`		0:31
`OR`	`0x50`	32	TAMP option register
`TAMP_OR_OUT5_RMP`		0
`TAMP_OR_IN2_RMP`		0
`TAMP_OR_IN3_RMP`		0
`TAMP_OR_IN4_RMP`		0
`TAMP_OR_OUT3_RMP`		1:2
`ERCFGR`	`0x54`	32	TAMP erase configuration register
`TAMP_ERCFGR_ERCFG0`		0
`BKP0R`	`0x100`	32	TAMP backup register 0
`BKP1R`	`0x104`	32	TAMP backup register 1
`BKP2R`	`0x108`	32	TAMP backup register 2
`BKP3R`	`0x10C`	32	TAMP backup register 3
`BKP4R`	`0x110`	32	TAMP backup register 4
`BKP5R`	`0x114`	32	TAMP backup register 5
`BKP6R`	`0x118`	32	TAMP backup register 6
`BKP7R`	`0x11C`	32	TAMP backup register 7
`BKP8R`	`0x120`	32	TAMP backup register 8
`BKP9R`	`0x124`	32	TAMP backup register 9
`BKP10R`	`0x128`	32	TAMP backup register 10
`BKP11R`	`0x12C`	32	TAMP backup register 11
`BKP12R`	`0x130`	32	TAMP backup register 12
`BKP13R`	`0x134`	32	TAMP backup register 13
`BKP14R`	`0x138`	32	TAMP backup register 14
`BKP15R`	`0x13C`	32	TAMP backup register 15
`BKP16R`	`0x140`	32	TAMP backup register 16
`BKP17R`	`0x144`	32	TAMP backup register 17
`BKP18R`	`0x148`	32	TAMP backup register 18
`BKP19R`	`0x14C`	32	TAMP backup register 19
`BKP20R`	`0x150`	32	TAMP backup register 20
`BKP21R`	`0x154`	32	TAMP backup register 21
`BKP22R`	`0x158`	32	TAMP backup register 22
`BKP23R`	`0x15C`	32	TAMP backup register 23
`BKP24R`	`0x160`	32	TAMP backup register 24
`BKP25R`	`0x164`	32	TAMP backup register 25
`BKP26R`	`0x168`	32	TAMP backup register 26
`BKP27R`	`0x16C`	32	TAMP backup register 27
`BKP28R`	`0x170`	32	TAMP backup register 28
`BKP29R`	`0x174`	32	TAMP backup register 29
`BKP30R`	`0x178`	32	TAMP backup register 30
`BKP31R`	`0x17C`	32	TAMP backup register 31

TIM — Timers (section 13)

Register	Offset	Bits	Purpose
`CR1`	`0x00`	32	TIM control register 1
`TIM_CR1_CEN`		0	Counter enable
`TIM_CR1_UDIS`		1	Update disable
`TIM_CR1_URS`		2	Update request source
`TIM_CR1_OPM`		3	One pulse mode
`TIM_CR1_DIR`		4	Direction
`TIM_CR1_CMS`		5:6	CMS[1:0] bits (Center-aligned mode selection)
`TIM_CR1_ARPE`		7	Auto-reload preload enable
`TIM_CR1_CKD`		8:9	CKD[1:0] bits (clock division)
`TIM_CR1_UIFREMAP`		11	Update interrupt flag remap
`TIM_CR1_DITHEN`		12	Dithering enable
`CR2`	`0x04`	32	TIM control register 2
`TIM_CR2_CCPC`		0	Capture/Compare Preloaded Control
`TIM_CR2_CCUS`		2	Capture/Compare Control Update Selection
`TIM_CR2_CCDS`		3	Capture/Compare DMA Selection
`TIM_CR2_MMS`		4:25	MMS[3:0] bits (Master Mode Selection)
`TIM_CR2_TI1S`		7	TI1 Selection
`TIM_CR2_OIS1`		8	Output Idle state 1 (OC1 output)
`TIM_CR2_OIS1N`		9	Output Idle state 1 (OC1N output)
`TIM_CR2_OIS2`		10	Output Idle state 2 (OC2 output)
`TIM_CR2_OIS2N`		11	Output Idle state 2 (OC2N output)
`TIM_CR2_OIS3`		12	Output Idle state 3 (OC3 output)
`TIM_CR2_OIS3N`		13	Output Idle state 3 (OC3N output)
`TIM_CR2_OIS4`		14	Output Idle state 4 (OC4 output)
`TIM_CR2_OIS4N`		15	Output Idle state 4 (OC4N output)
`TIM_CR2_OIS5`		16	Output Idle state 5 (OC5 output)
`TIM_CR2_OIS6`		18	Output Idle state 6 (OC6 output)
`TIM_CR2_MMS2`		20:23	MMS[2:0] bits (Master Mode Selection)
`SMCR`	`0x08`	32	TIM slave mode control register
`TIM_SMCR_SMS`		0:16	SMS[2:0] bits (Slave mode selection)
`TIM_SMCR_OCCS`		3	OCREF clear selection
`TIM_SMCR_TS`		4:21	TS[2:0] bits (Trigger selection)
`TIM_SMCR_MSM`		7	Master/slave mode
`TIM_SMCR_ETF`		8:11	ETF[3:0] bits (External trigger filter)
`TIM_SMCR_ETPS`		12:13	ETPS[1:0] bits (External trigger prescaler)
`TIM_SMCR_ECE`		14	External clock enable
`TIM_SMCR_ETP`		15	External trigger polarity
`TIM_SMCR_SMSPE`		25	SMS preload enable
`TIM_SMCR_SMSPS`		26	SMS preload source
`DIER`	`0x0C`	32	TIM DMA/interrupt enable register
`TIM_DIER_UIE`		0	Update interrupt enable
`TIM_DIER_CC1IE`		1	Capture/Compare 1 interrupt enable
`TIM_DIER_CC2IE`		2	Capture/Compare 2 interrupt enable
`TIM_DIER_CC3IE`		3	Capture/Compare 3 interrupt enable
`TIM_DIER_CC4IE`		4	Capture/Compare 4 interrupt enable
`TIM_DIER_COMIE`		5	COM interrupt enable
`TIM_DIER_TIE`		6	Trigger interrupt enable
`TIM_DIER_BIE`		7	Break interrupt enable
`TIM_DIER_UDE`		8	Update DMA request enable
`TIM_DIER_CC1DE`		9	Capture/Compare 1 DMA request enable
`TIM_DIER_CC2DE`		10	Capture/Compare 2 DMA request enable
`TIM_DIER_CC3DE`		11	Capture/Compare 3 DMA request enable
`TIM_DIER_CC4DE`		12	Capture/Compare 4 DMA request enable
`TIM_DIER_COMDE`		13	COM DMA request enable
`TIM_DIER_TDE`		14	Trigger DMA request enable
`TIM_DIER_IDXIE`		20	Encoder index interrupt enable
`TIM_DIER_DIRIE`		21	Encoder direction change interrupt enable
`TIM_DIER_IERRIE`		22	Encoder index error enable
`TIM_DIER_TERRIE`		23	Encoder transition error enable
`SR`	`0x10`	32	TIM status register
`TIM_SR_UIF`		0	Update interrupt Flag
`TIM_SR_CC1IF`		1	Capture/Compare 1 interrupt Flag
`TIM_SR_CC2IF`		2	Capture/Compare 2 interrupt Flag
`TIM_SR_CC3IF`		3	Capture/Compare 3 interrupt Flag
`TIM_SR_CC4IF`		4	Capture/Compare 4 interrupt Flag
`TIM_SR_COMIF`		5	COM interrupt Flag
`TIM_SR_TIF`		6	Trigger interrupt Flag
`TIM_SR_BIF`		7	Break interrupt Flag
`TIM_SR_B2IF`		8	Break 2 interrupt Flag
`TIM_SR_CC1OF`		9	Capture/Compare 1 Overcapture Flag
`TIM_SR_CC2OF`		10	Capture/Compare 2 Overcapture Flag
`TIM_SR_CC3OF`		11	Capture/Compare 3 Overcapture Flag
`TIM_SR_CC4OF`		12	Capture/Compare 4 Overcapture Flag
`TIM_SR_SBIF`		13	System Break interrupt Flag
`TIM_SR_CC5IF`		16	Capture/Compare 5 interrupt Flag
`TIM_SR_CC6IF`		17	Capture/Compare 6 interrupt Flag
`TIM_SR_IDXF`		20	Encoder index interrupt flag
`TIM_SR_DIRF`		21	Encoder direction change interrupt flag
`TIM_SR_IERRF`		22	Encoder index error flag
`TIM_SR_TERRF`		23	Encoder transition error flag
`EGR`	`0x14`	32	TIM event generation register
`TIM_EGR_UG`		0	Update Generation
`TIM_EGR_CC1G`		1	Capture/Compare 1 Generation
`TIM_EGR_CC2G`		2	Capture/Compare 2 Generation
`TIM_EGR_CC3G`		3	Capture/Compare 3 Generation
`TIM_EGR_CC4G`		4	Capture/Compare 4 Generation
`TIM_EGR_COMG`		5	Capture/Compare Control Update Generation
`TIM_EGR_TG`		6	Trigger Generation
`TIM_EGR_BG`		7	Break Generation
`TIM_EGR_B2G`		8	Break 2 Generation
`CCMR1`	`0x18`	32	TIM capture/compare mode register 1
`TIM_CCMR1_CC1S`		0:1	CC1S[1:0] bits (Capture/Compare 1 Selection)
`TIM_CCMR1_OC1FE`		2	Output Compare 1 Fast enable
`TIM_CCMR1_IC1PSC`		2:3	IC1PSC[1:0] bits (Input Capture 1 Prescaler)
`TIM_CCMR1_OC1PE`		3	Output Compare 1 Preload enable
`TIM_CCMR1_OC1M`		4:16	OC1M[2:0] bits (Output Compare 1 Mode)
`TIM_CCMR1_IC1F`		4:7	IC1F[3:0] bits (Input Capture 1 Filter)
`TIM_CCMR1_OC1CE`		7	Output Compare 1 Clear Enable
`TIM_CCMR1_CC2S`		8:9	CC2S[1:0] bits (Capture/Compare 2 Selection)
`TIM_CCMR1_OC2FE`		10	Output Compare 2 Fast enable
`TIM_CCMR1_IC2PSC`		10:11	IC2PSC[1:0] bits (Input Capture 2 Prescaler)
`TIM_CCMR1_OC2PE`		11	Output Compare 2 Preload enable
`TIM_CCMR1_OC2M`		12:24	OC2M[2:0] bits (Output Compare 2 Mode)
`TIM_CCMR1_IC2F`		12:15	IC2F[3:0] bits (Input Capture 2 Filter)
`TIM_CCMR1_OC2CE`		15	Output Compare 2 Clear Enable
`CCMR2`	`0x1C`	32	TIM capture/compare mode register 2
`TIM_CCMR2_CC3S`		0:1	CC3S[1:0] bits (Capture/Compare 3 Selection)
`TIM_CCMR2_OC3FE`		2	Output Compare 3 Fast enable
`TIM_CCMR2_IC3PSC`		2:3	IC3PSC[1:0] bits (Input Capture 3 Prescaler)
`TIM_CCMR2_OC3PE`		3	Output Compare 3 Preload enable
`TIM_CCMR2_OC3M`		4:16	OC3M[2:0] bits (Output Compare 3 Mode)
`TIM_CCMR2_IC3F`		4:7	IC3F[3:0] bits (Input Capture 3 Filter)
`TIM_CCMR2_OC3CE`		7	Output Compare 3 Clear Enable
`TIM_CCMR2_CC4S`		8:9	CC4S[1:0] bits (Capture/Compare 4 Selection)
`TIM_CCMR2_OC4FE`		10	Output Compare 4 Fast enable
`TIM_CCMR2_IC4PSC`		10:11	IC4PSC[1:0] bits (Input Capture 4 Prescaler)
`TIM_CCMR2_OC4PE`		11	Output Compare 4 Preload enable
`TIM_CCMR2_OC4M`		12:24	OC4M[2:0] bits (Output Compare 4 Mode)
`TIM_CCMR2_IC4F`		12:15	IC4F[3:0] bits (Input Capture 4 Filter)
`TIM_CCMR2_OC4CE`		15	Output Compare 4 Clear Enable
`CCER`	`0x20`	32	TIM capture/compare enable register
`TIM_CCER_CC1E`		0	Capture/Compare 1 output enable
`TIM_CCER_CC1P`		1	Capture/Compare 1 output Polarity
`TIM_CCER_CC1NE`		2	Capture/Compare 1 Complementary output enable
`TIM_CCER_CC1NP`		3	Capture/Compare 1 Complementary output Polarity
`TIM_CCER_CC2E`		4	Capture/Compare 2 output enable
`TIM_CCER_CC2P`		5	Capture/Compare 2 output Polarity
`TIM_CCER_CC2NE`		6	Capture/Compare 2 Complementary output enable
`TIM_CCER_CC2NP`		7	Capture/Compare 2 Complementary output Polarity
`TIM_CCER_CC3E`		8	Capture/Compare 3 output enable
`TIM_CCER_CC3P`		9	Capture/Compare 3 output Polarity
`TIM_CCER_CC3NE`		10	Capture/Compare 3 Complementary output enable
`TIM_CCER_CC3NP`		11	Capture/Compare 3 Complementary output Polarity
`TIM_CCER_CC4E`		12	Capture/Compare 4 output enable
`TIM_CCER_CC4P`		13	Capture/Compare 4 output Polarity
`TIM_CCER_CC4NE`		14	Capture/Compare 4 Complementary output enable
`TIM_CCER_CC4NP`		15	Capture/Compare 4 Complementary output Polarity
`TIM_CCER_CC5E`		16	Capture/Compare 5 output enable
`TIM_CCER_CC5P`		17	Capture/Compare 5 output Polarity
`TIM_CCER_CC6E`		20	Capture/Compare 6 output enable
`TIM_CCER_CC6P`		21	Capture/Compare 6 output Polarity
`CNT`	`0x24`	32	TIM counter register
`TIM_CNT_CNT`		0:31	Counter Value
`TIM_CNT_UIFCPY`		31	Update interrupt flag copy (if UIFREMAP=1)
`PSC`	`0x28`	32	TIM prescaler
`TIM_PSC_PSC`		0:15	Prescaler Value
`ARR`	`0x2C`	32	TIM auto-reload register
`TIM_ARR_ARR`		0:31	Actual auto-reload Value
`RCR`	`0x30`	32	TIM repetition counter register
`TIM_RCR_REP`		0:15	Repetition Counter Value
`CCR1`	`0x34`	32	TIM capture/compare register 1
`TIM_CCR1_CCR1`		0:15	Capture/Compare 1 Value
`CCR2`	`0x38`	32	TIM capture/compare register 2
`TIM_CCR2_CCR2`		0:15	Capture/Compare 2 Value
`CCR3`	`0x3C`	32	TIM capture/compare register 3
`TIM_CCR3_CCR3`		0:15	Capture/Compare 3 Value
`CCR4`	`0x40`	32	TIM capture/compare register 4
`TIM_CCR4_CCR4`		0:15	Capture/Compare 4 Value
`BDTR`	`0x44`	32	TIM break and dead-time register
`TIM_BDTR_DTG`		0:7	DTG[0:7] bits (Dead-Time Generator set-up)
`TIM_BDTR_LOCK`		8:9	LOCK[1:0] bits (Lock Configuration)
`TIM_BDTR_OSSI`		10	Off-State Selection for Idle mode
`TIM_BDTR_OSSR`		11	Off-State Selection for Run mode
`TIM_BDTR_BKE`		12	Break enable for Break 1
`TIM_BDTR_BKP`		13	Break Polarity for Break 1
`TIM_BDTR_AOE`		14	Automatic Output enable
`TIM_BDTR_MOE`		15	Main Output enable
`TIM_BDTR_BKF`		16:19	Break Filter for Break 1
`TIM_BDTR_BK2F`		20:23	Break Filter for Break 2
`TIM_BDTR_BK2E`		24	Break enable for Break 2
`TIM_BDTR_BK2P`		25	Break Polarity for Break 2
`TIM_BDTR_BKDSRM`		26	Break disarming/re-arming
`TIM_BDTR_BK2DSRM`		27	Break2 disarming/re-arming
`TIM_BDTR_BKBID`		28	Break BIDirectional
`TIM_BDTR_BK2BID`		29	Break2 BIDirectional
`CCR5`	`0x48`	32	TIM capture/compare register 5
`TIM_CCR5_CCR5`		0:31	Capture/Compare 5 Value
`TIM_CCR5_GC5C1`		29	Group Channel 5 and Channel 1
`TIM_CCR5_GC5C2`		30	Group Channel 5 and Channel 2
`TIM_CCR5_GC5C3`		31	Group Channel 5 and Channel 3
`CCR6`	`0x4C`	32	TIM capture/compare register 6
`TIM_CCR6_CCR6`		0:15	Capture/Compare 6 Value
`CCMR3`	`0x50`	32	TIM capture/compare mode register 3
`TIM_CCMR3_OC5FE`		2	Output Compare 5 Fast enable
`TIM_CCMR3_OC5PE`		3	Output Compare 5 Preload enable
`TIM_CCMR3_OC5M`		4:16	OC5M[3:0] bits (Output Compare 5 Mode)
`TIM_CCMR3_OC5CE`		7	Output Compare 5 Clear Enable
`TIM_CCMR3_OC6FE`		10	Output Compare 6 Fast enable
`TIM_CCMR3_OC6PE`		11	Output Compare 6 Preload enable
`TIM_CCMR3_OC6M`		12:24	OC6M[3:0] bits (Output Compare 6 Mode)
`TIM_CCMR3_OC6CE`		15	Output Compare 6 Clear Enable
`DTR2`	`0x54`	32	TIM deadtime register 2
`TIM_DTR2_DTGF`		0:3	DTGF[7:0] bits (Deadtime falling edge generator setup)
`TIM_DTR2_DTAE`		14	Deadtime asymmetric enable
`TIM_DTR2_DTPE`		15	Deadtime prelaod enable
`ECR`	`0x58`	32	TIM encoder control register
`TIM_ECR_IE`		0	Index enable
`TIM_ECR_IDIR`		1:2	IDIR[1:0] bits (Index direction)
`TIM_ECR_IBLK`		3:4	IBLK[1:0] bits (Index blanking)
`TIM_ECR_FIDX`		5	First index enable
`TIM_ECR_IPOS`		6:7	IPOS[1:0] bits (Index positioning)
`TIM_ECR_PW`		16:23	PW[7:0] bits (Pulse width)
`TIM_ECR_PWPRSC`		24:26	PWPRSC[2:0] bits (Pulse width prescaler)
`TISEL`	`0x5C`	32	TIM Input Selection register
`TIM_TISEL_TI1SEL`		0:3	TI1SEL[3:0] bits (TIM1 TI1 SEL)
`TIM_TISEL_TI2SEL`		8:11	TI2SEL[3:0] bits (TIM1 TI2 SEL)
`TIM_TISEL_TI3SEL`		16:19	TI3SEL[3:0] bits (TIM1 TI3 SEL)
`TIM_TISEL_TI4SEL`		24:27	TI4SEL[3:0] bits (TIM1 TI4 SEL)
`AF1`	`0x60`	32	TIM alternate function option register 1
`AF2`	`0x64`	32	TIM alternate function option register 2
`OR1`	`0x68`	32	TIM option register
`TIM_OR1_RTCPREEN`		1	RTCPRE HSE divider enable
`DCR`	`0x3DC`	32	TIM DMA control register
`TIM_DCR_DBA`		0:4	DBA[4:0] bits (DMA Base Address)
`TIM_DCR_DBL`		8:12	DBL[4:0] bits (DMA Burst Length)
`TIM_DCR_DBSS`		8:11	DBSS[19:16] bits (DMA Burst Source Selection)
`DMAR`	`0x3E0`	32	TIM DMA address for full transfer
`TIM_DMAR_DMAB`		0:31	DMA register for burst accesses

LPTIM — Low-power timer (section 46)

Register	Offset	Bits	Purpose
`ISR`	`0x00`	32	LPTIM Interrupt and Status register
`LPTIM_ISR_CC1IF`		0	Capture/Compare 1 interrupt flag
`LPTIM_ISR_ARRM`		1	Autoreload match
`LPTIM_ISR_EXTTRIG`		2	External trigger edge event
`LPTIM_ISR_CMP1OK`		3	Compare register 1 update OK
`LPTIM_ISR_ARROK`		4	Autoreload register update OK
`LPTIM_ISR_UP`		5	Counter direction change down to up
`LPTIM_ISR_DOWN`		6	Counter direction change up to down
`LPTIM_ISR_UE`		7	Update event
`LPTIM_ISR_REPOK`		8	Repetition register update OK
`LPTIM_ISR_CC2IF`		9	Capture/Compare 2 interrupt flag
`LPTIM_ISR_CC1OF`		12	Capture/Compare 1 over-capture flag
`LPTIM_ISR_CC2OF`		13	Capture/Compare 2 over-capture flag
`LPTIM_ISR_CMP2OK`		19	Compare register 2 update OK
`LPTIM_ISR_DIEROK`		24	DMA & interrupt enable update OK
`ICR`	`0x04`	32	LPTIM Interrupt Clear register
`LPTIM_ICR_CC1CF`		0	Capture/Compare 1 clear flag
`LPTIM_ICR_ARRMCF`		1	Autoreload match clear flag
`LPTIM_ICR_EXTTRIGCF`		2	External trigger edge event clear flag
`LPTIM_ICR_CMP1OKCF`		3	Compare register 1 update OK clear flag
`LPTIM_ICR_ARROKCF`		4	Autoreload register update OK clear flag
`LPTIM_ICR_UPCF`		5	Counter direction change down to up clear flag
`LPTIM_ICR_DOWNCF`		6	Counter direction change up to down clear flag
`LPTIM_ICR_UECF`		7	Update event clear flag
`LPTIM_ICR_REPOKCF`		8	Repetition register update OK clear flag
`LPTIM_ICR_CC2CF`		9	Capture/Compare 2 clear flag
`LPTIM_ICR_CC1OCF`		12	Capture/Compare 1 over-capture clear flag
`LPTIM_ICR_CC2OCF`		13	Capture/Compare 2 over-capture clear flag
`LPTIM_ICR_CMP2OKCF`		19	Compare register 2 update OK clear flag
`LPTIM_ICR_DIEROKCF`		24	Interrupt enable register update OK clear flag
`DIER`	`0x08`	32	LPTIM Interrupt Enable register
`LPTIM_DIER_CC1IE`		0	Compare/Compare interrupt enable
`LPTIM_DIER_ARRMIE`		1	Autoreload match interrupt enable
`LPTIM_DIER_EXTTRIGIE`		2	External trigger edge event interrupt enable
`LPTIM_DIER_CMP1OKIE`		3	Compare register 1 update OK interrupt enable
`LPTIM_DIER_ARROKIE`		4	Autoreload register update OK interrupt enable
`LPTIM_DIER_UPIE`		5	Counter direction change down to up interrupt enable
`LPTIM_DIER_DOWNIE`		6	Counter direction change up to down interrupt enable
`LPTIM_DIER_UEIE`		7	Update event interrupt enable
`LPTIM_DIER_REPOKIE`		8	Repetition register update OK interrupt enable
`LPTIM_DIER_CC2IE`		9	Capture/Compare 2 interrupt interrupt enable
`LPTIM_DIER_CC1OIE`		12	Capture/Compare 1 over-capture interrupt enable
`LPTIM_DIER_CC2OIE`		13	Capture/Compare 2 over-capture interrupt enable
`LPTIM_DIER_CC1DE`		16	Capture/Compare 1 DMA request enable
`LPTIM_DIER_CMP2OKIE`		19	Compare register 2 update OK interrupt enable
`LPTIM_DIER_UEDE`		23	Update event DMA request enable
`LPTIM_DIER_CC2DE`		25	Capture/Compare 2 DMA request enable
`CFGR`	`0x0C`	32	LPTIM Configuration register
`LPTIM_CFGR_CKSEL`		0	Clock selector
`LPTIM_CFGR_CKPOL`		1:2	CKPOL[1:0] bits (Clock polarity)
`LPTIM_CFGR_CKFLT`		3:4	CKFLT[1:0] bits (Configurable digital filter for external clock)
`LPTIM_CFGR_TRGFLT`		6:7	TRGFLT[1:0] bits (Configurable digital filter for trigger)
`LPTIM_CFGR_PRESC`		9:11	PRESC[2:0] bits (Clock prescaler)
`LPTIM_CFGR_TRIGSEL`		13:15	TRIGSEL[2:0]] bits (Trigger selector)
`LPTIM_CFGR_TRIGEN`		17:18	TRIGEN[1:0] bits (Trigger enable and polarity)
`LPTIM_CFGR_TIMOUT`		19	Timout enable
`LPTIM_CFGR_WAVE`		20	Waveform shape
`LPTIM_CFGR_WAVPOL`		21	Waveform shape
`LPTIM_CFGR_PRELOAD`		22	Reg update mode
`LPTIM_CFGR_COUNTMODE`		23	Counter mode enable
`LPTIM_CFGR_ENC`		24	Encoder mode enable
`CR`	`0x10`	32	LPTIM Control register
`LPTIM_CR_ENABLE`		0	LPTIMer enable
`LPTIM_CR_SNGSTRT`		1	Timer start in single mode
`LPTIM_CR_CNTSTRT`		2	Timer start in continuous mode
`LPTIM_CR_COUNTRST`		3	Timer Counter reset in synchronous mode
`LPTIM_CR_RSTARE`		4	Timer Counter reset after read enable (asynchronously)
`CCR1`	`0x14`	32	LPTIM Capture/Compare register 1
`LPTIM_CCR1_CCR1`		0:15	Compare register 1
`ARR`	`0x18`	32	LPTIM Autoreload register
`LPTIM_ARR_ARR`		0:15	Auto reload register
`CNT`	`0x1C`	32	LPTIM Counter register
`LPTIM_CNT_CNT`		0:15	Counter register
`CFGR2`	`0x24`	32	LPTIM Configuration register 2
`LPTIM_CFGR2_IN1SEL`		0:1	IN1SEL[1:0] bits (Remap selection)
`LPTIM_CFGR2_IC1SEL`		0:1	IC1SEL[17:16] bits
`LPTIM_CFGR2_IN2SEL`		4:5	IN2SEL[5:4] bits (Remap selection)
`LPTIM_CFGR2_IC2SEL`		4:5	IC2SEL[21:20] bits
`RCR`	`0x28`	32	LPTIM Repetition register
`LPTIM_RCR_REP`		0:7	Repetition register value
`CCMR1`	`0x2C`	32	LPTIM Capture/Compare mode register
`LPTIM_CCMR1_CC1SEL`		0	Capture/Compare 1 selection
`LPTIM_CCMR1_CC1E`		1	Capture/Compare 1 output enable
`LPTIM_CCMR1_CC1P`		2:3	Capture/Compare 1 output polarity
`LPTIM_CCMR1_IC1PSC`		8:9	Input capture 1 prescaler
`LPTIM_CCMR1_IC1F`		12:13	Input capture 1 filter
`LPTIM_CCMR1_CC2SEL`		16	Capture/Compare 2 selection
`LPTIM_CCMR1_CC2E`		17	Capture/Compare 2 output enable
`LPTIM_CCMR1_CC2P`		18:19	Capture/Compare 2 output polarity
`LPTIM_CCMR1_IC2PSC`		24:25	Input capture 2 prescaler
`LPTIM_CCMR1_IC2F`		28:29	Input capture 2 filter
`CCR2`	`0x34`	32	LPTIM Capture/Compare register 2
`LPTIM_CCR2_CCR2`		0:15	Compare register 2

ADC — ADC (section 14)

Register	Offset	Bits	Purpose
`ISR`	`0x00`	32	ADC interrupt and status register
`ADC_ISR_ADRDY`		0	ADC ready flag
`ADC_ISR_EOSMP`		1	ADC group regular end of sampling flag
`ADC_ISR_EOC`		2	ADC group regular end of unitary conversion flag
`ADC_ISR_EOS`		3	ADC group regular end of sequence conversions flag
`ADC_ISR_OVR`		4	ADC group regular overrun flag
`ADC_ISR_JEOC`		5	ADC group injected end of unitary conversion flag
`ADC_ISR_JEOS`		6	ADC group injected end of sequence conversions flag
`ADC_ISR_AWD1`		7	ADC analog watchdog 1 flag
`ADC_ISR_AWD2`		8	ADC analog watchdog 2 flag
`ADC_ISR_AWD3`		9	ADC analog watchdog 3 flag
`ADC_ISR_JQOVF`		10	ADC group injected contexts queue overflow flag
`IER`	`0x04`	32	ADC interrupt enable register
`ADC_IER_ADRDYIE`		0	ADC ready interrupt
`ADC_IER_EOSMPIE`		1	ADC group regular end of sampling interrupt
`ADC_IER_EOCIE`		2	ADC group regular end of unitary conversion interrupt
`ADC_IER_EOSIE`		3	ADC group regular end of sequence conversions interrupt
`ADC_IER_OVRIE`		4	ADC group regular overrun interrupt
`ADC_IER_JEOCIE`		5	ADC group injected end of unitary conversion interrupt
`ADC_IER_JEOSIE`		6	ADC group injected end of sequence conversions interrupt
`ADC_IER_AWD1IE`		7	ADC analog watchdog 1 interrupt
`ADC_IER_AWD2IE`		8	ADC analog watchdog 2 interrupt
`ADC_IER_AWD3IE`		9	ADC analog watchdog 3 interrupt
`ADC_IER_JQOVFIE`		10	ADC group injected contexts queue overflow interrupt
`CR`	`0x08`	32	ADC control register
`ADC_CR_ADEN`		0	ADC enable
`ADC_CR_ADDIS`		1	ADC disable
`ADC_CR_ADSTART`		2	ADC group regular conversion start
`ADC_CR_JADSTART`		3	ADC group injected conversion start
`ADC_CR_ADSTP`		4	ADC group regular conversion stop
`ADC_CR_JADSTP`		5	ADC group injected conversion stop
`ADC_CR_ADVREGEN`		28	ADC voltage regulator enable
`ADC_CR_DEEPPWD`		29	ADC deep power down enable
`ADC_CR_ADCALDIF`		30	ADC differential mode for calibration
`ADC_CR_ADCAL`		31	ADC calibration
`CFGR`	`0x0C`	32	ADC configuration register 1
`ADC_CFGR_DMAEN`		0	ADC DMA transfer enable
`ADC_CFGR_DMACFG`		1	ADC DMA transfer configuration
`ADC_CFGR_RES`		3:4	ADC data resolution
`ADC_CFGR_EXTSEL`		5:9	ADC group regular external trigger source
`ADC_CFGR_EXTEN`		10:11	ADC group regular external trigger polarity
`ADC_CFGR_OVRMOD`		12	ADC group regular overrun configuration
`ADC_CFGR_CONT`		13	ADC group regular continuous conversion mode
`ADC_CFGR_AUTDLY`		14	ADC low power auto wait
`ADC_CFGR_ALIGN`		15	ADC data alignment
`ADC_CFGR_DISCEN`		16	ADC group regular sequencer discontinuous mode
`ADC_CFGR_DISCNUM`		17:19	ADC group regular sequencer discontinuous number of ranks
`ADC_CFGR_JDISCEN`		20	ADC group injected sequencer discontinuous mode
`ADC_CFGR_JQM`		21	ADC group injected contexts queue mode
`ADC_CFGR_AWD1SGL`		22	ADC analog watchdog 1 monitoring a single channel or all channels
`ADC_CFGR_AWD1EN`		23	ADC analog watchdog 1 enable on scope ADC group regular
`ADC_CFGR_JAWD1EN`		24	ADC analog watchdog 1 enable on scope ADC group injected
`ADC_CFGR_JAUTO`		25	ADC group injected automatic trigger mode
`ADC_CFGR_AWD1CH`		26:30	ADC analog watchdog 1 monitored channel selection
`ADC_CFGR_JQDIS`		31	ADC group injected contexts queue disable
`CFGR2`	`0x10`	32	ADC configuration register 2
`ADC_CFGR2_ROVSE`		0	ADC oversampler enable on scope ADC group regular
`ADC_CFGR2_JOVSE`		1	ADC oversampler enable on scope ADC group injected
`ADC_CFGR2_OVSR`		2:4	ADC oversampling ratio
`ADC_CFGR2_OVSS`		5:8	ADC oversampling shift
`ADC_CFGR2_TROVS`		9	ADC oversampling discontinuous mode (triggered mode) for ADC group regular
`ADC_CFGR2_ROVSM`		10	ADC oversampling mode managing interlaced conversions of ADC group regular and group injected
`ADC_CFGR2_GCOMP`		16	ADC Gain Compensation mode
`ADC_CFGR2_SWTRIG`		25	ADC Software Trigger Bit for Sample time control trigger mode
`ADC_CFGR2_BULB`		26	ADC Bulb sampling mode
`ADC_CFGR2_SMPTRIG`		27	ADC Sample Time Control Trigger mode
`ADC_CFGR2_LFTRIG`		29	ADC Low Frequency Trigger
`SMPR1`	`0x14`	32	ADC sampling time register 1
`ADC_SMPR1_SMP0`		0:2	ADC channel 0 sampling time selection
`ADC_SMPR1_SMP1`		3:5	ADC channel 1 sampling time selection
`ADC_SMPR1_SMP2`		6:8	ADC channel 2 sampling time selection
`ADC_SMPR1_SMP3`		9:11	ADC channel 3 sampling time selection
`ADC_SMPR1_SMP4`		12:14	ADC channel 4 sampling time selection
`ADC_SMPR1_SMP5`		15:17	ADC channel 5 sampling time selection
`ADC_SMPR1_SMP6`		18:20	ADC channel 6 sampling time selection
`ADC_SMPR1_SMP7`		21:23	ADC channel 7 sampling time selection
`ADC_SMPR1_SMP8`		24:26	ADC channel 8 sampling time selection
`ADC_SMPR1_SMP9`		27:29	ADC channel 9 sampling time selection
`ADC_SMPR1_SMPPLUS`		31	ADC channels sampling time additional setting
`SMPR2`	`0x18`	32	ADC sampling time register 2
`ADC_SMPR2_SMP10`		0:2	ADC channel 10 sampling time selection
`ADC_SMPR2_SMP11`		3:5	ADC channel 11 sampling time selection
`ADC_SMPR2_SMP12`		6:8	ADC channel 12 sampling time selection
`ADC_SMPR2_SMP13`		9:11	ADC channel 13 sampling time selection
`ADC_SMPR2_SMP14`		12:14	ADC channel 14 sampling time selection
`ADC_SMPR2_SMP15`		15:17	ADC channel 15 sampling time selection
`ADC_SMPR2_SMP16`		18:20	ADC channel 16 sampling time selection
`ADC_SMPR2_SMP17`		21:23	ADC channel 17 sampling time selection
`ADC_SMPR2_SMP18`		24:26	ADC channel 18 sampling time selection
`TR1`	`0x20`	32	ADC analog watchdog 1 threshold register
`ADC_TR1_LT1`		0:11	ADC analog watchdog 1 threshold low
`ADC_TR1_AWDFILT`		12:14	ADC analog watchdog filtering parameter
`ADC_TR1_HT1`		16:27	ADC analog watchdog 1 threshold high
`TR2`	`0x24`	32	ADC analog watchdog 2 threshold register
`ADC_TR2_LT2`		0:7	ADC analog watchdog 2 threshold low
`ADC_TR2_HT2`		16:23	ADC analog watchdog 2 threshold high
`TR3`	`0x28`	32	ADC analog watchdog 3 threshold register
`ADC_TR3_LT3`		0:7	ADC analog watchdog 3 threshold low
`ADC_TR3_HT3`		16:23	ADC analog watchdog 3 threshold high
`SQR1`	`0x30`	32	ADC group regular sequencer register 1
`ADC_SQR1_L`		0:3	ADC group regular sequencer scan length
`ADC_SQR1_SQ1`		6:10	ADC group regular sequencer rank 1
`ADC_SQR1_SQ2`		12:16	ADC group regular sequencer rank 2
`ADC_SQR1_SQ3`		18:22	ADC group regular sequencer rank 3
`ADC_SQR1_SQ4`		24:28	ADC group regular sequencer rank 4
`SQR2`	`0x34`	32	ADC group regular sequencer register 2
`ADC_SQR2_SQ5`		0:4	ADC group regular sequencer rank 5
`ADC_SQR2_SQ6`		6:10	ADC group regular sequencer rank 6
`ADC_SQR2_SQ7`		12:16	ADC group regular sequencer rank 7
`ADC_SQR2_SQ8`		18:22	ADC group regular sequencer rank 8
`ADC_SQR2_SQ9`		24:28	ADC group regular sequencer rank 9
`SQR3`	`0x38`	32	ADC group regular sequencer register 3
`ADC_SQR3_SQ10`		0:4	ADC group regular sequencer rank 10
`ADC_SQR3_SQ11`		6:10	ADC group regular sequencer rank 11
`ADC_SQR3_SQ12`		12:16	ADC group regular sequencer rank 12
`ADC_SQR3_SQ13`		18:22	ADC group regular sequencer rank 13
`ADC_SQR3_SQ14`		24:28	ADC group regular sequencer rank 14
`SQR4`	`0x3C`	32	ADC group regular sequencer register 4
`ADC_SQR4_SQ15`		0:4	ADC group regular sequencer rank 15
`ADC_SQR4_SQ16`		6:10	ADC group regular sequencer rank 16
`DR`	`0x40`	32	ADC group regular data register
`ADC_DR_RDATA`		0:15	ADC group regular conversion data
`JSQR`	`0x4C`	32	ADC group injected sequencer register
`ADC_JSQR_JL`		0:1	ADC group injected sequencer scan length
`ADC_JSQR_JEXTSEL`		2:6	ADC group injected external trigger source
`ADC_JSQR_JEXTEN`		7:8	ADC group injected external trigger polarity
`ADC_JSQR_JSQ1`		9:13	ADC group injected sequencer rank 1
`ADC_JSQR_JSQ2`		14:18	ADC group injected sequencer rank 2
`ADC_JSQR_JSQ3`		21:25	ADC group injected sequencer rank 3
`ADC_JSQR_JSQ4`		27:31	ADC group injected sequencer rank 4
`OFR1`	`0x60`	32	ADC offset register 1
`ADC_OFR1_OFFSET1`		0:11	ADC offset number 1 offset level
`ADC_OFR1_OFFSETPOS`		24	ADC offset number 1 positive
`ADC_OFR1_SATEN`		25	ADC offset number 1 saturation enable
`ADC_OFR1_OFFSET1_CH`		26:30	ADC offset number 1 channel selection
`ADC_OFR1_OFFSET1_EN`		31	ADC offset number 1 enable
`OFR2`	`0x64`	32	ADC offset register 2
`ADC_OFR2_OFFSET2`		0:11	ADC offset number 2 offset level
`ADC_OFR2_OFFSETPOS`		24	ADC offset number 2 positive
`ADC_OFR2_SATEN`		25	ADC offset number 2 saturation enable
`ADC_OFR2_OFFSET2_CH`		26:30	ADC offset number 2 channel selection
`ADC_OFR2_OFFSET2_EN`		31	ADC offset number 2 enable
`OFR3`	`0x68`	32	ADC offset register 3
`ADC_OFR3_OFFSET3`		0:11	ADC offset number 3 offset level
`ADC_OFR3_OFFSETPOS`		24	ADC offset number 3 positive
`ADC_OFR3_SATEN`		25	ADC offset number 3 saturation enable
`ADC_OFR3_OFFSET3_CH`		26:30	ADC offset number 3 channel selection
`ADC_OFR3_OFFSET3_EN`		31	ADC offset number 3 enable
`OFR4`	`0x6C`	32	ADC offset register 4
`ADC_OFR4_OFFSET4`		0:11	ADC offset number 4 offset level
`ADC_OFR4_OFFSETPOS`		24	ADC offset number 4 positive
`ADC_OFR4_SATEN`		25	ADC offset number 4 saturation enable
`ADC_OFR4_OFFSET4_CH`		26:30	ADC offset number 4 channel selection
`ADC_OFR4_OFFSET4_EN`		31	ADC offset number 4 enable
`JDR1`	`0x80`	32	ADC group injected rank 1 data register
`ADC_JDR1_JDATA`		0:15	ADC group injected sequencer rank 1 conversion data
`JDR2`	`0x84`	32	ADC group injected rank 2 data register
`ADC_JDR2_JDATA`		0:15	ADC group injected sequencer rank 2 conversion data
`JDR3`	`0x88`	32	ADC group injected rank 3 data register
`ADC_JDR3_JDATA`		0:15	ADC group injected sequencer rank 3 conversion data
`JDR4`	`0x8C`	32	ADC group injected rank 4 data register
`ADC_JDR4_JDATA`		0:15	ADC group injected sequencer rank 4 conversion data
`AWD2CR`	`0xA0`	32	ADC analog watchdog 2 configuration register
`ADC_AWD2CR_AWD2CH`		0:18	ADC analog watchdog 2 monitored channel selection
`AWD3CR`	`0xA4`	32	ADC analog watchdog 3 Configuration Register
`ADC_AWD3CR_AWD3CH`		0:18	ADC analog watchdog 3 monitored channel selection
`DIFSEL`	`0xB0`	32	ADC differential mode selection register
`ADC_DIFSEL_DIFSEL`		0:18	ADC channel differential or single-ended mode
`CALFACT`	`0xB4`	32	ADC calibration factors
`ADC_CALFACT_CALFACT_S`		0:6	ADC calibration factor in single-ended mode
`ADC_CALFACT_CALFACT_D`		16:22	ADC calibration factor in differential mode
`OR`	`0xC8`	32	ADC option register
`ADC_OR_OP0`		0	ADC Option bit 0
`ADC_OR_OP1`		0	ADC Option bit 1

ADC_Common — ADC: common registers (section 14)

Register	Offset	Bits	Purpose
`CSR`	`0x00`	32	ADC common status register
`ADC_CSR_ADRDY_MST`		0	ADC multimode master ready flag
`ADC_CSR_EOSMP_MST`		1	ADC multimode master group regular end of sampling flag
`ADC_CSR_EOC_MST`		2	ADC multimode master group regular end of unitary conversion flag
`ADC_CSR_EOS_MST`		3	ADC multimode master group regular end of sequence conversions flag
`ADC_CSR_OVR_MST`		4	ADC multimode master group regular overrun flag
`ADC_CSR_JEOC_MST`		5	ADC multimode master group injected end of unitary conversion flag
`ADC_CSR_JEOS_MST`		6	ADC multimode master group injected end of sequence conversions flag
`ADC_CSR_AWD1_MST`		7	ADC multimode master analog watchdog 1 flag
`ADC_CSR_AWD2_MST`		8	ADC multimode master analog watchdog 2 flag
`ADC_CSR_AWD3_MST`		9	ADC multimode master analog watchdog 3 flag
`ADC_CSR_JQOVF_MST`		10	ADC multimode master group injected contexts queue overflow flag
`ADC_CSR_ADRDY_SLV`		16	ADC multimode slave ready flag
`ADC_CSR_EOSMP_SLV`		17	ADC multimode slave group regular end of sampling flag
`ADC_CSR_EOC_SLV`		18	ADC multimode slave group regular end of unitary conversion flag
`ADC_CSR_EOS_SLV`		19	ADC multimode slave group regular end of sequence conversions flag
`ADC_CSR_OVR_SLV`		20	ADC multimode slave group regular overrun flag
`ADC_CSR_JEOC_SLV`		21	ADC multimode slave group injected end of unitary conversion flag
`ADC_CSR_JEOS_SLV`		22	ADC multimode slave group injected end of sequence conversions flag
`ADC_CSR_AWD1_SLV`		23	ADC multimode slave analog watchdog 1 flag
`ADC_CSR_AWD2_SLV`		24	ADC multimode slave analog watchdog 2 flag
`ADC_CSR_AWD3_SLV`		25	ADC multimode slave analog watchdog 3 flag
`ADC_CSR_JQOVF_SLV`		26	ADC multimode slave group injected contexts queue overflow flag
`CCR`	`0x08`	32	ADC common configuration register
`ADC_CCR_DUAL`		0:4	ADC multimode mode selection
`ADC_CCR_DELAY`		8:11	ADC multimode delay between 2 sampling phases
`ADC_CCR_DMACFG`		13	ADC multimode DMA transfer configuration
`ADC_CCR_MDMA`		14:15	ADC multimode DMA transfer enable
`ADC_CCR_CKMODE`		16:17	ADC common clock source and prescaler (prescaler only for clock source synchronous)
`ADC_CCR_PRESC`		18:21	ADC common clock prescaler, only for clock source asynchronous
`ADC_CCR_VREFEN`		22	ADC internal path to VrefInt enable
`ADC_CCR_TSEN`		23	ADC internal path to temperature sensor enable
`ADC_CCR_VBATEN`		24	ADC internal path to battery voltage enable
`CDR`	`0x0C`	32	ADC common group regular data register
`ADC_CDR_RDATA_MST`		0:15	ADC multimode master group regular conversion data
`ADC_CDR_RDATA_SLV`		16:31	ADC multimode slave group regular conversion data

DAC — DAC (section 15)

Register	Offset	Bits	Purpose
`CR`	`0x00`	32	DAC control register
`DAC_CR_EN1`		0	DAC channel1 enable
`DAC_CR_TEN1`		1	DAC channel1 Trigger enable
`DAC_CR_TSEL1`		2:5	TSEL1[3:0] (DAC channel1 Trigger selection)
`DAC_CR_WAVE1`		6:7	WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
`DAC_CR_MAMP1`		8:11	MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
`DAC_CR_DMAEN1`		12	DAC channel1 DMA enable
`DAC_CR_DMAUDRIE1`		13	DAC channel 1 DMA underrun interrupt enable >
`DAC_CR_CEN1`		14	DAC channel 1 calibration enable >
`DAC_CR_EN2`		16	DAC channel2 enable
`DAC_CR_TEN2`		17	DAC channel2 Trigger enable
`DAC_CR_TSEL2`		18:21	TSEL2[3:0] (DAC channel2 Trigger selection)
`DAC_CR_WAVE2`		22:23	WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)
`DAC_CR_MAMP2`		24:27	MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)
`DAC_CR_DMAEN2`		28	DAC channel2 DMA enabled
`DAC_CR_DMAUDRIE2`		29	DAC channel2 DMA underrun interrupt enable >
`DAC_CR_CEN2`		30	DAC channel2 calibration enable >
`SWTRIGR`	`0x04`	32	DAC software trigger register
`DAC_SWTRIGR_SWTRIG1`		0	DAC channel1 software trigger
`DAC_SWTRIGR_SWTRIG2`		1	DAC channel2 software trigger
`DAC_SWTRIGR_SWTRIGB1`		16	DAC channel1 software trigger B
`DAC_SWTRIGR_SWTRIGB2`		17	DAC channel2 software trigger B
`DHR12R1`	`0x08`	32	DAC channel1 12-bit right-aligned data holding register
`DAC_DHR12R1_DACC1DHR`		0:11	DAC channel1 12-bit Right aligned data
`DAC_DHR12R1_DACC1DHRB`		16:27	DAC channel1 12-bit Right-aligned data B
`DHR12L1`	`0x0C`	32	DAC channel1 12-bit left aligned data holding register
`DAC_DHR12L1_DACC1DHR`		4:15	DAC channel1 12-bit Left aligned data
`DAC_DHR12L1_DACC1DHRB`		20:31	DAC channel1 12-bit Left aligned data B
`DHR8R1`	`0x10`	32	DAC channel1 8-bit right aligned data holding register
`DAC_DHR8R1_DACC1DHR`		0:7	DAC channel1 8-bit Right aligned data
`DAC_DHR8R1_DACC1DHRB`		8:15	DAC channel1 8-bit Right aligned data B
`DHR12R2`	`0x14`	32	DAC channel2 12-bit right aligned data holding register
`DAC_DHR12R2_DACC2DHR`		0:11	DAC channel2 12-bit Right aligned data
`DAC_DHR12R2_DACC2DHRB`		16:27	DAC channel2 12-bit Right-aligned data B
`DHR12L2`	`0x18`	32	DAC channel2 12-bit left aligned data holding register
`DAC_DHR12L2_DACC2DHR`		4:15	DAC channel2 12-bit Left aligned data
`DAC_DHR12L2_DACC2DHRB`		20:31	DAC channel2 12-bit Left aligned data B
`DHR8R2`	`0x1C`	32	DAC channel2 8-bit right-aligned data holding register
`DAC_DHR8R2_DACC2DHR`		0:7	DAC channel2 8-bit Right aligned data
`DAC_DHR8R2_DACC2DHRB`		8:15	DAC channel2 8-bit Right aligned data B
`DHR12RD`	`0x20`	32	Dual DAC 12-bit right-aligned data holding register
`DAC_DHR12RD_DACC1DHR`		0:11	DAC channel1 12-bit Right aligned data
`DAC_DHR12RD_DACC2DHR`		16:27	DAC channel2 12-bit Right aligned data
`DHR12LD`	`0x24`	32	DUAL DAC 12-bit left aligned data holding register
`DAC_DHR12LD_DACC1DHR`		4:15	DAC channel1 12-bit Left aligned data
`DAC_DHR12LD_DACC2DHR`		20:31	DAC channel2 12-bit Left aligned data
`DHR8RD`	`0x28`	32	DUAL DAC 8-bit right aligned data holding register
`DAC_DHR8RD_DACC1DHR`		0:7	DAC channel1 8-bit Right aligned data
`DAC_DHR8RD_DACC2DHR`		8:15	DAC channel2 8-bit Right aligned data
`DOR1`	`0x2C`	32	DAC channel1 data output register
`DAC_DOR1_DACC1DOR`		0:11	DAC channel1 data output
`DAC_DOR1_DACC1DORB`		16:27	DAC channel1 data output B
`DOR2`	`0x30`	32	DAC channel2 data output register
`DAC_DOR2_DACC2DOR`		0:11	DAC channel2 data output
`DAC_DOR2_DACC2DORB`		16:27	DAC channel2 data output B
`SR`	`0x34`	32	DAC status register
`DAC_SR_DAC1RDY`		11	DAC channel 1 ready status bit
`DAC_SR_DORSTAT1`		12	DAC channel 1 output register status bit
`DAC_SR_DMAUDR1`		13	DAC channel1 DMA underrun flag
`DAC_SR_CAL_FLAG1`		14	DAC channel1 calibration offset status
`DAC_SR_BWST1`		15	DAC channel1 busy writing sample time flag
`DAC_SR_DAC2RDY`		27	DAC channel 2 ready status bit
`DAC_SR_DORSTAT2`		28	DAC channel 2 output register status bit
`DAC_SR_DMAUDR2`		29	DAC channel2 DMA underrun flag
`DAC_SR_CAL_FLAG2`		30	DAC channel2 calibration offset status
`DAC_SR_BWST2`		31	DAC channel2 busy writing sample time flag
`CCR`	`0x38`	32	DAC calibration control register
`DAC_CCR_OTRIM1`		0:4	DAC channel1 offset trimming value
`DAC_CCR_OTRIM2`		16:20	DAC channel2 offset trimming value
`MCR`	`0x3C`	32	DAC mode control register
`DAC_MCR_MODE1`		0:2	MODE1[2:0] (DAC channel1 mode)
`DAC_MCR_DMADOUBLE1`		8	DAC Channel 1 DMA double data mode
`DAC_MCR_SINFORMAT1`		9	DAC Channel 1 enable signed format
`DAC_MCR_HFSEL`		14:15	HFSEL[1:0] (High Frequency interface mode selection)
`DAC_MCR_MODE2`		16:18	MODE2[2:0] (DAC channel2 mode)
`DAC_MCR_DMADOUBLE2`		24	DAC Channel 2 DMA double data mode
`DAC_MCR_SINFORMAT2`		25	DAC Channel 2 enable signed format
`SHSR1`	`0x40`	32	DAC Sample and Hold sample time register 1
`DAC_SHSR1_TSAMPLE1`		0:9	DAC channel1 sample time
`SHSR2`	`0x44`	32	DAC Sample and Hold sample time register 2
`DAC_SHSR2_TSAMPLE2`		0:9	DAC channel2 sample time
`SHHR`	`0x48`	32	DAC Sample and Hold hold time register
`DAC_SHHR_THOLD1`		0:9	DAC channel1 hold time
`DAC_SHHR_THOLD2`		16:25	DAC channel2 hold time
`SHRR`	`0x4C`	32	DAC Sample and Hold refresh time register
`DAC_SHRR_TREFRESH1`		0:7	DAC channel1 refresh time
`DAC_SHRR_TREFRESH2`		16:23	DAC channel2 refresh time
`AUTOCR`	`0x54`	32	DAC Autonomous mode register
`DAC_AUTOCR_AUTOMODE`		22	AUTOCR Enable

USART — UART / USART / LPUART (section 16)

Register	Offset	Bits	Purpose
`CR1`	`0x00`	32	USART Control register 1
`USART_CR1_UE`		0	USART Enable
`USART_CR1_UESM`		1	USART Enable in STOP Mode
`USART_CR1_RE`		2	Receiver Enable
`USART_CR1_TE`		3	Transmitter Enable
`USART_CR1_IDLEIE`		4	IDLE Interrupt Enable
`USART_CR1_RXNEIE`		5	RXNE Interrupt Enable
`USART_CR1_TCIE`		6	Transmission Complete Interrupt Enable
`USART_CR1_TXEIE`		7	TXE Interrupt Enable
`USART_CR1_TXEIE_TXFNFIE`		7
`USART_CR1_PEIE`		8	PE Interrupt Enable
`USART_CR1_PS`		9	Parity Selection
`USART_CR1_PCE`		10	Parity Control Enable
`USART_CR1_WAKE`		11	Receiver Wakeup method
`USART_CR1_M`		12:28	Word length
`USART_CR1_M0`		12	Word length - Bit 0
`USART_CR1_MME`		13	Mute Mode Enable
`USART_CR1_CMIE`		14	Character match interrupt enable
`USART_CR1_OVER8`		15	Oversampling by 8-bit or 16-bit mode
`USART_CR1_DEDT`		16:20	DEDT[4:0] bits (Driver Enable Deassertion Time)
`USART_CR1_DEAT`		21:25	DEAT[4:0] bits (Driver Enable Assertion Time)
`USART_CR1_RTOIE`		26	Receive Time Out interrupt enable
`USART_CR1_EOBIE`		27	End of Block interrupt enable
`USART_CR1_M1`		28	Word length - Bit 1
`USART_CR1_FIFOEN`		29	FIFO mode enable
`USART_CR1_TXFEIE`		30	TXFIFO empty interrupt enable
`USART_CR1_RXFFIE`		31	RXFIFO Full interrupt enable
`CR2`	`0x04`	32	USART Control register 2
`USART_CR2_SLVEN`		0	Synchronous Slave mode enable
`USART_CR2_DIS_NSS`		3	Slave Select (NSS) pin management
`USART_CR2_ADDM7`		4	7-bit or 4-bit Address Detection
`USART_CR2_LBDL`		5	LIN Break Detection Length
`USART_CR2_LBDIE`		6	LIN Break Detection Interrupt Enable
`USART_CR2_LBCL`		8	Last Bit Clock pulse
`USART_CR2_CPHA`		9	Clock Phase
`USART_CR2_CPOL`		10	Clock Polarity
`USART_CR2_CLKEN`		11	Clock Enable
`USART_CR2_STOP`		12:13	STOP[1:0] bits (STOP bits)
`USART_CR2_LINEN`		14	LIN mode enable
`USART_CR2_SWAP`		15	SWAP TX/RX pins
`USART_CR2_RXINV`		16	RX pin active level inversion
`USART_CR2_TXINV`		17	TX pin active level inversion
`USART_CR2_DATAINV`		18	Binary data inversion
`USART_CR2_MSBFIRST`		19	Most Significant Bit First
`USART_CR2_ABREN`		20	Auto Baud-Rate Enable
`USART_CR2_ABRMODE`		21:22	ABRMOD[1:0] bits (Auto Baud-Rate Mode)
`USART_CR2_RTOEN`		23	Receiver Time-Out enable
`USART_CR2_ADD`		24:31	Address of the USART node
`CR3`	`0x08`	32	USART Control register 3
`USART_CR3_EIE`		0	Error Interrupt Enable
`USART_CR3_IREN`		1	IrDA mode Enable
`USART_CR3_IRLP`		2	IrDA Low-Power
`USART_CR3_HDSEL`		3	Half-Duplex Selection
`USART_CR3_NACK`		4	SmartCard NACK enable
`USART_CR3_SCEN`		5	SmartCard mode enable
`USART_CR3_DMAR`		6	DMA Enable Receiver
`USART_CR3_DMAT`		7	DMA Enable Transmitter
`USART_CR3_RTSE`		8	RTS Enable
`USART_CR3_CTSE`		9	CTS Enable
`USART_CR3_CTSIE`		10	CTS Interrupt Enable
`USART_CR3_ONEBIT`		11	One sample bit method enable
`USART_CR3_OVRDIS`		12	Overrun Disable
`USART_CR3_DDRE`		13	DMA Disable on Reception Error
`USART_CR3_DEM`		14	Driver Enable Mode
`USART_CR3_DEP`		15	Driver Enable Polarity Selection
`USART_CR3_SCARCNT`		17:19	SCARCNT[2:0] bits (SmartCard Auto-Retry Count)
`USART_CR3_WUS`		20:21	WUS[1:0] bits (Wake UP Interrupt Flag Selection)
`USART_CR3_WUFIE`		22	Wake Up Interrupt Enable
`USART_CR3_TXFTIE`		23	TXFIFO threshold interrupt enable
`USART_CR3_TCBGTIE`		24	Transmission Complete Before Guard Time Interrupt Enable
`USART_CR3_RXFTCFG`		25:27	RXFIFO FIFO threshold configuration
`USART_CR3_RXFTIE`		28	RXFIFO threshold interrupt enable
`USART_CR3_TXFTCFG`		29:31	TXFIFO threshold configuration
`BRR`	`0x0C`	32	USART Baud rate register
`USART_BRR_LPUART`		0:19	LPUART Baud rate register [19:0]
`GTPR`	`0x10`	32	USART Guard time and prescaler register
`USART_GTPR_PSC`		0:7	PSC[7:0] bits (Prescaler value)
`USART_GTPR_GT`		8:15	GT[7:0] bits (Guard time value)
`RTOR`	`0x14`	32	USART Receiver Time Out register
`USART_RTOR_RTO`		0:23	Receiver Time Out Value
`USART_RTOR_BLEN`		24:31	Block Length
`RQR`	`0x18`	32	USART Request register
`ISR`	`0x1C`	32	USART Interrupt and status register
`USART_ISR_PE`		0	Parity Error
`USART_ISR_FE`		1	Framing Error
`USART_ISR_NE`		2	Noise detected Flag
`USART_ISR_ORE`		3	OverRun Error
`USART_ISR_IDLE`		4	IDLE line detected
`USART_ISR_RXNE`		5	Read Data Register Not Empty
`USART_ISR_TC`		6	Transmission Complete
`USART_ISR_TXE`		7	Transmit Data Register Empty
`USART_ISR_LBDF`		8	LIN Break Detection Flag
`USART_ISR_CTSIF`		9	CTS interrupt flag
`USART_ISR_CTS`		10	CTS flag
`USART_ISR_RTOF`		11	Receiver Time Out
`USART_ISR_EOBF`		12	End Of Block Flag
`USART_ISR_UDR`		13	SPI slave underrun error flag
`USART_ISR_ABRE`		14	Auto-Baud Rate Error
`USART_ISR_ABRF`		15	Auto-Baud Rate Flag
`USART_ISR_BUSY`		16	Busy Flag
`USART_ISR_CMF`		17	Character Match Flag
`USART_ISR_SBKF`		18	Send Break Flag
`USART_ISR_RWU`		19	Receive Wake Up from mute mode Flag
`USART_ISR_WUF`		20	Wake Up from low power mode Flag
`USART_ISR_TEACK`		21	Transmit Enable Acknowledge Flag
`USART_ISR_REACK`		22	Receive Enable Acknowledge Flag
`USART_ISR_TXFE`		23	TXFIFO Empty
`USART_ISR_RXFF`		24	RXFIFO Full
`USART_ISR_TCBGT`		25	Transmission Complete Before Guard Time completion
`USART_ISR_RXFT`		26	RXFIFO threshold flag
`USART_ISR_TXFT`		27	TXFIFO threshold flag
`ICR`	`0x20`	32	USART Interrupt flag Clear register
`USART_ICR_PECF`		0	Parity Error Clear Flag
`USART_ICR_FECF`		1	Framing Error Clear Flag
`USART_ICR_NECF`		2	Noise detected Clear Flag
`USART_ICR_ORECF`		3	OverRun Error Clear Flag
`USART_ICR_IDLECF`		4	IDLE line detected Clear Flag
`USART_ICR_TXFECF`		5	TXFIFO empty Clear flag
`USART_ICR_TCCF`		6	Transmission Complete Clear Flag
`USART_ICR_TCBGTCF`		7	Transmission Complete Before Guard Time Clear Flag
`USART_ICR_LBDCF`		8	LIN Break Detection Clear Flag
`USART_ICR_CTSCF`		9	CTS Interrupt Clear Flag
`USART_ICR_RTOCF`		11	Receiver Time Out Clear Flag
`USART_ICR_EOBCF`		12	End Of Block Clear Flag
`USART_ICR_UDRCF`		13	SPI Slave Underrun Clear Flag
`USART_ICR_CMCF`		17	Character Match Clear Flag
`USART_ICR_WUCF`		20	Wake Up from stop mode Clear Flag
`RDR`	`0x24`	32	USART Receive Data register
`TDR`	`0x28`	32	USART Transmit Data register
`PRESC`	`0x2C`	32	USART Prescaler register
`USART_PRESC_PRESCALER`		0:3	PRESCALER[3:0] bits (Clock prescaler)

I2C — I²C (section 17)

Register	Offset	Bits	Purpose
`CR1`	`0x00`	32	I2C Control register 1
`I2C_CR1_PE`		0	Peripheral enable
`I2C_CR1_TXIE`		1	TX interrupt enable
`I2C_CR1_RXIE`		2	RX interrupt enable
`I2C_CR1_ADDRIE`		3	Address match interrupt enable
`I2C_CR1_NACKIE`		4	NACK received interrupt enable
`I2C_CR1_STOPIE`		5	STOP detection interrupt enable
`I2C_CR1_TCIE`		6	Transfer complete interrupt enable
`I2C_CR1_ERRIE`		7	Errors interrupt enable
`I2C_CR1_DNF`		8:11	Digital noise filter
`I2C_CR1_ANFOFF`		12	Analog noise filter OFF
`I2C_CR1_SWRST`		13	Software reset
`I2C_CR1_TXDMAEN`		14	DMA transmission requests enable
`I2C_CR1_RXDMAEN`		15	DMA reception requests enable
`I2C_CR1_SBC`		16	Slave byte control
`I2C_CR1_NOSTRETCH`		17	Clock stretching disable
`I2C_CR1_WUPEN`		18	Wakeup from STOP enable
`I2C_CR1_GCEN`		19	General call enable
`I2C_CR1_SMBHEN`		20	SMBus host address enable
`I2C_CR1_SMBDEN`		21	SMBus device default address enable
`I2C_CR1_ALERTEN`		22	SMBus alert enable
`I2C_CR1_PECEN`		23	PEC enable
`I2C_CR1_FMP`		24	Fast-mode Plus 20 mA drive enable
`I2C_CR1_ADDRACLR`		30	ADDRACLR enable
`I2C_CR1_STOPFACLR`		31	STOPFACLR enable
`CR2`	`0x04`	32	I2C Control register 2
`I2C_CR2_SADD`		0:9	Slave address (master mode)
`I2C_CR2_RD_WRN`		10	Transfer direction (master mode)
`I2C_CR2_ADD10`		11	10-bit addressing mode (master mode)
`I2C_CR2_HEAD10R`		12	10-bit address header only read direction (master mode)
`I2C_CR2_START`		13	START generation
`I2C_CR2_STOP`		14	STOP generation (master mode)
`I2C_CR2_NACK`		15	NACK generation (slave mode)
`I2C_CR2_NBYTES`		16:23	Number of bytes
`I2C_CR2_RELOAD`		24	NBYTES reload mode
`I2C_CR2_AUTOEND`		25	Automatic end mode (master mode)
`I2C_CR2_PECBYTE`		26	Packet error checking byte
`OAR1`	`0x08`	32	I2C Own address 1 register
`I2C_OAR1_OA1`		0:9	Interface own address 1
`I2C_OAR1_OA1MODE`		10	Own address 1 10-bit mode
`I2C_OAR1_OA1EN`		15	Own address 1 enable
`OAR2`	`0x0C`	32	I2C Own address 2 register
`I2C_OAR2_OA2`		1:7	Interface own address 2
`I2C_OAR2_OA2MSK`		8:10	Own address 2 masks
`I2C_OAR2_OA2MASK01`		8	OA2[1] is masked, Only OA2[7:2] are compared
`I2C_OAR2_OA2MASK03`		8:9	OA2[3:1] is masked, Only OA2[7:4] are compared
`I2C_OAR2_OA2MASK05`		8:10	OA2[5:1] is masked, Only OA2[7:6] are compared
`I2C_OAR2_OA2MASK07`		8:10	OA2[7:1] is masked, No comparison is done
`I2C_OAR2_OA2MASK02`		9	OA2[2:1] is masked, Only OA2[7:3] are compared
`I2C_OAR2_OA2MASK06`		9:10	OA2[6:1] is masked, Only OA2[7] are compared
`I2C_OAR2_OA2MASK04`		10	OA2[4:1] is masked, Only OA2[7:5] are compared
`I2C_OAR2_OA2EN`		15	Own address 2 enable
`TIMINGR`	`0x10`	32	I2C Timing register
`I2C_TIMINGR_SCLL`		0:7	SCL low period (master mode)
`I2C_TIMINGR_SCLH`		8:15	SCL high period (master mode)
`I2C_TIMINGR_SDADEL`		16:19	Data hold time
`I2C_TIMINGR_SCLDEL`		20:23	Data setup time
`I2C_TIMINGR_PRESC`		28:31	Timings prescaler
`TIMEOUTR`	`0x14`	32	I2C Timeout register
`I2C_TIMEOUTR_TIMEOUTA`		0:11	Bus timeout A
`I2C_TIMEOUTR_TIDLE`		12	Idle clock timeout detection
`I2C_TIMEOUTR_TIMOUTEN`		15	Clock timeout enable
`I2C_TIMEOUTR_TIMEOUTB`		16:27	Bus timeout B
`I2C_TIMEOUTR_TEXTEN`		31	Extended clock timeout enable
`ISR`	`0x18`	32	I2C Interrupt and status register
`I2C_ISR_TXE`		0	Transmit data register empty
`I2C_ISR_TXIS`		1	Transmit interrupt status
`I2C_ISR_RXNE`		2	Receive data register not empty
`I2C_ISR_ADDR`		3	Address matched (slave mode)
`I2C_ISR_NACKF`		4	NACK received flag
`I2C_ISR_STOPF`		5	STOP detection flag
`I2C_ISR_TC`		6	Transfer complete (master mode)
`I2C_ISR_TCR`		7	Transfer complete reload
`I2C_ISR_BERR`		8	Bus error
`I2C_ISR_ARLO`		9	Arbitration lost
`I2C_ISR_OVR`		10	Overrun/Underrun
`I2C_ISR_PECERR`		11	PEC error in reception
`I2C_ISR_TIMEOUT`		12	Timeout or Tlow detection flag
`I2C_ISR_ALERT`		13	SMBus alert
`I2C_ISR_BUSY`		15	Bus busy
`I2C_ISR_DIR`		16	Transfer direction (slave mode)
`I2C_ISR_ADDCODE`		17:23	Address match code (slave mode)
`ICR`	`0x1C`	32	I2C Interrupt clear register
`I2C_ICR_ADDRCF`		3	Address matched clear flag
`I2C_ICR_NACKCF`		4	NACK clear flag
`I2C_ICR_STOPCF`		5	STOP detection clear flag
`I2C_ICR_BERRCF`		8	Bus error clear flag
`I2C_ICR_ARLOCF`		9	Arbitration lost clear flag
`I2C_ICR_OVRCF`		10	Overrun/Underrun clear flag
`I2C_ICR_PECCF`		11	PAC error clear flag
`I2C_ICR_TIMOUTCF`		12	Timeout clear flag
`I2C_ICR_ALERTCF`		13	Alert clear flag
`PECR`	`0x20`	32	I2C PEC register
`I2C_PECR_PEC`		0:7	PEC register
`RXDR`	`0x24`	32	I2C Receive data register
`I2C_RXDR_RXDATA`		0:7	8-bit receive data
`TXDR`	`0x28`	32	I2C Transmit data register
`I2C_TXDR_TXDATA`		0:7	8-bit transmit data

SPI — SPI / I²S (section 18)

Register	Offset	Bits	Purpose
`CR1`	`0x00`	32	SPI/I2S Control register 1
`SPI_CR1_SPE`		0	Serial Peripheral Enable
`SPI_CR1_MASRX`		8	Master automatic SUSP in Receive mode
`SPI_CR1_CSTART`		9	Master transfer start
`SPI_CR1_CSUSP`		10	Master SUSPend request
`SPI_CR1_HDDIR`		11	Rx/Tx direction at Half-duplex mode
`SPI_CR1_SSI`		12	Internal SS signal input level
`SPI_CR1_CRC33_17`		13	32-bit CRC polynomial configuration
`SPI_CR1_RCRCINI`		14	CRC init pattern control for receiver
`SPI_CR1_TCRCINI`		15	CRC init pattern control for transmitter
`SPI_CR1_IOLOCK`		16	Locking the AF configuration of associated IOs
`CR2`	`0x04`	32	SPI Control register 2
`SPI_CR2_TSIZE`		0:15	Number of data at current transfer
`CFG1`	`0x08`	32	SPI Configuration register 1
`SPI_CFG1_DSIZE`		0:4	DSIZE[4:0]: Bits number in single SPI data frame
`SPI_CFG1_FTHLV`		5:8	FTHVL [3:0]: FIFO threshold level
`SPI_CFG1_UDRCFG`		9:10	Behavior of Slave transmitter at underrun
`SPI_CFG1_RXDMAEN`		14	Rx DMA stream enable
`SPI_CFG1_TXDMAEN`		15	Tx DMA stream enable
`SPI_CFG1_CRCSIZE`		16:20	CRCSIZE [4:0]: Length of CRC frame
`SPI_CFG1_CRCEN`		22	Hardware CRC computation enable
`SPI_CFG1_MBR`		28:30	Master baud rate
`SPI_CFG1_BPASS`		31	Bypass of the prescaler
`CFG2`	`0x0C`	32	SPI Configuration register 2
`SPI_CFG2_MSSI`		0:3	Master SS Idleness
`SPI_CFG2_MIDI`		4:7	Master Inter-Data Idleness
`SPI_CFG2_RDIOM`		13	RDY signal input/output management
`SPI_CFG2_RDIOP`		14	RDY signal input/output polarity
`SPI_CFG2_IOSWP`		15	Swap functionality of MISO and MOSI pins
`SPI_CFG2_COMM`		17:18	COMM [1:0]: SPI Communication Mode
`SPI_CFG2_SP`		19:21	SP[2:0]: Serial Protocol
`SPI_CFG2_MASTER`		22	SPI Master
`SPI_CFG2_LSBFRST`		23	Data frame format
`SPI_CFG2_CPHA`		24	Clock Phase
`SPI_CFG2_CPOL`		25	Clock Polarity
`SPI_CFG2_SSM`		26	Software slave management
`SPI_CFG2_SSIOP`		28	SS input/output polarity
`SPI_CFG2_SSOE`		29	SS output enable
`SPI_CFG2_SSOM`		30	SS output management in master mode
`SPI_CFG2_AFCNTR`		31	Alternate function GPIOs control
`IER`	`0x10`	32	SPI/I2S Interrupt Enable register
`SPI_IER_RXPIE`		0	RXP Interrupt Enable
`SPI_IER_TXPIE`		1	TXP interrupt enable
`SPI_IER_DXPIE`		2	DXP interrupt enable
`SPI_IER_EOTIE`		3	EOT/SUSP/TXC interrupt enable
`SPI_IER_TXTFIE`		4	TXTF interrupt enable
`SPI_IER_UDRIE`		5	UDR interrupt enable
`SPI_IER_OVRIE`		6	OVR interrupt enable
`SPI_IER_CRCEIE`		7	CRCE interrupt enable
`SPI_IER_TIFREIE`		8	TI Frame Error interrupt enable
`SPI_IER_MODFIE`		9	MODF interrupt enable
`SR`	`0x14`	32	SPI/I2S Status register
`SPI_SR_RXP`		0	Rx-Packet available
`SPI_SR_TXP`		1	Tx-Packet space available
`SPI_SR_DXP`		2	Duplex Packet available
`SPI_SR_EOT`		3	Duplex Packet available
`SPI_SR_TXTF`		4	Transmission Transfer Filled
`SPI_SR_UDR`		5	UDR at Slave transmission
`SPI_SR_OVR`		6	Rx-Packet available
`SPI_SR_CRCE`		7	CRC Error Detected
`SPI_SR_TIFRE`		8	TI frame format error Detected
`SPI_SR_MODF`		9	Mode Fault Detected
`SPI_SR_SUSP`		11	SUSP is set by hardware
`SPI_SR_TXC`		12	TxFIFO transmission complete
`SPI_SR_RXPLVL`		13:14	RxFIFO Packing Level
`SPI_SR_RXWNE`		15	Rx FIFO Word Not Empty
`SPI_SR_CTSIZE`		16:31	Number of data frames remaining in TSIZE
`IFCR`	`0x18`	32	SPI/I2S Interrupt/Status flags clear register
`SPI_IFCR_EOTC`		3	End Of Transfer flag clear
`SPI_IFCR_TXTFC`		4	Transmission Transfer Filled flag clear
`SPI_IFCR_UDRC`		5	Underrun flag clear
`SPI_IFCR_OVRC`		6	Overrun flag clear
`SPI_IFCR_CRCEC`		7	CRC Error flag clear
`SPI_IFCR_TIFREC`		8	TI frame format error flag clear
`SPI_IFCR_MODFC`		9	Mode Fault flag clear
`SPI_IFCR_SUSPC`		11	SUSPend flag clear
`TXDR`	`0x20`	32	SPI/I2S Transmit data register
`SPI_TXDR_TXDR`		0:31	Transmit Data Register
`RXDR`	`0x30`	32	SPI/I2S Receive data register
`SPI_RXDR_RXDR`		0:31	Receive Data Register
`CRCPOLY`	`0x40`	32	SPI CRC Polynomial register
`SPI_CRCPOLY_CRCPOLY`		0:31	CRC Polynomial register
`TXCRC`	`0x44`	32	SPI Transmitter CRC register
`SPI_TXCRC_TXCRC`		0:31	CRCRegister for transmitter
`RXCRC`	`0x48`	32	SPI Receiver CRC register
`SPI_RXCRC_RXCRC`		0:31	CRCRegister for receiver
`UDRDR`	`0x4C`	32	SPI Underrun data register
`SPI_UDRDR_UDRDR`		0:31	Data at slave underrun condition
`I2SCFGR`	`0x50`	32	I2S Configuration register
`SPI_I2SCFGR_I2SMOD`		0	I2S mode selection
`SPI_I2SCFGR_I2SCFG`		1:3	I2SCFG[2:0] I2S configuration mode
`SPI_I2SCFGR_I2SSTD`		4:5	I2SSTD[1:0] I2S standard selection
`SPI_I2SCFGR_PCMSYNC`		7	PCM frame synchronization
`SPI_I2SCFGR_DATLEN`		8:9	DATLEN[1:0] Data length to be transferred
`SPI_I2SCFGR_CHLEN`		10	Channel length (number of bits per audio channel)
`SPI_I2SCFGR_CKPOL`		11	Steady state clock polarity
`SPI_I2SCFGR_FIXCH`		12	Fixed channel length in SLAVE
`SPI_I2SCFGR_WSINV`		13	Word select inversion
`SPI_I2SCFGR_DATFMT`		14	Data format
`SPI_I2SCFGR_I2SDIV`		16:23	I2S Linear prescaler
`SPI_I2SCFGR_ODD`		24	Odd factor for the prescaler
`SPI_I2SCFGR_MCKOE`		25	Master Clock Output Enable

FDCAN — FDCAN (section 19)

Register	Offset	Bits	Purpose
`CREL`	`0x00`	32	FDCAN Core Release register
`FDCAN_CREL_DAY`		0:7	Timestamp Day
`FDCAN_CREL_MON`		8:15	Timestamp Month
`FDCAN_CREL_YEAR`		16:19	Timestamp Year
`FDCAN_CREL_SUBSTEP`		20:23	Sub-step of Core release
`FDCAN_CREL_STEP`		24:27	Step of Core release
`FDCAN_CREL_REL`		28:31	Core release
`ENDN`	`0x04`	32	FDCAN Endian register
`FDCAN_ENDN_ETV`		0:31	Endianness Test Value
`DBTP`	`0x0C`	32	FDCAN Data Bit Timing & Prescaler register
`FDCAN_DBTP_DSJW`		0:3	Synchronization Jump Width
`FDCAN_DBTP_DTSEG2`		4:7	Data time segment after sample point
`FDCAN_DBTP_DTSEG1`		8:12	Data time segment before sample point
`FDCAN_DBTP_DBRP`		16:20	Data BIt Rate Prescaler
`FDCAN_DBTP_TDC`		23	Transceiver Delay Compensation
`TEST`	`0x10`	32	FDCAN Test register
`FDCAN_TEST_LBCK`		4	Loop Back mode
`FDCAN_TEST_TX`		5:6	Control of Transmit Pin
`FDCAN_TEST_RX`		7	Receive Pin
`RWD`	`0x14`	32	FDCAN RAM Watchdog register
`FDCAN_RWD_WDC`		0:7	Watchdog configuration
`FDCAN_RWD_WDV`		8:15	Watchdog value
`CCCR`	`0x18`	32	FDCAN CC Control register
`FDCAN_CCCR_INIT`		0	Initialization
`FDCAN_CCCR_CCE`		1	Configuration Change Enable
`FDCAN_CCCR_ASM`		2	ASM Restricted Operation Mode
`FDCAN_CCCR_CSA`		3	Clock Stop Acknowledge
`FDCAN_CCCR_CSR`		4	Clock Stop Request
`FDCAN_CCCR_MON`		5	Bus Monitoring Mode
`FDCAN_CCCR_DAR`		6	Disable Automatic Retransmission
`FDCAN_CCCR_TEST`		7	Test Mode Enable
`FDCAN_CCCR_FDOE`		8	FD Operation Enable
`FDCAN_CCCR_BRSE`		9	FDCAN Bit Rate Switching
`FDCAN_CCCR_PXHD`		12	Protocol Exception Handling Disable
`FDCAN_CCCR_EFBI`		13	Edge Filtering during Bus Integration
`FDCAN_CCCR_TXP`		14	Two CAN bit times Pause
`FDCAN_CCCR_NISO`		15	Non ISO Operation
`NBTP`	`0x1C`	32	FDCAN Nominal Bit Timing & Prescaler register
`FDCAN_NBTP_NTSEG2`		0:6	Nominal Time segment after sample point
`FDCAN_NBTP_NTSEG1`		8:15	Nominal Time segment before sample point
`FDCAN_NBTP_NBRP`		16:24	Bit Rate Prescaler
`FDCAN_NBTP_NSJW`		25:31	Nominal (Re)Synchronization Jump Width
`TSCC`	`0x20`	32	FDCAN Timestamp Counter Configuration register
`FDCAN_TSCC_TSS`		0:1	Timestamp Select
`FDCAN_TSCC_TCP`		16:19	Timestamp Counter Prescaler
`TSCV`	`0x24`	32	FDCAN Timestamp Counter Value register
`FDCAN_TSCV_TSC`		0:15	Timestamp Counter
`TOCC`	`0x28`	32	FDCAN Timeout Counter Configuration register
`FDCAN_TOCC_ETOC`		0	Enable Timeout Counter
`FDCAN_TOCC_TOS`		1:2	Timeout Select
`FDCAN_TOCC_TOP`		16:31	Timeout Period
`TOCV`	`0x2C`	32	FDCAN Timeout Counter Value register
`FDCAN_TOCV_TOC`		0:15	Timeout Counter
`ECR`	`0x40`	32	FDCAN Error Counter register
`FDCAN_ECR_TEC`		0:7	Transmit Error Counter
`FDCAN_ECR_REC`		8:14	Receive Error Counter
`FDCAN_ECR_RP`		15	Receive Error Passive
`FDCAN_ECR_CEL`		16:23	CAN Error Logging
`PSR`	`0x44`	32	FDCAN Protocol Status register
`FDCAN_PSR_LEC`		0:2	Last Error Code
`FDCAN_PSR_ACT`		3:4	Activity
`FDCAN_PSR_EP`		5	Error Passive
`FDCAN_PSR_EW`		6	Warning Status
`FDCAN_PSR_BO`		7	Bus_Off Status
`FDCAN_PSR_DLEC`		8:10	Data Last Error Code
`FDCAN_PSR_RESI`		11	ESI flag of last received FDCAN Message
`FDCAN_PSR_RBRS`		12	BRS flag of last received FDCAN Message
`FDCAN_PSR_REDL`		13	Received FDCAN Message
`FDCAN_PSR_PXE`		14	Protocol Exception Event
`FDCAN_PSR_TDCV`		16:22	Transmitter Delay Compensation Value
`TDCR`	`0x48`	32	FDCAN Transmitter Delay Compensation register
`FDCAN_TDCR_TDCF`		0:6	Transmitter Delay Compensation Filter
`FDCAN_TDCR_TDCO`		8:14	Transmitter Delay Compensation Offset
`IR`	`0x50`	32	FDCAN Interrupt register
`FDCAN_IR_RF0N`		0	Rx FIFO 0 New Message
`FDCAN_IR_RF0F`		1	Rx FIFO 0 Full
`FDCAN_IR_RF0L`		2	Rx FIFO 0 Message Lost
`FDCAN_IR_RF1N`		3	Rx FIFO 1 New Message
`FDCAN_IR_RF1F`		4	Rx FIFO 1 Full
`FDCAN_IR_RF1L`		5	Rx FIFO 1 Message Lost
`FDCAN_IR_HPM`		6	High Priority Message
`FDCAN_IR_TC`		7	Transmission Completed
`FDCAN_IR_TCF`		8	Transmission Cancellation Finished
`FDCAN_IR_TFE`		9	Tx FIFO Empty
`FDCAN_IR_TEFN`		10	Tx Event FIFO New Entry
`FDCAN_IR_TEFF`		11	Tx Event FIFO Full
`FDCAN_IR_TEFL`		12	Tx Event FIFO Element Lost
`FDCAN_IR_TSW`		13	Timestamp Wraparound
`FDCAN_IR_MRAF`		14	Message RAM Access Failure
`FDCAN_IR_TOO`		15	Timeout Occurred
`FDCAN_IR_ELO`		16	Error Logging Overflow
`FDCAN_IR_EP`		17	Error Passive
`FDCAN_IR_EW`		18	Warning Status
`FDCAN_IR_BO`		19	Bus_Off Status
`FDCAN_IR_WDI`		20	Watchdog Interrupt
`FDCAN_IR_PEA`		21	Protocol Error in Arbitration Phase
`FDCAN_IR_PED`		22	Protocol Error in Data Phase
`FDCAN_IR_ARA`		23	Access to Reserved Address
`IE`	`0x54`	32	FDCAN Interrupt Enable register
`FDCAN_IE_RF0NE`		0	Rx FIFO 0 New Message Enable
`FDCAN_IE_RF0FE`		1	Rx FIFO 0 Full Enable
`FDCAN_IE_RF0LE`		2	Rx FIFO 0 Message Lost Enable
`FDCAN_IE_RF1NE`		3	Rx FIFO 1 New Message Enable
`FDCAN_IE_RF1FE`		4	Rx FIFO 1 Full Enable
`FDCAN_IE_RF1LE`		5	Rx FIFO 1 Message Lost Enable
`FDCAN_IE_HPME`		6	High Priority Message Enable
`FDCAN_IE_TCE`		7	Transmission Completed Enable
`FDCAN_IE_TCFE`		8	Transmission Cancellation Finished Enable
`FDCAN_IE_TFEE`		9	Tx FIFO Empty Enable
`FDCAN_IE_TEFNE`		10	Tx Event FIFO New Entry Enable
`FDCAN_IE_TEFFE`		11	Tx Event FIFO Full Enable
`FDCAN_IE_TEFLE`		12	Tx Event FIFO Element Lost Enable
`FDCAN_IE_TSWE`		13	Timestamp Wraparound Enable
`FDCAN_IE_MRAFE`		14	Message RAM Access Failure Enable
`FDCAN_IE_TOOE`		15	Timeout Occurred Enable
`FDCAN_IE_ELOE`		16	Error Logging Overflow Enable
`FDCAN_IE_EPE`		17	Error Passive Enable
`FDCAN_IE_EWE`		18	Warning Status Enable
`FDCAN_IE_BOE`		19	Bus_Off Status Enable
`FDCAN_IE_WDIE`		20	Watchdog Interrupt Enable
`FDCAN_IE_PEAE`		21	Protocol Error in Arbitration Phase Enable
`FDCAN_IE_PEDE`		22	Protocol Error in Data Phase Enable
`FDCAN_IE_ARAE`		23	Access to Reserved Address Enable
`ILS`	`0x58`	32	FDCAN Interrupt Line Select register
`FDCAN_ILS_RXFIFO0`		0
`FDCAN_ILS_RXFIFO1`		1
`FDCAN_ILS_SMSG`		2
`FDCAN_ILS_TFERR`		3
`FDCAN_ILS_MISC`		4
`FDCAN_ILS_BERR`		5
`FDCAN_ILS_PERR`		6
`ILE`	`0x5C`	32	FDCAN Interrupt Line Enable register
`FDCAN_ILE_EINT0`		0	Enable Interrupt Line 0
`FDCAN_ILE_EINT1`		1	Enable Interrupt Line 1
`RXGFC`	`0x80`	32	FDCAN Global Filter Configuration register
`FDCAN_RXGFC_RRFE`		0	Reject Remote Frames Extended
`FDCAN_RXGFC_RRFS`		1	Reject Remote Frames Standard
`FDCAN_RXGFC_ANFE`		2:3	Accept Non-matching Frames Extended
`FDCAN_RXGFC_ANFS`		4:5	Accept Non-matching Frames Standard
`FDCAN_RXGFC_F1OM`		8	FIFO 1 operation mode
`FDCAN_RXGFC_F0OM`		9	FIFO 0 operation mode
`FDCAN_RXGFC_LSS`		16:20	List Size Standard
`FDCAN_RXGFC_LSE`		24:27	List Size Extended
`XIDAM`	`0x84`	32	FDCAN Extended ID AND Mask register
`FDCAN_XIDAM_EIDM`		0:28	Extended ID Mask
`HPMS`	`0x88`	32	FDCAN High Priority Message Status register
`FDCAN_HPMS_BIDX`		0:2	Buffer Index
`FDCAN_HPMS_MSI`		6:7	Message Storage Indicator
`FDCAN_HPMS_FIDX`		8:12	Filter Index
`FDCAN_HPMS_FLST`		15	Filter List
`RXF0S`	`0x90`	32	FDCAN Rx FIFO 0 Status register
`FDCAN_RXF0S_F0FL`		0:3	Rx FIFO 0 Fill Level
`FDCAN_RXF0S_F0GI`		8:9	Rx FIFO 0 Get Index
`FDCAN_RXF0S_F0PI`		16:17	Rx FIFO 0 Put Index
`FDCAN_RXF0S_F0F`		24	Rx FIFO 0 Full
`FDCAN_RXF0S_RF0L`		25	Rx FIFO 0 Message Lost
`RXF0A`	`0x94`	32	FDCAN Rx FIFO 0 Acknowledge register
`FDCAN_RXF0A_F0AI`		0:2	Rx FIFO 0 Acknowledge Index
`RXF1S`	`0x98`	32	FDCAN Rx FIFO 1 Status register
`FDCAN_RXF1S_F1FL`		0:3	Rx FIFO 1 Fill Level
`FDCAN_RXF1S_F1GI`		8:9	Rx FIFO 1 Get Index
`FDCAN_RXF1S_F1PI`		16:17	Rx FIFO 1 Put Index
`FDCAN_RXF1S_F1F`		24	Rx FIFO 1 Full
`FDCAN_RXF1S_RF1L`		25	Rx FIFO 1 Message Lost
`RXF1A`	`0x9C`	32	FDCAN Rx FIFO 1 Acknowledge register
`FDCAN_RXF1A_F1AI`		0:2	Rx FIFO 1 Acknowledge Index
`TXBC`	`0xC0`	32	FDCAN Tx Buffer Configuration register
`FDCAN_TXBC_TFQM`		24	Tx FIFO/Queue Mode
`TXFQS`	`0xC4`	32	FDCAN Tx FIFO/Queue Status register
`FDCAN_TXFQS_TFFL`		0:2	Tx FIFO Free Level
`FDCAN_TXFQS_TFGI`		8:9	Tx FIFO Get Index
`FDCAN_TXFQS_TFQPI`		16:17	Tx FIFO/Queue Put Index
`FDCAN_TXFQS_TFQF`		21	Tx FIFO/Queue Full
`TXBRP`	`0xC8`	32	FDCAN Tx Buffer Request Pending register
`FDCAN_TXBRP_TRP`		0:2	Transmission Request Pending
`TXBAR`	`0xCC`	32	FDCAN Tx Buffer Add Request register
`FDCAN_TXBAR_AR`		0:2	Add Request
`TXBCR`	`0xD0`	32	FDCAN Tx Buffer Cancellation Request register
`FDCAN_TXBCR_CR`		0:2	Cancellation Request
`TXBTO`	`0xD4`	32	FDCAN Tx Buffer Transmission Occurred register
`FDCAN_TXBTO_TO`		0:2	Transmission Occurred
`TXBCF`	`0xD8`	32	FDCAN Tx Buffer Cancellation Finished register
`FDCAN_TXBCF_CF`		0:2	Cancellation Finished
`TXBTIE`	`0xDC`	32	FDCAN Tx Buffer Transmission Interrupt Enable register
`FDCAN_TXBTIE_TIE`		0:2	Transmission Interrupt Enable
`TXBCIE`	`0xE0`	32	FDCAN Tx Buffer Cancellation Finished Interrupt Enable register
`FDCAN_TXBCIE_CFIE`		0:2	Cancellation Finished Interrupt Enable
`TXEFS`	`0xE4`	32	FDCAN Tx Event FIFO Status register
`FDCAN_TXEFS_EFFL`		0:2	Event FIFO Fill Level
`FDCAN_TXEFS_EFGI`		8:9	Event FIFO Get Index
`FDCAN_TXEFS_EFPI`		16:17	Event FIFO Put Index
`FDCAN_TXEFS_EFF`		24	Event FIFO Full
`FDCAN_TXEFS_TEFL`		25	Tx Event FIFO Element Lost
`TXEFA`	`0xE8`	32	FDCAN Tx Event FIFO Acknowledge register
`FDCAN_TXEFA_EFAI`		0:1	Event FIFO Acknowledge Index

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